Oct 30 Announcements Code Marked and on Blackboard This week: Mon 2:30 to 3:00pm, Tues 2:30 to 3:30 and W-F 1:30 to 3:00pm opportunity to talk about code: earn 2 extra points on the coding part Bonus marked will be posted today Will provide 270 style feedback on multiple-choice questions. [3.E]-1
Module 3.E Pulse Width Modulation (PWM) Tim Rogers 2017
Learning Outcome #3 An ability to effectively utilize the wide variety of peripherals integrated into a contemporary microcontroller How? A: Clocks and Real Time Interrupt (RTI) B: Analog-to-Digital Converter (ATD) C: Serial Peripheral Interface (SPI) D: Timer Module (TIM) E: Pulse Width Modulation (PWM) F: Serial Communications Interface (SCI) [3.E]-3
PWM Function Relatively simple Outputs a digital waveform (i.e. either 0 or 1), with a specific frequency and duty cycle. All of these waves have the same frequency. PWM allows you to program both duty cycle and frequency [3.E]-4
PWM applications D.C Motor speed control LED backlight intensity Useful for varying power delivery in digital systems Digital-to-analog conversion (w/ low-pass filter) [3.E]-5
PWM encoding an analog signal Referred to as natural sampling which is different than pulsecode modulation (PCM) Can be thought of as a one-bit A/D encoding system. The sampling frequency must be at least an order of magnitude higher than the highest frequency component of the input signal. The PWM output can be low-pass filtered to re-construct the analog signal. [3.E]-6
PWM Encoding + Signal Reconstruction low-pass filter [3.E]-7
In lab You will sample a signal with the ATD. Then use the PWM + low-pass filter to reconstruct the signal. This analog signal creation is how audio signals typically get created in mini-projects [3.E]-8
9S12C PWM Features 6 independent channels with programmable period and duty cycle 8-bit resolution (6-channel mode) or 16-bit resolution (3-channel mode) Flexible clock generation wide range of sampling frequencies Period and duty cycle registers are double-buffered (allows immediate PWM update) Output pulse polarity and alignment are programmable Emergency shutdown capability [3.E]-9
Double Buffer One example: Video games Once screen is fully drawn, kick to display Back Buffer Visible Display Buffer CPU/GPUs generate new frames by clearing screen, then redrawing [3.E]-10
Double Buffer PWM Example Kick new period/duty after current period ends What if you are midperiod when you update the duty register? Back period register Period register Back duty register Duty register CPU Writes the new duty/period to the back register [3.E]-11
Double Buffer PWM Example Kick new period/duty after current period ends What if you are midperiod when you update the duty register? Back period register Period register Back duty register Duty register [3.E]-12
PWM Module User Guide https://engineering.purdue.edu/ece362/refs/9s12c_refs/s12pwm8 B6CV1.pdf [3.E]-13
PWM Block Diagram [3.E]-14
Key Registers Enable bit per channel. 0=off 1=on Polarity bit per channel. 0=Active low 1=Active high [3.E]-15
Key Registers One 8-bit PWMPER/Channel. PWM cycles in one period. One 8-bit PWMDTY/Channel PWM cycles in asserted (i.e. low if PPOL=0, high if PPOL=1) [3.E]-16
PWM Boundary Conditions 17
Polarity Select and Duty Cycle Duty Cycle (%) = 100 * (PWMDTY)/(PWMPER) Sampling Frequency = (Input Clock)/(PWMPER) Left Aligned Mode (default) 18
PWM Clock Selection Diagram 19
PWM Clock Selection Diagram Pre-scale divisor range is 1 to 128 Clock source is the BUS CLOCK 20
PWM Registers l PWMPRCLK (prescale clock select) PCKB2- PCKB0 (bits 6-4) Clock B prescaler PCKA2-PCKA0 (bits 2-0) Clock A prescaler 000 bus clock 001 bus clock/2 010 bus clock/4 011 bus clock/8 100 bus clock/16 101 bus clock/32 110 bus clock/64 111 bus clock/128 indicates default mode after RESET 21
Clock A is the pre-scaled bus clock, and Clock SA is the scaled Clock A In general: N = D/2 where N is the value to load in PWSCALA for clock divisor D Note that the range of SA is from A/2 to A/512 PWM Channels 0, 1, 4, and 5 can select either Clock A or Clock SA 22
PWM Registers l PWMCLK (clock source select) PCLK5 (bit 5) channel 5 clock select 0 use Clock A 1 use Clock SA PCLK4 (bit 4) channel 4 clock select 0 use Clock A 1 use Clock SA indicates default mode after RESET 23
PWM Registers l PWMCLK (clock source select) PCLK1 (bit 1) channel 1 clock select 0 use Clock A 1 use Clock SA PCLK0 (bit 0) channel 0 clock select 0 use Clock A 1 use Clock SA indicates default mode after RESET 24
PWM Registers l PWMSCLA (Scale A Register) 8-bit programmable scale value for Clock A Clock SA = Clock A / (2 * PWMSCLA) $00 is used to represent 256 10 25
Clock B is the pre-scaled bus clock, and Clock SB is the scaled Clock B In general: N = D/2 where N is the value to load in PWSCALB for clock divisor D Note that the range of SB is from B/2 to B/512 PWM Channels 2 and 3 can select either Clock B or Clock SB 26
PWM Registers l PWMCLK (clock source select) PCLK3 (bit 3) channel 3 clock select 0 use Clock B 1 use Clock SB PCLK2 (bit 2) channel 2 clock select 0 use Clock B 1 use Clock SB indicates default mode after RESET 27
PWM Registers l PWMSCLB (Scale B Register) 8-bit programmable scale value for Clock B Clock SB = Clock B / (2 * PWMSCLB) $00 used to represent 256 10 28
16-bit PWM Mode In 16-bit ( concatenated ) mode, the lower numbered channel is the high byte 29
PWM Registers l PWMCTL (PWM control) CON45 (bit 6) concatenate chs 4 & 5 0 channels 4 & 5 separate 8-bit 1 channels 4 & 5 concatenated 16-bit CON23 (bit 5) concatenate chs 2 & 3 0 channels 2 & 3 separate 8-bit 1 channels 2 & 3 concatenated 16-bit CON01 (bit 4) concatenate chs 0 & 1 0 channels 0 & 1 separate 8-bit 1 channels 0 & 1 concatenated 16-bit indicates default mode after RESET 30
PWM Registers l PWMCAE (center align enable) CAEx (bit x) center align channel x 0 operate ch x in left-aligned mode 1 operate ch x in center-aligned mode Note: The center-aligned mode is useful for asynchronous motor control (e.g., for brushless DC motors) indicates default mode after RESET 31
Center-Aligned Mode Duty Cycle (%) = 100 * (PWMDTY)/(PWMPER) Sampling Frequency = (Input Clock)/(2* PWMPER) 32
PWM Registers l Port P (data register) bits 0-5 used for PWM output channels 0-5 PWM takes precedence over generalpurpose I/O when enabled l DDRP (data direction register) used to establish data direction of Port P bits when used for general-purpose I/O 33
1. Useful applications of the PWM include: A. D.C. motor speed control B. digital-to-analog conversion C. controlling the intensity of an LED D. all of the above E. none of the above 34
2. The double buffering feature of the PWM unit: A. prevents a PWM output from changing the instant the period or duty register is written B. provides a larger window of time during which the PWM registers can be written C. provides a larger window of time during which the PWM registers can be read D. all of the above E. none of the above 35
3. Given a 24 MHz bus clock, in 8-bit left-aligned mode the minimum frequency 50% duty cycle square wave that can be generated by the PWM unit is approximately: A. 0.15 Hz B. 1.50 Hz C. 15.00 Hz D. 150.0 Hz E. none of the above 36
4. Given a 24 MHz bus clock, in 8-bit left-aligned mode the maximum frequency 50% duty cycle square wave that can be generated by the PWM unit is: A. 12,000 Hz B. 120,000 Hz C. 1,200,000 Hz D. 12,000,000 Hz E. 24,000,000 Hz 37
5. Given a 24 MHz system clock with PWMPRCLK = 0110 0000 2 and PWMCLK = 0000 0100 2, the following combination of PWM register initializations will produce a 100 Hz (approx.), 50% duty cycle square wave on Channel 2 (assuming PWMPOL = 0000 0100 2 and PWMEN = 0000 0100 2 ): A. PWSCALB = 93 10, PMWPER2 = 20 10, PMWDTY2 = 10 10 B. PWSCALB = 186 10, PWMPER2 = 20 10, PWMDTY2 = 10 10 C. PWSCALB = 50 10, PWMPER2 = 100 10, PWMDTY2 = 50 10 D. PWSCALB = 49 10, PWMPER2 = 100 10, PWMDTY2 = 50 10 E. none of the above 38
PWM Initialization Example Assume the bus clock is 24 MHz and that the PWM is used to generate four left-aligned active high square wave signals: l Ch 0 120,000 Hz 10% duty cycle l Ch 1 20,000 Hz 30% duty cycle l Ch 2 7,500 Hz 70% duty cycle l Ch 3 250 Hz 85% duty cycle Determine the register initializations required to generate these four waveforms 39
PWM Initialization Example For Ch 0 (and Ch 1), need PWMPER = 100 to have a resolution of 1% in specifying the duty cycle need input clock frequency of at least 120,000 * 100 = 12 MHz (conveniently, this is half the 9S212C32 bus clock freq.) The scale register for Clock A can be used to produce the input clock for Ch 1, which is 20,000 * 100 = 2 MHz Clock SA = (Clock A)/6 PWSCALA = 3 40
PWM Initialization Example l PWME = $0F (enables PWM Chs 0-3) l PWMPER0 (ch 0 period) = 100 l PWMPER1 (ch 1 period) = 100 Will allow l PWMPER2 (ch 2 period) = 100 resolution of 1% l PWMPER3 (ch 3 period) = 100 the number of clock ticks that constitute one complete period of the PWM signal Leftaligned mode 100 41
PWM Initialization Example l PWMPOL = $0F (Chs 0-3 active high polarity) l PWMDTY0 (Ch 0 duty cycle) = 10 (10%) l PWMDTY1 (Ch 1 duty cycle) = 30 (30%) l PWMDTY2 (Ch 2 duty cycle) = 70 (70%) l PWMDTY3 (Ch 3 duty cycle) = 85 (85%) the number of clock ticks the PWM signal is asserted low (PPOL=0) or high (PPOL=1) Leftaligned mode 100 42
12 MHz PWM Clock Selection Diagram 24 MHz 3 2 MHz 43
PWM Initialization Example For Ch 2 (and Ch 3), again need PWMPER = 100 to have a resolution of 1% in specifying the duty cycle need input clock frequency of at least 7,500 * 100 = 750 KHz = 24 MHz / 32 The scale register for Clock B can be used to produce the input clock for Ch 3, which is 250 * 100 = 25 KHz Clock SB = (Clock B) / 30 PWSCALB = 15 44
12 MHz PWM Clock Selection Diagram 24 MHz 3 15 2 MHz 750 KHz 25 KHz 45
PWM Clock Selection Diagram 24 MHz 12 MHz 2 MHz 3 750 KHz 25 KHz 15 PWMPRCLK = x101 x001 46
PWM Clock Selection Diagram 24 MHz 12 MHz 2 MHz 3 750 KHz 25 KHz 15 PWMCLK = xxxx 1010 47
PWM Applications/Interfaces l Simple D/A converter (single pole LPF) PWM Port Pin A higher order (active) LPF can also be used the OP AMP provides isolation and additional output drive capability (not necessary if output load is high impedance) 48
PWM Applications/Interfaces l Driving a small loudspeaker VCC PWM Port Pin The loudspeaker will mechanically lowpass filter the PWM signal note that an arc suppression diode is needed because the loudspeaker voice coil is an inductive load 49
PWM Applications/Interfaces l Motor speed and direction control using an H -bridge (here, a pair of half-h bridges) Output Port Pin PWM Port Pin 50
H Bridge V+ V+ motor V- V- 51
H Bridge V+ V+ + - motor V- V- 52
H Bridge V+ V+ - + motor V- V- 53
;************************************ ; Analyze the following code ;************************************ ; ; initialize PWM Ch 0 movb #$01,MODRR ; PT0 used as PWM Ch 0 output movb #$01,PWME ; enable PWM Ch 0 movb #$01,PWMPOL ; set active high polarity E. none of the above movb #$00,PWMCTL ; no concatenate (8-bit) movb #$00,PWMCAE ; left-aligned output mode movb #$FF,PWMPER0 ; set maximum 8-bit period (255) movb #$7F,PWMDTY0 ; set 50% duty cycle movb #$07,PWMPRCLK ; set Clock A = 24 MHz / 128 (max pre-scalar) movb #$01,PWMCLK ; select Clock SA for Ch 0 movb #$00,PWMSCLA ; set Clock SA scalar to 512 (max scalar) ; initialize TIM Ch 1 ASM version movb #$80,tscr1 ; enable TC1 movb #$07,tscr2 ; set TIM pre-scale factor to 128 (max) movb #$02,tios ; set TIM TC1 for Output Compare mode movw #$0004,tctl1 ; toggle PT1 on successful output compare movw #$0000,tc1 ; value for OC1 Increasing The PT1 PT0 the toggle and value PT1 rate loaded toggle (i.e., into rates period, TC1 could (relative in ms) be for made to the its to code be current as identical written value (i.e., will of $0000) exactly be approximately: would: in sync) by: A. A. do 1.36 changing nothing ms the except value change in PWMDTY0 the (initial) to $80 relative B. phase 2.73 350 changing ms of the PT0 value and in PWMPER0 PT1 port pin to toggling $00 P B. C. increase changing 696 ms P the PT1 value port in PWMSCLA pin toggle rate to $01 C. D. decrease changing 699 ms P the PT1 value port in TC1 pin toggle $0100 rate D. E. disable none of port the above pin PT1 P from toggling eloop bra eloop ; infinite (do-nothing) loop 54
/* Timer Channel 1 initialization */ TSCR2 = 0x07; // set TIM prescale to 128 TIOS = 0x02; // set TIM Channel 1 for output compare mode TCTL2 = 0x04; // toggle PT1 on successful output compare TC1 = 0x0000; // TCNT value that triggers output compare C version /* PWM Channel 0 initialization */ MODRR = 0x01; // route PWM Channel 0 to PT0 PWMCTL = 0x00; // no-concatenate (8-bit mode) PWMPOL = 0x01; // select active high polarity PWMCAE = 0x00; // select left-aligned output PWMPER0 = 0xFF; // maximum period = 255 PWMDTY0 = 0x7F; // approx 50% duty cycle PWMPRCLK = 0x07; // maximum pre-scalar = 128 PWMCLK = 0x01; // select scaled clock PWMSCLA = 0x00; // maximum scale value = 512 /* enable timer and PWM */ TSCR1 = 0x80; PWME = 0x01; // enable TIM (output on PT1) // enable PWM (output on PT0) /* main (infinite) loop */ for(;;) { } 55