Chapter 4 Junction Field Effect Transistor Theory and Applications 4.0 ntroduction Like bipolar junction transistor, junction field effect transistor JFET is also a three-terinal device but it is a unipolar device, which shall ean that the current is ade of either electron or hole carrier. The operation of JFET is controlled by electric field effect. Thus, JFET is a voltae-controlled current source device, whereas BJT is a current-controlled source device. There are two types of JFET naely n-channel and p-channel. n-channel type eans the carrier type in the conductin channel is electron. Likewise, for p-channel type, the carrier type in conductin channel is hole. JFET has three terinals, which are ate G, drain and source S. The ate is used to control the flow of carrier fro source to drain. Source is the terinal that eits carrier and the drain is the terinal that receives carrier. The structures of n-channel and p-channel JFET are shown in Fi. 4.1. (a) n-channel JFET (b) p-channel JFET Fiure 4.1: The structures of n-channel and p-channel - 111 -
The sybols of n-channel and p-channel JFETs are shown in Fi. 4.. (a) n-channel JFET (b) p-channel JFET Fiure 4.: Sybols of n-channel and p-channel JFET 4.1 Biasin the JFET n noral operation, the ate of JFET is always reverse-biased. Thus, an n- channel type, the ate is biased with neative voltae i.e. ate voltae is less than zero volt G < 0, whilst for p-channel type, the ate is biased with positive voltae i.e. ate voltae is reater than zero voltae G > 0. The source and drain are biased accordin to the channel type or carrier type. f it is an n-channel JFET (electron as carrier), the source is biased with neative voltae while the drain is biased with positive voltae. Alternatively, it can be biased such that the drain voltae is reater than the source voltae S. i.e. > S. f it is a p-channel JFET (hole as carrier), the source is biased with positive voltae while the drain is biased with neative voltae. Alternatively, it can be biased such that the drain voltae is less than the source voltae S. i.e. < S. Fiure 4.3 shows the bias condition for an n-channel JFET. - 11 -
Fiure 4.3: Bias connection for n-channel JFET 4. JFET Characteristics and Paraeters Fiure 4.4 shows the drain current characteristics of a JFET for ate-to-source voltae equal to 0. i.e. GS = 0. Fiure 4.4: JFET drain characteristics curve for GS = 0-113 -
Between point A and B, it is the ohic reion of the JFET. t is the reion where the voltae and current relationship follows oh's law. At point B, the drain current is at axiu for GS = 0 condition and is defined as SS. t is the pinch-off point, where there is no increase of current as drain-to-source voltae S is further increased. The S voltae at this point is called pinch-off voltae P. t is also the voltae point where drain-to-ate voltae G produces enouh depletion thickness to narrow the channel so that the resistance of the channel will increase sinificantly. Since GS = 0, S is also equal to G. Thus, in eneral the pinch-off voltae p is p = S(P) - GS (4.1) where S(P) is the pinch-off drain-to-source voltae for a GS value. SS and P are constant values listed by the anufacturer for a iven JFET type, which are the drain current and pinch-off voltae at ate-to-source voltae GS = 0. At point C, the JFET beins to breakdown where the increases rapidly and it is an irreversible breakdown. ifferent value of GS produces different drain characteristic curve. For n- channel JFET, as GS decreases, current and S(P) decreases. There is a GS value that no drain current is reistered irrespective of the drain-source voltae S. This ate-to-source voltae GS is the cutoff ate-to-source voltae GS(off). Since there is no current, S ust be zero. Thus, fro equation (4.1) GS = - P. Equation (4.1) can also now be written as S(P) = GS GS(off). Fiure 4.5: rain characteristics of n-channel JFET of different GS - 114 -
At ohic reion of the drain characteristic curve for n-channel type follows equation (4.a), which is W = AqN µ ne X = bqn µ n S (4.a) L where A is the effective cross sectional area of the channel for a iven GS voltae and b is the effective channel width for a iven ate-to-source voltae and zero drain current. At ate-to-source voltae equals to zero volt i.e. GS = 0 volt, the effective channel width b is equal to h. Thus, the channel on-resistance is defined as r = 1 ( ) hqn µ S on n L W The pinch-off curve follows equation (4.b), which is. S(P) = SS 1 (4.b) P Fiure 4.6 shows the set-up for obtainin cut-off condition whereby the drain current is equal to zero. Fiure 4.6: Condition for cutoff of an n-channel JFET - 115 -
Exaple 4.1 For the JFET circuit shown in the fiure, P = 8.0 and SS = 1.0A. (a) eterine the value of S when pinch-off beins. (b) f the ate is rounded, what is the value of for = 1.0 when S is above pinch-off? Solution Fro the circuit, GS = -5 and apply equation (4.1), S(P) = P + GS = 8 + (-5) = 3 The S voltae when pinch-off occurred is 3.0. When the ate is rounded, GS = 0, the drain current is equal to SS = 1A. For any value of drain-to-source voltae S above pinch-off voltae of 8, the drain current reains as SS = 1.0A. This is true as lon as the drain-to-source voltae S is below breakdown voltae. 4..1 Transfer Characteristics The transfer characteristic of an n-channel JFET is shown in Fi. 4.7. At ateto-source voltae GS = 0, the drain current is equal to SS and at ate-tosource voltae GS(off), drain current = 0. - 116 -
Fiure 4.7: Transfer characteristics curve of an n-channel JFET The curve is a parabolic curve, which can be expressed atheatically as = SS 1 GS GS( off ) (4.3) 4.. Forward Transconductance The forward transconductance of the JFET is defined as the chane of drain current for a iven chane in ate-source voltae GS and it is expressed as = GS (4.4) Fro the transfer characteristic curve, one will realize that the transconductance of the device is at axiu when GS is at zero voltae. The value of at GS = 0 is always iven in the anufacturer data sheet of the device, which is denoted as 0. f 0 is iven, for a iven GS can be calculated fro equation (4.5). - 117 -
= GS 1 0 GS( off ) (4.5) Equation (4.5) can be derived fro equation (4.4) by differentiatin drain current with respect to ate-to-source voltae i.e. d /d GS. d SS = = 1 dgs GS Off GS ( ) GS( off ) (4.6) Coparin equation (4.5) and (4.6), 0 shall be 0 = SS GS( off ) (4.7) Thus, iven the values of SS and GS(off), the transconductance of the device at GS = 0 can be deterined. Fro equation (4.3) and (4.5), transconductance can be expressed as = 0 / SS (4.8) Thus, the transconductance of JFET for a iven drain current value, can be obtained. 4..3 nput pedance Since the ate of JFET is reverse-biased, the input ipedance is very hih. This is one advantae of JFET over bipolar junction transistor. n JFET data sheet, the input ipedance is iven by ate reverse current GSS for a iven ate-source voltae GS. Thus, input ipedance can be expressed as R GS N( ate) = (4.9) GSS 4.3 dc Biasin JFET The purpose of biasin the device is to select the riht dc ate-to-source voltae for the JFET in order to establish a desired value of drain current. Listed here are soe standard ethods. - 118 -
4.3.1 Self-Biasin of JFET 4 Junction Field Effect Transistor Theory and Applications The self-biasin circuits for n-channel and p-channel JFET are shown in Fi. 4.8. The ate of the JFET is connected to the round via a ate resistor R G. (a) n-channel JFET (b) p-channel JFET Fiure 4.8: Self-biasin of JFET The ate voltae G is closed to zero since the voltae dropped across R G by GSS can be inored. Thus, GS = G - S (4.10) Fro Fi. 4.8(a), S = R S and G = 0 GS = 0 - R S and GS = + R S for p-channel JFET The drain-source voltae S is S = - S = - R - R S = - (R + R S ) (4.11) - 119 -
As entioned earlier, the purpose of biasin is to select the riht dc ate-source voltae for the JFET to establish a desired value of drain current. Once it is established. The source resistance R S can be calculated usin equation (4.1). R S = GS (4.1) Exaple 4. eterine the value of R S required to self-bias an n-channel JFET with SS = 5A, GS(off) = -10, GS = -5 and its transconductance. Solution rain current at ate-to-source GS = -5 is = SS 1 The source resistance R S is GS GS( off ) = 5A 1 5 6 5 10 =. A R S = GS 5 = = 800Ω 6. 5A Transconductance at GS = 0, 0 = SS GS( off ) x5a = = 5A / 10 Thus, the transconductance at = 6.5A is, = 0 / SS =5A / 6. 5A 5 A =. 5A / 4.3. Mid-point Bias The purpose of idpoint bias is to allow axiu drain current swin. Fro the drain transfer characteristic curve, the idpoint bias occurred at drain current corresponds to SS / and at approxiately ate-to-source voltae GS equals to GS(off) /4. ndeed when drain current equals to = SS /, ate-tosource voltae is GS = 0.9 tie of ate-to-source cutoff voltae GS(off). The illustration is shown in Fi. 4.9. - 10 -
Fiure 4.9: The transfer characteristic curve showin idpoint-bias values for JFET 4.3.3 oltae ivider Bias An n-channel JFET with voltae-divider bias is shown in Fi. 4.10. The voltae at the source of the JFET ust be ore positive than the voltae at the ate in order to keep the ate-source junction reverse-biased. The source voltae S is S = R S (4.13) The ate voltae G is set by resistors R 1 and R and is expressed by the followin equation usin voltae-divider concept. G R = R + R 1 (4.14) The ate-to-source voltae GS is GS = G - S - 11 -
Thus, GS = R R R + 1 - R S (4.15) S = - (R +R S ) (4.16) and = G R S GS (4.17) Fiure 4.10: An n-channel JFET voltae-divider bias circuit Exaple 4. 3 eterine the dc Q-point of the aplifier shown in fiure and draw its dc load line. Given the SS and GS(off) of JFET are 0A and - 4.0 respectively. - 1 -
Solution Since R N(ate) is extreely lare, it does not cause any sinificant effect to ate resistor R G. Usin equation (4.3) = A 15. 0 1 = 7. 8A 4 oltae drop across drain-source S = - x 1kΩ = 0-1kΩ x 7.8A = 1. Maxiu = SS = 0A and S at cutoff, S(cutoff) = 0. Fro the results above, the Q (quiescent)-point and dc load line are drawn and shown in Fi. 4.11. - 13 -
Fiure 4.11: The raph shows the dc load line and Q-point of the aplifier shown in Fi. 4.10 Exaple 4.4 eterine the approxiate Q-point for the JFET biased with a voltae divider circuit as shown in the fiure, iven that the particular device has transfer characteristic curve as shown. Solution Fro equation (4.13), for drain current = 0A, the ate-to-source voltae GS is GS = G = R R R = + 1. MΩ 8. MΩ +. MΩ = 4.0 Fro Equation (4.15), for GS = 0, the drain current is = R G S = 4/3.3kΩ = 1.A - 14 -
Fro raphic plot, for Q-point is 1.8A. Thus, fro equation (4.14) S = - (R +R S ) - 15 -
= 8-1.8A(680Ω + 3.3kΩ) = 0.83 4.4 Sall Sinal Aplifier n this Section, the JFET is confiured such that it works as a sall-sinal aplifier. arious ethods of biasin confiuration such coon-drain, coon-ate, and coon-source confiurations will be studied includin its erit and deerit points. The aplification can be achieved fro n-channel JFET transfer characteristic and drain curves as they are shown in Fi. 4.1 and Fi. 4.13 respectively. Siilarly, aplification can be achieved for p-channel JFET device. As shown in Fi. 4.1, a sall chane of ate-to-source voltae GS can result a lare chane of drain current. Fiure 4.1: Transfer characteristic curve of n-channel JFET showin sinal aplification Siilarly, once can see that the above-entioned chane would also show in the chane of drain-to-source voltae S as shown in Fi. 4.13. - 16 -
Like in the case of bipolar junction transistor, the Q-point of the aplifier should be desined to set at the linear reion of the transfer characteristic curve to avoid non-linearity distortion. Fiure 4.13: rain curve of n-channel JFET showin sinal aplification Equation (4.4) defines dc transconductance as transconductance is defined as current is d = s. 4.4.1 Equivalent Circuits of FET =. Thus, ac GS d =. By rearranin the equation, ac drain s The hybrid π-odel equivalent circuits of JFET are shown in Fi. 4.14. These circuits are applicable for JFET and MOSFET. The drain current d is equal to s ate-source resistance r s and output ipedance = r o are introduced as shown in Fi. 4.14(a). f ate-to-source resistance r s is assued to be infinitely lare and r O is lare enouh to be nelected, then the siplified equivalent circuit shall be Fi. 4.14(b). Output ipedance r o of the JFET can be deterined - 17 -
fro the Early voltae M and drain current usin equation r + M S M 0 =. (a) (b) Fiure 4.14: π-odel of JFET/MOSFET ac equivalent circuit The T-odel of the JFET device, which is also the odel for the MOSFET device, is shown in Fi. 4.15. The odel is derived based on the fact the ac source resistance R in(source) of the JFET/MOSFET is equal to R in(source) = s s = =. S s 1 Fiure 4.15: T-odel of JFET/MOSFET ac equivalent circuit - 18 -
4.4. oltae Gain The voltae ain A of the JFET with an external ac source as input is defined as A = out / in. For a self bias JFET aplifier, its ac equivalent circuit is shown in Fi. 4.16. Fiure 4.16: ac equivalent circuit Fro the circuit, the output voltae out is out = - ds = - d R and the input voltae in is in = s = d /. Thus, the voltae ain is equal to A = out / in is A d R = = R / d (4.18) 4.4.3 Effect of r o and R S f output ipedance r o of JFET is taken into consideration, the voltae ain A will be reduced to A = R ro R + r O (4.19) f there is a source resistance R S, where the ac equivalent circuit is shown in Fi. 4.17, voltae ain A is reduced further because input voltae in is not just equal to ate-to-source voltae s. The input voltae in is in = s + s R S R ro = s (1 + R S ). Since output voltae out is out = - s. Therefore, the ac voltae ain A is - 19 - R + r O
A = - R ro ( 1+ R ) R + r S O (4.0) Fiure 4.17: ac equivalent circuit with external source resistance R s 4.4.4 Coon-Source Aplifier Fiure 4.18 shows a coon-source aplifier and its correspondin ac equivalent circuit is shown in Fi. 4.19. Fiure 4.18: A coon source JFET aplifier - 130 -
Fiure 4.19: ac equivalent circuit of the coon source JFET aplifier f the dc circuit is biased at idpoint, then = SS /. Otherwise, needs to be known. Since it is self-bias then GS = - R S. Substitute GS into equation R S (4.3), it yields the drain current as = SS 1 +. Expandin the square GS(off ) ter of the equation, it yields drain current = SS R S R S 1 + +. GS(off ) GS(off ) ax bx + c = R R SS S 1 SS S SSR S SS + + = 0, whereby the coefficients are a = GS(off ), b GS(off ) GS(Off ) = SS R S 1, and c = SS respectively. Thus, drain-current is obtained fro GS(off ) Rearrane this quadratic equation in the fors of + 0, it becoes = b ± b a 4ac. t yields two values for drain current. One needs to consider the value of SS before the riht value of to be chosen. The drain current shall not be reater than SS current. The drain-to-source voltae S is obtained fro equation (4.1). S = - R - R S (4.1) The input ipedance of the ate is extreely hih so it can be nelected. However, if GSS and GS are iven then it can be calculated usin equation (4.9). - 131 -
4.4.5 Coon-rain Aplifier Fiure 4.0 shows a coon-drain aplifier. t is also called source-follower. Unlike the bipolar junction transistor coon-collector aplifier, it is called eitter-follower. The ac equivalent circuit of the aplifier is shown in Fi. 4.1. Fiure 4.0: A coon-drain aplifier Fiure 4.1: The ac equivalent circuit of the coon-drain aplifier - 13 -
As usual voltae ain A is A v = out / in. The input voltae in is in = s + d R S. The output voltae out is out = d R S. The voltae ain A shall then be equal to A = d R S /( s + d R S ). Recall that transconductance is = d / s. Substitutin drain current d equals to d = s, the voltae ain A shall be A = R S 1+ R S (4.) Thus, one can see that the ain is always less than one. f R s >> 1 then A v 1. The input ipedance of the ate R N(ate) is very hih and it can be calculated fro the ate reverse current GSS value for a specified GS value fro data sheet of the JFET usin equation (4.9). f these data are iven for a specified JFET then the input ipedance R N for the aplifier shall be R N(ate) parallel with ate resistance R G. 4.4.6 Coon-Gate Aplifier The coon-ate aplifier is shown in Fi. 4. and its correspondin ac equivalent circuit is shown in Fi. 4.3. Fiure 4.: A coon-ate aplifier - 133 -
Fiure 4.3: The equivalent circuit of the coon-ate aplifier The voltae ain A is A = - out / in and takin equation (4.4) for the drain current d, which is equal to s. The voltae ain shall be A v = - out / s = - d R / s = s d R / s = - R d (4.3) The input ipedance R in(source) = in / in. Since the input voltae in is in = s and in = d = s. The ac source resistance R in(source) shall be R in(source) = 1/ (4.4) Fro equation (4.4), it tells us that the input ipedance R in(source) is sall, which true because the source should have low ipedance. Exaple 4.5 Fro the circuit of coon source JFET aplifier shown in the fiure, its has GS(off) = -.0, SS = 1.4A. f you need this aplifier to be biased with = 0.7A, = 0, and voltae ain of 0dB, what is the value of R S, and R? - 134 -
Solution Usin equation (4.3), the drain current is GS = SS 1 = GS 0.7A 1.4A 1 GS(off ) =. Solvin this equation for ate-tosource voltae GS is yield equal to - 0.59. Fro equation (4.7), the transconductance at ate-to-source voltae equal to zero volt. i.e. GS = 0 is x1.4a. SS 0 = = = 1.4A / GS(off ).0 is Fro equation (4.8), the transconductance for drain current = 0.7A = 0 / SS = 1.4A / 0.7A = 0.99A /. 1.4A Fro equation (4.1), the source resistance is R S = GS / = 0.59/0.7A = 84.8Ω. oltae ain A of 0dB corresponds to absolute voltae ain A equal to 10. Fro equation (4.13), voltae ain A is A = R, then drain resistance R is R = A / =10/0.99A/ = 10.1kΩ. - 135 -
4.5 Multistae Aplifier The two-stae n-channel JFET aplifier is shown in Fi. 4.4. Recall the ultiple stae bipolar junction transistor aplifiers; the voltae ain of the first stae is decreased by the load effect created by the input ipedance of the followin stae. However, the input ipedance of each stae of ultistae JFET aplifier is very hih that it has little effect on the precedin stae and it can be nelected. Fiure 4.4: A two-stae JFET aplifier The drain current is found to be 3.36A. The transconductance shall then be.9s. Thus, the overall ain of this two-stae aplifier is A = A 1 A which is equal to (833µS)(1.5kΩ)(833µS)(1.5kΩ) = 18.9. n decibel it is A (db) = 0lo(18.9) = 5.5dB. - 136 -
Tutorials 4.1. escribe and draw the diaras to illustrate, how the n-channel and p- channel JFET should be biased for noral operation. 4.. The data sheet for certain type of JFET indicates that SS = 5A, GS(off) = -10, and 0 = 5000µS. eterine (i) The type of JFET (ii) rain current at GS = 0 (iii) rain current and transconductance at GS = - 4. 4.3. Given that prove that 0 SS GS = SS 1, GS(off ) GS GS(off ) =, and = and 0 / SS =. = GS 0 1, GS(off ) 4.4. An n-channel JFET has a pinch-off voltae P of 4.5 and SS = 9.0A. At what value of GS in the pinch-off reion will equal to 3.0A and what is the value of S(P) when = 3.0A? 4.5. Fro the circuit of coon source JFET aplifier shown in fiure, its has GS(off) = -.0, SS = 1.4A. f you need this aplifier to be biased with = 0.7A, = 0, and voltae ain of 0dB, what is the value of R S, and R? - 137 -
4.6. Given a coon drain JFET aplifier has GS(off) = -8.0, 0 = 6000µS, R 1 = R = 500kΩ, = 0, and C 1 = C = 0.1µF. (i) Calculate the values of output ipedance and input ipedance of the aplifier when ate-to-source voltae GS are -1.0 and -0.5? (ii) Calculate the drain-to-source current S when GS is -1.5? (iii) What is the ac voltae ain A of this aplifier when a load R L of 15.0kΩ is connected at GS = -1.5? References 1. Thoas L. Floyd, "Electronic evices", Prentice Hall nternational, nc.,1999.. Robert T. Paynter,"Electronic evices and Circuits", fifth edition, McGraw- Hill, 1997. 3. Adel S. Sedra and Kenneth C. Sith, "Microelectronic Circuits", fourth edition, Oxford University Press, 1998. 4. Theodore F. Boart, Jr., Jeffrey S. Beasley, and Guillero Rico, Electronic evices and Circuits, sixth edition, Prentice Hall nternational nc., 004. - 138 -