Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers Features Very high speed MBit/s Superior CMR kv/µs Double working voltage-4v Fan-out of over -4 C to +5 C Logic gate output Strobable output Wired OR-open collector U.L. recognized (File # E97) Applications Ground loop elimination LSTTL to TTL, LSTTL or 5-volt CMOS Line receiver, data transmission Data multiplexing Switching power supplies Pulse transformer replacement Computer-peripheral interface Schematics N/C + V F _ 3 N/C 4 5 GND 6N37 HCPL6 HCPL6 7 6 V CC V E V O A.µF bypass capacitor must be connected between pins and 5 (). + V F V F 3 + 4 5 GND HCPL63 HCPL63 Description January The 6N37, HCPL6, HCPL6 single-channel and HCPL63, HCPL63 dual-channel optocouplers consist of a 5 nm AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -4 C to +5 C. A maximum input signal of 5mA will provide a minimum output sink current of 3mA (fan out of ). An internal noise shield provides superior common mode rejection of typically kv/µs. The HCPL6 and HCPL63 has a minimum CMR of 5kV/µs. The HCPL6 has a minimum CMR of kv/µs. 7 6 V CC V V Package Outlines Truth Table (Positive Logic) Input Enable Output H H L L H H H L H L L H H NC L L NC H Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers 6N37, HCPL6, HCPL6, HCPL63, HCPL63 Rev...
Absolute Maximum Ratings (T A = 5 C unless otherwise specified) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Value Units T STG Storage Temperature -55 to +5 C T OPR Operating Temperature -4 to +5 C T SOL Lead Solder Temperature (for wave soldering only)* 6 for sec C EMITTER I F DC/Average Forward Single Channel 5 ma Input Current Dual Channel (Each Channel) 3 V E Enable Input Voltage Not to Exceed Single Channel 5.5 V V CC by more than 5mV V R Reverse Input Voltage Each Channel 5. V P I Power Dissipation Single Channel mw Dual Channel (Each Channel) 45 DETECTOR V CC Supply Voltage 7. V ( minute max) I O Output Current Single Channel 5 ma Dual Channel (Each Channel) 5 V O Output Voltage Each Channel 7. V P O Collector Output Single Channel 5 mw Power Dissipation Dual Channel (Each Channel) 6 *For peak soldering reflow, please refer to the Reflow Profile on page. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Units I FL Input Current, Low Level 5 µa I FH Input Current, High Level *6.3 5 ma V CC Supply Voltage, Output 4.5 5.5 V V EL Enable Voltage, Low Level. V V EH Enable Voltage, High Level. V CC V T A Low Level Supply Current -4 +5 C N Fan Out (TTL load) *6.3mA is a guard banded value which allows for at least % CTR degradation. Initial input current threshold value is 5.mA or less. Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers 6N37, HCPL6, HCPL6, HCPL63, HCPL63 Rev...
Electrical Characteristics (T A = to 7 C unless otherwise specified) Individual Component Characteristics Symbol Parameter Test Conditions Min. Typ.* Max. Unit EMITTER V F Input Forward Voltage I F = ma. V T A = 5 C.4.75 B VR Input Reverse Breakdown Voltage I R = µa 5. V C IN Input Capacitance V F =, f = MHz 6 pf V F / T A Input Diode Temperature Coefficient I F = ma -.4 mv/ C DETECTOR I CCH High Level Supply Current V CC = 5.5V, I F = ma, V E =.5V Single Channel 7 ma Dual Channel 5 I CCL Low Level Supply Current Single Channel V CC = 5.5V, 9 3 ma I F = ma Dual Channel V E =.5V 4 I EL Low Level Enable Current V CC = 5.5V, V E =.5V -. -.6 ma I EH High Level Enable Current V CC = 5.5V, V E =.V -.6 -.6 ma V EH High Level Enable Voltage V CC = 5.5V, I F = ma. V V EL Low Level Enable Voltage V CC = 5.5V, I F = ma (3). V Switching Characteristics (T A = -4 C to +5 C, V CC = 5V, I F = 7.5mA unless otherwise specified) Symbol AC Characteristics Test Conditions Min. Typ.* Max. Unit T PLH T PHL Propagation Delay Time to Output HIGH Level Propagation Delay Time to Output LOW Level R L = 35Ω, C L = 5pF (4) (Fig. ) T A = 5 C 45 75 ns T A = 5 C (5) 5 45 75 ns R L = 35Ω, C L = 5pF (Fig. ) T PHL T PLH Pulse Width Distortion (R L = 35Ω, C L = 5pF (Fig. ) 3 35 ns t r Output Rise Time R L = 35Ω, C L = 5pF (6) (Fig. ) 5 ns ( 9%) t f Output Rise Time R L = 35Ω, C L = 5pF (7) (Fig. ) ns (9 %) t ELH Enable Propagation Delay Time to Output HIGH Level I F = 7.5mA, V EH = 3.5V, R L = 35Ω, C L = 5pF () (Fig. 3) ns t EHL CM H CM L Enable Propagation Delay Time to Output LOW Level Common Mode Transient Immunity (at Output HIGH Level) Common Mode Transient Immunity (at Output LOW Level) I F = 7.5mA, V EH = 3.5V, R L = 35Ω, C L = 5pF (9) (Fig. 3) T A = 5 C, V CM = 5V (Peak), I F = ma, V OH (Min.) =.V, R L = 35Ω () (Fig. 4) ns 6N37, HCPL63, V/µs HCPL6, HCPL63 5, V CM = 4V HCPL6, 5, V/µs R L = 35Ω, I F = 7.5mA, 6N37, HCPL63, V OL (Max.) =.V, T A = 5 C () (Fig. 4) HCPL6, HCPL63 5, V CM = 4V HCPL6, 5, Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers 6N37, HCPL6, HCPL6, HCPL63, HCPL63 Rev... 3
Electrical Characteristics (Continued) Transfer Characteristics (T A = -4 to +5 C unless otherwise specified) Symbol DC Characteristics Test Conditions Min. Typ.* Max. Unit I OH HIGH Level Output Current V CC = 5.5V, V O = 5.5V, µa I F = 5µA, V E =.V () V OL LOW Level Output Current V CC = 5.5V, I F = 5mA, V E =.V,.35.6 V I CL = 3mA () I FT Input Threshold Current V CC = 5.5V, V O =.6V, V E =.V, 3 5 ma I OL = 3mA Isolation Characteristics (T A = -4 C to +5 C unless otherwise specified.) Symbol Characteristics Test Conditions Min. Typ.* Max. Unit I I-O Input-Output Insulation Leakage Current Relative humidity = 45%, T A = 5 C, t = 5s, V I-O = 3 VDC ().* µa V ISO Withstand Insulation Test Voltage *All Typicals at V CC = 5V, T A = 5 C RH < 5%, T A = 5 C, 5 V RMS I I-O µa, t = min. () R I-O Resistance (Input to Output) V I-O = 5V () Ω C I-O Capacitance (Input to Output) f = MHz ().6 pf Notes:. The V CC supply to each optoisolator must be bypassed by a.µf capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V CC and GND pins of each device.. Each channel. 3. Enable Input No pull up resistor required as the device has an internal pull up resistor. 4. t PLH Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current pulse to the.5 V level on the LOW to HIGH transition of the output voltage pulse. 5. t PHL Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current pulse to the.5 V level on the HIGH to LOW transition of the output voltage pulse. 6. t r Rise time is measured from the 9% to the % levels on the LOW to HIGH transition of the output pulse. 7. t f Fall time is measured from the % to the 9% levels on the HIGH to LOW transition of the output pulse.. t ELH Enable input propagation delay is measured from the.5v level on the HIGH to LOW transition of the input voltage pulse to the.5v level on the LOW to HIGH transition of the output voltage pulse. 9. t EHL Enable input propagation delay is measured from the.5v level on the LOW to HIGH transition of the input voltage pulse to the.5v level on the HIGH to LOW transition of the output voltage pulse.. CM H The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the HIGH state (i.e., V OUT >.V). Measured in volts per microsecond (V/µs).. CM L The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the LOW output state (i.e., V OUT <.V). Measured in volts per microsecond (V/µs).. Device considered a two-terminal device: Pins,, 3 and 4 shorted together, and Pins 5, 6, 7 and shorted together. Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers 6N37, HCPL6, HCPL6, HCPL63, HCPL63 Rev... 4
Typical Performance Curves VOL LOW LEVEL OUTPUT VOLTAGE (V) TP PROPAGATION DELAY (ns) IFT INPUT THRESHOLD CURRENT (ma)..7.6.5.4.3.. Fig. Low Level Output Voltage vs. Ambient Temperature I OL = 6mA. -4-4 6 6 4 5 4 3 Conditions: I F = 5 ma V E = V V CC = 5.5V V CC = 5 V Conditions: V CC = 5. V V O =.6 V I OL =. ma I OL = 6.4mA T A AMBIENT TEMPERATURE ( C) I F FORWARD CURRENT (ma) Fig. 5 Input Threshold Current vs. Ambient Temperature R L = 35Ω R L = kω R L = 4kΩ I OL = 9.6mA Fig.3 Switching Time vs. Forward Current R L = 35 Ω (T PLH ) R L = 4 kω (T PLH ) R L = kω (T PLH ) R L = kω R L = 4 kω (T PHL ) R L = 35 kω 7 9 3 5-4 - 4 6 T A AMBIENT TEMPERATURE ( C) IF FORWARD CURRENT (ma) IOL LOW LEVEL OUTPUT CURRENT (ma) VO OUTPUT VOLTAGE (V) 3 6 5 45 4 35 3 5 Fig. 4 Low Level Output Current vs. Ambient Temperature I F = 5mA I F = ma I F = 5mA -4-4 6 6 5 4 3... T A AMBIENT TEMPERATURE ( C) Fig. 6 Output Voltage vs. Input Forward Current R L = 4kΩ Fig. Input Diode Forward Voltage vs. Forward Current.9....3.4.5.6 V F FORWARD VOLTAGE (V) R L = 35Ω R L = kω I F - FORWARD CURRENT (ma) Conditions: V CC = 5 V V E = V V OL =.6 V 3 4 5 6 Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers 6N37, HCPL6, HCPL6, HCPL63, HCPL63 Rev... 5
PWD PULSE WIDTH DISTORTION (ns) IOH HIGH LEVEL OUTPUT CURRENT (µa) Typical Performance Curves (Continued) TE ENABLE PROPAGATION DELAY (ns) 6 4 6 4 Fig. 7 Pulse Width Distortion vs. Temperature Conditions: I F = 7.5mA VCC = 5A RL = kω RL = 35Ω RL = 4 kω -6-4 - 4 6 T A TEMPERATURE ( C) Fig. 9 Enable Propagation Delay vs. Temperature RL = 4 kω (TELH) RL = kω (TELH) RL = 35Ω (TELH) RL = 35Ω RL = kω (TEHL) RL = 4 kω -6-4 - 4 6 T A TEMPERATURE ( C) 5 5 TP PROPAGATION DELAY (ns) Tr/Tf RISE AND FALL TIME (ns) 6 5 4 3 Conditions: IF = 7.5 ma VCC = 5 V Fig. High Level Output Current vs. Temperature -6-4 - 4 6 T A TEMPERATURE ( C) 6 4 Fig. Rise and Fall Time vs. Temperature RL = kω (tr) RL = 35Ω (tr) R L = 4 kω (tr) RL = kω RL = 4 kω RL = 35Ω -6-4 - 4 6 T A TEMPERATURE ( C) Fig. Switching Time vs. Temperature RL = 4 kω TPLH RL = kω TPLH RL = 35Ω TPLH RL = kω RL = 4 kω TPHL RL = 35Ω -6-4 - 4 6 Conditions: V CC = 5.5 V V O = 5.5 V V E =. V I F = 5 µa T A TEMPERATURE ( C) (tf) Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers 6N37, HCPL6, HCPL6, HCPL63, HCPL63 Rev... 6
Test Circuits Input Monitor (I F) Pulse Generator tr = 5ns Z O= 5Ω 47 Pulse Generator tr = 5ns Z O= 5Ω 7.5 ma 3 4 GND 5 3 4 V CC V CC GND 7 6 7 6 5. µf bypass R L C L +5V Output (V ) O +5V Input (I F) t PHL Output (V O) Output (V ) O Fig. Test Circuit and Waveforms for t PLH, t PHL, t r and t f Input Monitor (V E). µf bypass R L C L Output (V O) Input (V ) E tehl Output (V O) Fig. 3 Test Circuit t EHL and t ELH tf 9% % t PLH t ELH tr I F = 7.5 ma I = 3.75 ma F.5 V 3. V.5 V.5 V Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers 6N37, HCPL6, HCPL6, HCPL63, HCPL63 Rev... 7
Test Circuits (Continued) VCM V 5V VO VO.5 V V FF B A I F 3 4 Peak V CC GND V CM Pulse Gen Switching Pos. (A), I = F V (Min) O 7 6 5 V O (Max). µf bypass Switching Pos. (B), I = 7.5 ma F 35Ω Fig. 4 Test Circuit Common Mode Transient Immunity +5V Output (V O) CM H CM L Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers 6N37, HCPL6, HCPL6, HCPL63, HCPL63 Rev...
Ordering Information Option Example Part Number Description S 6N37S Surface Mount Lead Bend SD 6N37SD Surface Mount; Tape and Reel W 6N37W.4" Lead Spacing V 6N37V VDE4 WV 6N37WV VDE4;.4 Lead Spacing SV 6N37SV VDE4; Surface Mount SDV 6N37SDV VDE4; Surface Mount; Tape and Reel Marking Information Definitions Fairchild logo Device number V 3 4 5 3 VDE mark (Note: Only appears on parts ordered with VDE option See order entry table) 4 Two digit year code, e.g., 3 5 Two digit work week ranging from to 53 6 Assembly package code XX YY 6 T 6 Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers 6N37, HCPL6, HCPL6, HCPL63, HCPL63 Rev... 9
Tape Specifications Reflow Profile 4.9 ±. 3. ±..3 ±.5 User Direction of Feed 4. ±.. MAX.3 ±. Temperature ( C) 3 5 5 5. ±. 4. ±. 5 C peak Ramp up = 3C/sec Time (Minute) 5 C, 3 s Time above 3C, 6 5 sec.5.5.5 3 3.5 4 4.5 Ø.55 ±.5.3 ±. Peak reflow temperature: 5C (package surface temperature) Time of temperature higher than 3C for 6 5 seconds One time soldering reflow is recommended.75 ±. 7.5 ±. Ø.6 ±. 6. ±.3 Single-Channel: 6N37, HCPL6, HCPL6 Dual-Channel: HCPL63, HCPL63 High Speed MBit/s Logic Gate Optocouplers 6N37, HCPL6, HCPL6, HCPL63, HCPL63 Rev...
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