G401, G403, G40 Low-Power, High-Speed MOS Analog Switches ESRIPTION The G401, G403, G40 monolithic analog switches were designed to provide precision, high performance switching of analog signals. ombining low power (0.3 µw, typ.) with high speed (t ON : 7 ns, typ.), the G401 series is ideally suited for portable and battery powered industrial and military applications. Built on the proprietary high-voltage silicon-gate process to achieve high voltage rating and superior switch on/off performance, break-before-make is guaranteed for the SPT configurations. An epitaxial layer prevents latchup. Each switch conducts equally well in both directions when on, and blocks up to 30 V peak-to-peak when off. Onresistance is very flat over the full ± 1 V analog range, rivaling JFET performance without the inherent dynamic range limitations. The three devices in this series are differentiated by the type of switch action as shown in the functional block diagrams. FEATURES 44 V supply max. rating ± 1 V analog signal range On-resistance - R S (on): 30 Ω Low leakage - I (on) : 40 pa Fast switching - t ON : 7 ns Ultra low power requirements - P : 0.3 µw TTL, MOS compatible Single supply capability ompliant to RoHS directive 2002/9/E BENEFITS Wide dynamic range Break-before-make switching action Simple interfacing APPLIATIONS Audio and video switching Sample-and-hold circuits Battery operation Test equipment ommunications systems PBX, PABX FUTIONAL BLOK IAGRAM AN PIN ONFIGURATION G401 ual-in-line and SOI 1 1 16 S 1 2 1 IN 1 3 14 4 13 12 6 11 7 IN 2 2 8 9 S 2 Key 4 6 7 8 G401 L 1 S 1 IN 1 3 2 1 20 19 9 11 12 13 18 17 16 1 14 Two SPST Switches per Package TRUTH TABLE Logic Switch 0 OFF 1 ON Logic "0" 0.8 V Logic "1" 2.4 V Top View 2 S 2 Top View IN 2 * Pb containing terminations are not RoHS compliant, exemptions may apply S09-261-Rev. I, 30-Nov-09 1
G401, G403, G40 FUTIONAL BLOK IAGRAM AN PIN ONFIGURATION G403 ual-in-line and SOI 1 1 16 S 1 2 1 IN 1 3 3 14 S 3 4 13 S 4 12 4 6 11 7 IN 2 2 8 9 S 2 Key 3 S 3 S 4 4 4 6 7 8 G403 L 1 S 1 IN 1 3 2 1 20 19 9 11 12 13 2 S 2 IN 2 18 17 16 1 14 Two SPT Switches per Package TRUTH TABLE Logic SW 1, SW 2 SW 3, SW 4 0 OFF ON 1 ON OFF Logic "0" 0.8 V Logic "1" 2.4 V Top View Top View G40 G40 ual-in-line and SOI 1 1 16 S 1 2 1 IN 1 3 3 14 S 3 4 13 S 4 12 4 6 11 7 IN 2 2 8 9 S 2 Key 3 S 3 S 4 4 4 6 7 8 L 1 S 1 IN 1 3 2 1 20 19 9 11 12 13 18 17 16 1 14 Two PST Switches per Package TRUTH TABLE Logic "0" 0.8 V Logic "1" 2.4 V Logic Switch 0 OFF 1 ON 2 S 2 IN 2 Top View Top View 2 S09-261-Rev. I, 30-Nov-09
G401, G403, G40 ORERING INFORMATION Temp. Range Package Part Number G401 G403 G40-40 to 8-40 to 8-40 to 8 16-Pin Plastic IP 16-Pin Narrow SOI 16-Pin Plastic IP 16-Pin Narrow SOI 16-Pin Plastic IP 16-Pin Narrow SOI G401J G401J-E3 G401Y G401Y-T1 G401Y-E3 G401Y-T1-E3 G403J G403J-E3 G403Y G403Y-E3 G403Y-T1 G403Y-T1-E3 G40J G40J-E3 G40Y G40Y-E3 G40Y-T1 G40Y-T1-E3 ABSOLUTE MAXIMUM RATINGS Parameter Limit Unit to 44 to 2 ( - 0.3) to () + 0.3 V igital Inputs a () - 2 to () + 2, V S, V or 30 ma, whichever occurs first urrent (Any Terminal) ontinuous 30 urrent, S or (Pulsed 1 ms, % uty) 0 ma Storage Temperature (J, Y Suffix) - 6 to 12 Power issipation (Package) b 16-Pin Plastic IP c 40 16-Pin SOI d 600 mw Notes: a. Signals on S X, X, or IN X exceeding or will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to P board. c. erate 6 mw/ above 7. d. erate 7.6 mw/ above 7. S09-261-Rev. I, 30-Nov-09 3
G401, G403, G40 SPEIFIATIONS a Test onditions Unless Specified = 1 V, = Suffix - 40 to 8 Parameter Symbol = V, V IN = 2.4 V, 0.8 V f Temp. b Typ. c Min. d Max. d Unit Analog Switch Analog Signal Range e V ANALOG Full - 1 1 V rain-source On-Resistance Δ rain-source On-Resistance Switch Off Leakage urrent R S(on) ΔR S(on) I S(off) I (off) I S = - ma, V = ± V = 13. V, = - 13. V I S = - ma, V = ± V, 0 V = 16. V, = - 16. V = 16. V, = - 16. V V = ± 1. V, V S = ± 1. V = 16. V, = - 16. V hannel On Leakage urrent I (on) V S = V = ± 1. V igital ontrol V Input urrent V IN Low I IN under test = 0.8 V IL All Other = 2.4 V V Input urrent V IN High I IN under test = 2.4 V IH All Other = 0.8 V ynamic haracteristics Turn-On Time t ON R L = 300 Ω, L = 3 pf See Figure 2 Break-Before-Make Time elay (G403) harge Injection Q L = nf V gen = 0 V, R gen = 0 Ω Off Isolation Reject Ratio OIRR R L = 0 Ω, L = pf f = 1 MHz Source Off apacitance S(off) f = 1 MHz, V S = 0 V Notes: a. Refer to PROESS OPTION FLOWHART. b. = 2, Full = as determined by the operating temperature suffix. c. Typical values are for ESIGN AI ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet. e. Guaranteed by design, not subject to production test. f. V IN = input voltage to perform proper function. Full Full Hot Hot Hot 30 4 3 3-0.01-0. - - 0.01-0. - - 0.04-1 - 0. 0. 1 Full 0.00-1 1 Full 0.00-1 1 7 Turn-Off Time t OFF 30 0 t R L = 300 Ω, L = 3 pf 3 Ω na µa ns 60 p 72 hannel-to-hannel rosstalk X TALK 90 12 rain Off apacitance (off) 12 hannel On apacitance, S(on) 39 Power Supplies Positive Supply urrent I+ Full Negative Supply urrent Logic Supply urrent I- I L = 16. V, = - 16. V Full V IN = 0 or V Full Ground urrent I Full 0.01 1-0.01-1 - 0.01 1-0.01-1 - db pf µa Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4 S09-261-Rev. I, 30-Nov-09
G401, G403, G40 TYPIAL HARATERISTIS 2, unless otherwise noted 7 3. 6 = 1 V = -1 V 3 SW1, 2 2. (V) 4 SW3, 4 (V) 2 = 7 V V T 3 V TH 1. 2 1 = V 1 0. 0 0 2 4 6 8 12 14 16 18 - Logic Supply (V) Input Switching Threshold vs. Logic Supply Voltage 0 1 20 2 30 3 () Input Switching Threshold vs. Supply Voltages R S(on) - rain-source On-Resistance (Ω) 0 4 40 3 30 2 20 1 8 2 0 = 1 V, = VL = V - 40 R S(on) - rain-source On-Resistance (Ω) 60 0 40 30 20 T A = 2 ±6 V ± V ± 12 V ± 1 V ± 20 V ± 22 V 0-1 - - 0 1 V - rain Voltage (V) R S(on) vs. V and Temperature - 2-1 - 1 26 V - rain Voltage (V) R S(on) vs. V and Power Supply Voltage R S(on) - rain-source On-Resistance (Ω) 0 90 80 70 60 0 40 30 20 T A = 2 7. V V 12 V 1 V 20 V 22 V Q (p) 0 40 30 20 0 - - 20 L = nf 0 pf 1 nf 0 1 20 2 V - rain Voltage (V) R S(on) vs. V and Power Supply Voltage ( = 0 V) - 30-1 - - 0 1 V S - Source Voltage (V) harge Injection vs. Analog Voltage S09-261-Rev. I, 30-Nov-09
G401, G403, G40 TYPIAL HARATERISTIS 2, unless otherwise noted 00p 0p = 1 V = -1 V = V V = ± 14 V I S (off) 40 20 0 I (on) I (off) I S (off) I (off) I (on) (pa) I S, I - 20-40 p I (off) - 60-80 1p - 40-20 0 20 40 60 80 Temperature ( ) Leakage urrent vs. Temperature - 0-1 - - 0 1 V or V S - rain or Source Voltage (V) Leakage urrent vs. Analog Voltage 0 na 1 na = 1 V = = V I+ I- 120 0 V + = 1 V = = V t ON I+, I-, I L (A) 0 pa pa I L t ON, t OFF (ns) 80 60 40 V S = V V S = V V S = - V t OFF 20 V S = - V t ON, t OFF (ns) 1 pa 180 160 140 120 0 80 60 40 20 0-40 - 20 0 20 40 60 80 0 T A - Temperature ( ) Supply urrent vs. Temperature V S = - V V S = V V S = V V S = - V 0 ± ± ± 1 ± 20 ± 2, Positive and Negative Supplies (V) Switching Time vs. Power Supply Voltage* * Refer to Figure 2 for test conditions. t ON t OFF t ON, t OFF (ns) 0-40 - 20 0 20 40 60 80 0 T A - Temperature ( ) Switching Time vs. Temperature* 300 270 0 V V S = V 240 2 180 - V 120 90 60 t ON - V t OFF 30 0 V 0 0 1 20 2 - Positive Supply (V) Switching Time vs. Positive Supply Voltage* 6 S09-261-Rev. I, 30-Nov-09
G401, G403, G40 TYPIAL HARATERISTIS 2, unless otherwise noted 0 ma ma 1 ma Supply urrent (A) 0 µa µa 1 µa 0 na na 0 1K K 0K 1M M Frequency (Hz) Supply urrent vs. Switching Frequency SHEMATI IAGRAM Typical hannel S V IN Level Shift/ rive V V Figure 1. S09-261-Rev. I, 30-Nov-09 7
G401, G403, G40 TEST IRUITS is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. + V + 1 V Logic Input 0 V 0 % t f < 20 ns t f < 20 ns ± V S Switch Input* V S 90 % t OFF IN R L 1 kω L 3 pf Switch Output Switch Input* 0 V -V S t ON 90 % L (includes fixture and stray capacitance) R O = V S R L + r S(on) * V S = V for t ON, V S = - V for t OFF Note: Logic input waveform is inverted for switches that have the opposite logic sense control Figure 2. Switching Time V S1 V S2 + V + 1 V S 1 1 S 2 2 IN 2 R L1 L1 1 Logic Input Switch Output 3 V 0 V V S1 1 0 V V S2 2 0 % 90 % 90 % R L2 L2 Switch Output 0 V t t L (includes fixture and stray capacitance) Figure 3. Break-Before-Make + V + 1 V R g S Δ V g 3 V IN L nf IN On Off On Q = Δ x L Figure 4. harge Injection 8 S09-261-Rev. I, 30-Nov-09
G401, G403, G40 TEST IRUITS + V + 1 V + V + 1 V V S S 1 V S S R g = 0 Ω 0 Ω R g = 0 Ω 0 V, 2.4 V IN R L 0 Ω R L 0.8 V S 2 IN Off Isolation = 20 log = RF bypass V S X TALK Isolation = 20 log = RF bypass V S Figure. Off Isolation Figure 7. rosstalk + V + 1 V + V + 1 V V S R g = 0 Ω 0 V, 2.4 V S IN R L 0 Ω 0 V, 2.4 V IN S Meter HP4192A Impedance Analyzer or Equivalent f = 1 MHz = RF bypass Figure 6. Insertion Loss Figure 8. apacitances S09-261-Rev. I, 30-Nov-09 9
G401, G403, G40 APPLIATIONS + V + 1 V + V + 1 V Source 1 Left Right S 1 S 3 1 3 Left e in S 1 S 3 1 3 + - e out Left IN 1 IN 1 1 Source 2 Right S 2 S 4 2 4 Right TTL Integrate/ Reset S 2 S 4 2 4 TTL hannel Select IN 2 G403 Slope Select IN 2 G403 2 Figure 9. Stereo Source Selector Figure. ual Slope Integrator ual Slope Integrators: The G403 is well suited to configure a selectable slope integrator. One control signal selects the timing capacitor 1 or 2. Another one selects e in or discharges the capacitor in preparation for the next integration cycle. + V S 1 + 1 V 1 Band-Pass Switched apacitor Filter: Single-pole double-throw switches are a common element for switched capacitor networks and filters. The fast switching times and low leakage of the G403 allow for higher clock rates and consequently higher filter operating frequencies. e in lock S 3 3 IN 1 S 2 2 S 4 4 IN 2 G403 + - e out Figure 11. Band-Pass Switched apacitor Filter S09-261-Rev. I, 30-Nov-09
G401, G403, G40 APPLIATIONS Peak etector: A 3 acting as a comparator provides the logic drive for operating SW 1. The output of A 2 is fed back to A 3 and compared to the analog input e in. If e in > e out the output of A 3 is high keeping SW 1 closed. This allows 1 to charge up to the analog input voltage. When e in goes below e out A 3 goes negative, turning SW 1 off. The system will therefore store the most positive analog input experienced. Reset SW 2 e in A1 + SW 1 R 1 + A 2 e out + A 3 G401 1 Figure 12. Positive Peak etector maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?70049. S09-261-Rev. I, 30-Nov-09 11
Package Information JEE Part Number: MS-012 16 1 14 13 12 11 9 1 2 3 4 6 7 8 E im Min Max Min Max A 1.3 1.7 0.03 0.069 A 1 0. 0.20 0.004 0.008 B 0.38 0.1 0.01 0.020 0.18 0.23 0.007 0.009 9.80.00 0.38 0.393 E 3.80 4.00 0.149 0.17 e 1.27 BS 0.00 BS H.80 6.20 0.228 0.244 L 0.0 0.93 0.020 0.037 0 8 0 8 EN: S-03946 Rev. F, 09-Jul-01 WG: 300 H All Leads e B A1 L 0.1 mm 0.004 IN ocument Number: 71194 02-Jul-01 1
Package Information 16 1 14 13 12 11 9 E 1 E 1 2 3 4 6 7 8 S Q 1 A A 1 L B 1 e 1 B e A 1 MAX im Min Max Min Max A 3.81.08 0. 0.200 A 1 0.38 1.27 0.01 0.00 B 0.38 0.1 0.01 0.020 B 1 0.89 1.6 0.03 0.06 0.20 0.30 0.008 0.012 18.93 21.33 0.74 0.840 E 7.62 8.26 0.300 0.32 E 1.9 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.1 e A 7.37 7.87 0.290 0.3 L 2.79 3.81 0.1 0. Q 1 1.27 2.03 0.00 0.080 S 0.38 1.2.01 0.060 EN: S-03946 Rev., 09-Jul-01 WG: 482 ocument Number: 71261 06-Jul-01 1
Application Note 826 REOMMENE MINIMUM PAS FOR SO-16 REOMMENE MINIMUM PAS FOR SO-16 0.372 (9.449) 0.047 (1.194) APPLIATION NOTE 0.246 (6.248) 0.12 (3.861) 0.022 (0.9) 0.00 (1.270) 0.028 (0.711) Recommended Minimum Pads imensions in Inches/(mm) Return to Index Return to Index ocument Number: 72608 24 Revision: 21-Jan-08
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Mouser Electronics Authorized istributor lick to View Pricing, Inventory, elivery & Lifecycle Information: Vishay: G403AK G40Y-E3 G40J-E3 G403Y-E3 G403J G403Y G40Y G40J G40AK G401J G403Y-T1 G403J-E3 G401J-E3 G403Y-T1-E3 G40Y-T1-E3 G40Y-T1 G401Y- T1-E3 G401Y-E3 G401Y