Exercise 1: EXCLUSIVE OR/NOR Gate Functions

Similar documents
Exercise 2: OR/NOR Logic Functions

Exercise 1: AND/NAND Logic Functions

Exercise 1: DC Operation of a NOT and an OR-TIE

Exercise 1: Circuit Block Familiarization

Exercise 2: Source and Sink Current

Exercise 1: Tri-State Buffer Output Control

Exercise 2: Current in a Series Resistive Circuit

Exercise 3: Ohm s Law Circuit Voltage

Lab# 13: Introduction to the Digital Logic

Exercise 2: Ohm s Law Circuit Current

EXPERIMENT 12: DIGITAL LOGIC CIRCUITS

Exercise 1: Inductors

Exercise 2: Temperature Measurement

TECH 3232 Fall 2010 Lab #1 Into To Digital Circuits. To review basic logic gates and digital logic circuit construction and testing.

Exercise 3: Voltage in a Series Resistive Circuit

Exercise 2: Temperature Measurement

Schmitt Trigger Inputs, Decoders

The collector terminal is common to the input and output signals and is connected to the dc power supply. Common Collector Circuit

Exercise 2: Inductors in Series and in Parallel

LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.

Lab Project #2: Small-Scale Integration Logic Circuits

Digital Fundamentals. Lab 4 EX-OR Circuits & Combinational Circuit Design

4-bit counter circa bit counter circa 1990

4-bit counter circa bit counter circa 1990

DIGITAL ELECTRONICS. Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3

Exercise 1: AC Waveform Generator Familiarization

A B. 1 (a) (i) Fig shows the symbol for a circuit component. Fig Name this component. ... [1]

Exercise 3: Power in a Series/Parallel Circuit

Schmitt trigger. V I is converted from a sine wave into a square wave. V O switches between +V SAT SAT and is in phase with V I.

1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e.

2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs.

EK307 Lab 3 Spring Lab Assignment 3 Logic Gates

When you have completed this exercise, you will be able to determine ac operating characteristics of a

This transistor circuit has a voltage divider circuit with an emitter resistor for bias stability.

When you have completed this exercise, you will be able to determine the ac operating characteristics of

Gates and Circuits 1

Exercise 1: Series RLC Circuits

Exercise 1: The Rheostat

An input resistor suppresses noise and stray pickup developed across the high input impedance of the op amp.

Exercise 1: The DC Ammeter

In this experiment you will study the characteristics of a CMOS NAND gate.

Chapter 6 Digital Circuit 6-6 Department of Mechanical Engineering

Gates and and Circuits

PS 12b Lab 1c IV Curves

Lecture 15 Analysis of Combinational Circuits

Experiment # 3 Combinational Circuits (I) Binary Addition and Subtraction

CSE208W Lecture #1 Notes Barry E. Mapen

using dc inputs. You will verify circuit operation with a multimeter.

ELECTROVATE. Electromania Problem Statement Discussion

Figure 1: Basic Relationships for a Comparator. For example: Figure 2: Example of Basic Relationships for a Comparator

Digital Electronics Course Objectives

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

Project Board Game Counter: Digital

Introduction to Electronics. Dr. Lynn Fuller

Logic diagram: a graphical representation of a circuit

Experiment # 2 The Voting Machine

3.1 There are three basic logic functions from which all circuits can be designed: NOT (invert), OR, and

ENG 100 Electric Circuits and Systems Lab 6: Introduction to Logic Circuits

UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC 180A DIGITAL SYSTEMS I Winter 2015

Lab 2: Combinational Circuits Design

Exercise 1: Touch and Position Sensing

BMC040. Dual Logic. Last updated

Department of Electrical and Electronics Engineering Logic Circuits Laboratory EXPERIMENT-1 BASIC GATE CIRCUITS

Chapter 1: Digital logic

UNIVERSITI MALAYSIA PERLIS

Function Table of an Odd-Parity Generator Circuit

Exercise 2: FM Detection With a PLL

Total No. of Questions : 40 ] [ Total No. of Printed Pages : 7. March, Time : 3 Hours 15 Minutes ] [ Max. Marks : 90

Logic Symbols with Truth Tables INVERTER A B NAND A B C NOR C A B A B C XNOR A B C A B Digital Logic 1

B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics

Basic Logic Circuits

QUIZ. What do these bits represent?

Revised: Summer 2010

Multiple input gates. The AND gate

Chapter 4 Logic Functions and Gates

EGCP 1010 Digital Logic Design (DLD) Laboratory #1

Digital Fundamentals

Lab #10: Finite State Machine Design

Simple Circuits Experiment

Combinational logic. ! Regular logic: multiplexers, decoders, LUTs and FPGAs. ! Switches, basic logic and truth tables, logic functions

Name EGR 2131 Lab #2 Logic Gates and Boolean Algebra Objectives Equipment and Components Part 1: Reading Pin Diagrams 7400 (TOP VIEW)

o What happens if S1 and S2 or S3 and S4 are closed simultaneously? o Perform Motor Control, H-Bridges LAB 2 H-Bridges with SPST Switches

;UsetJand : Llto Record the truth. LAB EXERCISE 6.1 Binary Adders. Materials. Procedure

Exercise 2: Collector Current Versus Base Current

Odd-Prime Number Detector The table of minterms is represented. Table 13.1

Exercise 2: Q and Bandwidth of a Series RLC Circuit

ELEC 2210 EXPERIMENT 12 NMOS Logic

Introduction to Pspice

Chapter 4 Combinational Logic Circuits

Some frequently used transistor parameter symbols and their meanings are given here.

UNIT E1 (Paper version of on-screen assessment) A.M. WEDNESDAY, 8 June hour

Lab 2 Revisited Exercise

*X025/11/01* X025/11/01 ELECTRONIC AND ELECTRICAL FUNDAMENTALS INTERMEDIATE 2 NATIONAL QUALIFICATIONS 2015 WEDNESDAY, 3 JUNE 9.00 AM 11.

1. LINEAR WAVE SHAPING

EXPERIMENT 5 Basic Digital Logic Circuits

ELECTRICAL ENGINEERING - TEACHER MODULE 1 LOGIC GATES

University of Technology

TTL LOGIC and RING OSCILLATOR TTL

Chapter 4 Combinational Logic Circuits

Lab 10. Magnetic-Levitation Controller

Transcription:

EXCLUSIVE-OR/NOR Gates Digital Logic Fundamentals Exercise 1: EXCLUSIVE OR/NOR Gate Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate the operation of an EXCLUSIVE- OR and an EXCLUSIVE-NOR logic gate. You will verify your results by generating truth tables for each function. EXERCISE DISCUSSION Pins 14 and 7 supply power to the IC. The IC has four two-input XOR gates labeled A through D. 84 FACET by Lab-Volt

Digital Logic Fundamentals EXCLUSIVE-OR/NOR Gates With a 74LS136 IC, inputs may be tied to other inputs, an output may be connected to inputs, and outputs can be connected to other outputs. The outputs require pull-up resistors. Pin 6 is the output of which XOR gate in the IC? a. gate A b. gate B c. gate C d. gate D The internal open collector output circuit of an XOR gate is shown in the large circle. The output of an open collector device requires an external collector load or pull-up resistor. FACET by Lab-Volt 85

EXCLUSIVE-OR/NOR Gates Digital Logic Fundamentals Output terminals of the 74LS136 require pull-up resistors because the 74LS136 has an open collector circuit at the output. The gate output is pulled up to V CC by a 10 k resistor. The open collector circuit must have a source of power for the output. The pull-up resistor provides this required power source. PROCEDURE Locate the XOR/XNOR circuit block, and connect the circuit shown. Insert a two-post connector in BLOCK SELECT, and place toggle switches A and B of the INPUT SIGNALS circuit block in the LOW position. NOTE: A high logic level turns on an LED. You can verify the state of a signal, as indicated by a circuit LED, by connecting your multimeter to the appropriate test point. 86 FACET by Lab-Volt

Digital Logic Fundamentals EXCLUSIVE-OR/NOR Gates What are the logic levels at XOR gate inputs A and B? a. both low b. both high Based on the input levels of the XOR gate, what is the output state? a. logic 1 b. logic 0 What are the logic levels at XNOR gate inputs A and B? a. both high b. both low Based on the input levels of the XNOR gate, what is the output state? a. logic 1 b. logic 0 FACET by Lab-Volt 87

EXCLUSIVE-OR/NOR Gates Digital Logic Fundamentals Set INPUT SIGNALS toggle switches A and B to HIGH. What is the XOR output logic state? What is the XNOR output logic state? Set INPUT SIGNALS switch A to HIGH and switch B to LOW. What is the XOR output logic state? What is the XNOR output logic state? 88 FACET by Lab-Volt

Digital Logic Fundamentals EXCLUSIVE-OR/NOR Gates Set INPUT SIGNALS switch A to LOW and switch B to HIGH. What is the XOR output logic state? What is the XNOR output logic state? Set INPUT SIGNALS switches A and B to LOW. What is the XOR output logic state? What is the XNOR output logic state? FACET by Lab-Volt 89

EXCLUSIVE-OR/NOR Gates Digital Logic Fundamentals Based on the truth table, which gate detects input inequality by the output being 1? a. XOR b. XNOR Based on the truth table, which gate detects input equality by the output being logic 1? a. XOR b. XNOR What is the relationship of the XOR output logic state with respect to the XNOR output logic state for the same input conditions? a. They are the same. b. There is no relationship. c. They are complementary. Can either input of the XOR gate be used to lock out the effect on the output by the other input? a. yes b. no 90 FACET by Lab-Volt

Digital Logic Fundamentals EXCLUSIVE-OR/NOR Gates CONCLUSION The output of an XOR circuit is high for input conditions of inequality. The output of an XNOR circuit is high for input conditions of equality. The inputs of an exclusive type IC cannot be locked out because all input logic states affect the output state. The outputs of an XOR and XNOR gate are complementary when the input conditions are the same. REVIEW QUESTIONS 1. Which schematic symbol represents an EXCLUSIVE-OR gate? a. (a) b. (b) c. (c) d. (d) 2. Which schematic symbol represents an EXCLUSIVE-NOR gate? a. (a) b. (b) c. (c) d. (d) 3. When the two inputs to an XNOR gate are equal, the output logic state a. is high. b. is low. c. depends on the previous output state. d. cannot be determined. 4. When the two inputs to an XOR gate are not equal, the output logic state a. is high. b. is low. c. depends on the previous output state. d. cannot be determined. 5. In the circuit shown, a. output D is locked out by the action of the pull-up resistor. b. outputs C and D are complementary. c. outputs C and D are in phase. d. outputs C and D are EXCLUSIVE-OR functions of inputs A and B. FACET by Lab-Volt 91