Introduction to Electronic Devices (Course Number 300331) Fall 2006 Dr. Dietmar Knipp Assistant Professor of Electrical Engineering Information: http://www.faculty.iubremen.de/dknipp/ Source: Apple Ref.: Apple Ref.: IBM Critical 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 1 10 1 dimension (m) Ref.: Palo Alto Research Center 1
7 7.1 Introduction 7.2 Ideal Inverter Characteristic 7.3 Real Inverter Characteristic 7.4 Noise Margin of inverters 7.5 Classification of inverters 7.5.1 Inverter with ohmic load 7.5.2 PELS / NELS Inverter 7.5.3 PELL / NELL Inverter 7.5.4 The CMOS Inverter 7.5.4.1 CMOS Technology 7.5.4.2 Static behavior 7.5.4.3 Static power Dissipation 7.5.4.4 Dynamic behavior of an CMOS inverter 7.5.4.5 Summary of CMOS inverter 7.6 From CMOS inverters to logical gates 7.6.1 Complementary Logic 7.6.2 Transmission Gate Logic References 2
7.1 Introduction In the following we will discuss the electrical characteristic of different MOS inverter circuits. We will discuss the implementation of different types of inverters and its electrical properties. Based on the inverter circuit all other logical gates like OR, AND, NOR, and NAND can be derived. Layout of a CMOS inverter. CMOS inverter and simplified circuit description of a CMOS inverter. Ref.: Hodges & Jackson, Analysis and Design of 3
7.2 Ideal Inverter Characteristic Different types of inverters can be distinguished depending on the circuit implementation. In the ideal case the static characteristic of an inverter (Voltage transfer curve, VTC) is described by a sharp transition from one state to second state. Voltage transfer characteristic of an ideal inverter. Ref.: Hodges & Jackson, Analysis and Design of Input range Output range 4
7.3 Real Inverter Characteristic However, ideal inverters can not be realized. Voltage transfer characteristic of a real inverter. Ref.: Hodges & Jackson, Analysis and Design of Input range Output range 5
7.4 Noise Margin of inverters Ref.: Hodges & Jackson, Analysis and Design of 6
7.4 Noise Margin of inverters Voltage transfer characteristic of the second inverter of a chain of inverters. Voltage transfer characteristic of the third inverter of a chain of inverters. Ref.: Hodges & Jackson, Analysis and Design of 7
7.4 Noise Margin of inverters The input and output signal of an inverter have to be within the noise margin of an inverter. Otherwise the input or output signal of an inverter is undefined. Ref.: Hodges & Jackson, Analysis and Design of 8
7.5 Classification of inverters Inverters can be realized by using different circuit implementations. In the following the different circuit implementations and their advantages and disadvantages will be discussed. The output curve of an inverter (Voltage transfer curve, VTC) is determined by the superposition of the load (pmons, nmos, resistor) and the driver (pmos, nmos) component. Inverter type Driver Load Operation (Load) ER E-MOSFET (n- or p-channel) Resistor - NELS & NELL E-MOSFET (nchannel) E-MOSFET (nchannel) Saturation, Linear PELS & PELL E-MOSFET (pchannel) E-MOSFET (pchannel) Saturation, Linear (p) CMOS E-MOSFET (nchannel) E-MOSFET (pchannel) - (n) CMOS E-MOSFET (pchannel) E-MOSFET (nchannel) - 9
7.5.1 Inverter with ohmic load An inverter can be realized by combining a resistor (load) with an enhancement type transistor (driver). An inverter with an ohmic load is not of relevance for practical applications, but the discussion of the operating principle allows a better understanding of the operating principle of inverters. Inverter with ohmic load and output characteristic. Ref.: Hodges & Jackson, Analysis and Design of 10
7.5.1 Inverter with ohmic load The performance of an inverter is described by the voltage transfer curve and the gain of an inverter. The gain, v, is defined as the ratio of the differential input voltage divided by the differential output voltage of the inverter. The gain of an inverter should be maximized. In the case of an inverter with an ohmic load the driver transistor can be described by a current source, so that the gain can be easily derived. V DD V in g m V in V out V th V in V out v v in gain = = vout g m R Inverter with ohmic load. Ref.: Böhm, Lecture on Microelectroics, University Siegen Equivalent circuit of inverter with ohmic load. 11
7.5.1 Inverter with ohmic load g m = I V D GS Transconductance in linear region I D g m = µ n VG g m I D = µ n VG C C G G W L Transconductance in saturation region W L V D ( V V ) G T v v = v gain in = out g m R Voltage transfer characteristic of an inverter with resistor load. Ref.: Hodges & Jackson, Analysis and Design of 12
7.5.1 Inverter with ohmic load The gain of an inverter with ohmic load can be increased by increasing the load resistance and the W/L ratio of the transistor (driver). The W/L ratio can be increased by choosing a short but wide channel. However, the gain is not the only parameter, which has to be optimized when developing an inverter. In addition to the gain (static behavior) the dynamic behavior has to be taken into account. If we assume that the inverter drives another logic gate like an inverter, and the inverter exhibits an input capacitance it is obvious to see that an increase of the load resistance will increase the time constant (switching speed) of the inverter. A similar behavior is observed if the width of the transistor is increased. The increased width leads to a improved gain, but the input capacitance of the inverter is increased as well, so that the switching speed of the inverter is reduced. An inverter with an ohmic load has an additional disadvantage. It is difficult to realized resistors by using classical semiconductor processes. Therefore, the resistor is usually replaced by a transistor which operates as a load. 13
7.5.2 PELS / NELS Inverter P/N Channel Enhancement Load Saturation Mode Inverter The resistor loads is replaced by an enhancement type transistor which operates in saturation mode. In order to operate the load in saturation the gate of the load transistor is connected to V DD. (W/L) L (W/L) D Ref.: Hodges & Jackson, Analysis and Design of 14
7.5.2 PELS / NELS Inverter P/N Channel Enhancement Load Saturation Mode Inverter The resistor loads is replaced by an enhancement type transistor operates in saturation mode. In order to operate the load in saturation the gate of the load transistor is connected to V DD. v gain = g g md ml = ( W L) D = K R ( W L) L K = R ( W L) D ( W L) L Voltage transfer characteristic of a NELS inverter. Ref.: Hodges & Jackson, Analysis and Design of 15
7.5.2 PELS / NELS Inverter P/N Channel Enhancement Load Saturation Mode Inverter PELS or NELS inverters have the disadvantage that the output voltage in the high state is always smaller that operating voltage V DD. The output voltage is reduced by the effective threshold voltage. The effective threshold voltage is the threshold voltage which is influence by the bulk voltage which applied to the substrate. Furthermore, the PELS / NELS inverters are limited by the differential drain source resistance of the load transistor. As the transistor operates in saturation the differential drain source resistance is rather large, which limits the switching speed of the inverter. The differential drain source resistance can be reduced by operating the load transistor in the linear region. This can be achieved by using an additional voltage supply which provides a gate voltage for the load transistors. The reduced differential drain source resistance leads to an decreased switching speed of the inverter. However, the reduced differential drain source resistance leads to an increased power consumption of the inverter. 16
7.5.3 PELL / NELL Inverter P/N Channel Enhancement Load Linear Mode Inverter Therefore, the static, the dynamic behavior and the power consumption has to be considered when designing an inverter. Ref.: Hodges & Jackson, Analysis and Design of 17
7.5.4 CMOS Inverter 7.5.4.1 CMOS Technology CMOS technology refers to Complementary MOS technology, which means that transistors always exists as a pair of a p-channel and a n-channel transistor. CMOS technology is the driving force behind most of the electronic applications today. All microprocessors and solid state memories use CMOS technology. The main advantage of CMOS technology is the low power dissipation. As a consequence very high integration densities can be achieved. In the following we will discuss the realization of CMOS circuits and its advantages. We will discuss the implementation of a CMOS inverter which is the bases of all digital gates. All other logical gates like OR, AND, NOR, and NAND can be derived from an inverter structure. 18
7.5.4.1 CMOS Technology In order to realize NMOS and PMOS field effect transistors on the same substrate the individual transistors have to be insulated from each other. Different implementation of CMOS technology. Ref.: M. Shur, Introduction to Electronic Devices 19
7.5.4.2 Static behavior A CMOS inverter circuit consist of two matched enhanced type MOSFETs, one transistor with a n- channel and the other transistor with a p-channel. The circuit operation can be discussed based on its extreme cases, meaning V in =0 and V in =V DD is applied to the input of the inverter. V in =0 corresponds to a logic 0, whereas V in =V DD corresponds to a logic 1. As the circuit is symmetric a definition of a load and a driver transistor is not necessary, because the reverse definition would lead to the same results. CMOS inverter and simplified circuit description of a CMOS inverter. 20
7.5.4.2 Static behavior The output curve of an inverter (Voltage transfer curve, VTC) can be derived from the superposition of the output curves of the two (PMOS and NMOS) FETs. The operating point of the inverter corresponds to the interceptions of the two output curves. The interception of the output curves of the two MOSFETs of an inverter represent the output of the inverter. Ref.: M.S. Sze, Semiconductor Devices 21
7.5.4.2 Static behavior The output curve of an inverter (Voltage transfer curve, VTC) can be derived from the superposition of the output curves of the two (PMOS and NMOS) FETs. Voltage transfer curve of an CMOS inverter. The points A, B, C and D correspond to the points A, B, C and D on the previous slide. Ref.: M.S. Sze, Semiconductor Devices 22
7.5.4.3 Static power Dissipation The static power dissipation of a CMOS inverter is negligible as always one of the two transistors is in the off state. The dissipation is independent of the input state of the inverter. The power dissipation of CMOS inverters is distinctly lower than the dissipation of alternative inverter circuits (e.g. NMOS or PMOS FETs in enhanced or depletion mode). However, as the number of gates steadily increases the dynamic power dissipation has become a serious issue. 7.5.4.4 Dynamic behavior of an CMOS inverter The dynamic power dissipation can be determined by: P D = f C equi V 2 DD Dynamic power dissipation of an CMOS inverter where f is the switching frequency. C equi is the equivalent input capacitance of a CMOS inverter and V DD is the operating voltage. 23
7.5.4.4 Dynamic behavior of an CMOS inverter As an inverter typically drives another logical gate, the capacitive load of an inverter is determined by the input capacitance of the next inverter stage. The transient response of an inverter is comparable with the transient response of a RC circuit. The capacitance is formed by the input capacitance of an inverter stage. The channel resistance of the transistor in the on state determines the resistor. Schematic illustration of the operation of a CMOS inverter including the voltage transfer curve and the power dissipation. Ref.: M. Shur, Introduction to Electronic Devices 24
7.5.4.5 Summary of CMOS inverter Based on the above described device behavior we can summarize the ideal behavior of an CMOS inverter: The output levels should either be either 0V or V DD. As a consequence the signal swing between the two levels should be maximized. The static power dissipation of an inverter is close to zero, if the leakage current of the transistors can be neglected. As a CMOS inverter is symmetric the power dissipation is independent of the logical output state. A low resistance path exists between the output terminal and ground (in the 0 state) or V DD (in the 1 state). The low resistance path ensures that the output voltage is independent of the transistor dimensions. As we use identical transistors for the driver and the load of the CMOS inverter a change of the dimensions of the FETs has no impact on the output voltage of the inverter. The input resistance of the inverter is infinite, because the input current is close to zero. Thus a large number of similar inverters can be driven with no loss on the signal level. 25
7.6 From CMOS inverters to logical gates Inverters are elementary components of digital logic circuits. All circuits can be reduced to inverter circuits. In the following the gained knowledge on CMOS inverters will be used to design simple logical CMOS circuits. We will concentrate here on basic structure, where the output signal is a direct combination of the input signals. Memory elements will not be taken into account. 26
7.6.1 Complementary Logic In general, a CMOS inverter can be described by a NMOS pull-down transistor and a PMOS pull-up transistor, which operate in a complementary fashion. We will now apply the pull-up and pull-down concept to logical gates with more than one input signals. Therefore, we define two networks, a pull-down network (PDN) and a pull-up network. The networks operate in a complementary fashion. Let us assume we want to realize a logic gate with three input signals. As a consequence, both networks (pull-up and the pull-down network) will have three input signals. Nevertheless the number of output states is still two (0 and 1). The pulldown network is able to pull down the output signal for the possible low ground states. Opposite applies for the pull-up network. The network is able to pull-up the output signals for all high or positive states. Pull-up and pull-down network. Ref.: B. Jacob, University of Maryland 27
7.6.1 Complementary Logic Since the PDN comprises of NMOS transistors and the NMOS transistors conduct when the input signals is high, the PDN is active when the input signals are high. In a complementary manner, the PUN comprises PMOS transistors and PMOS transistors conduct when the input signal is low. Therefore the PUN is active for low input signals. Based on this scheme we can deduce the operation of logic gates like NOR, NAND, OR or AND. 28
7.6.1 Complementary Logic Implementation of a NOR gate: M2 The output signals get low if one of the input signals gets high. If A or B or both signals gets high one or two of the PMOS transistors pulls the output signal down. At the same time one or both of the NMOS transistors are in their off state, so that the output signal gets low. input A input B A B Out M1 M2 M1 out 0Vdc V1 0 0 1 0 1 1 1 0 1 0 0 0 Y = A + B = AB Implementation of an NOR logical gate with two inputs based on CMOS technology. 29
7.6.2 Transmission gate logic Besides complementary implementations of digital circuits, there is one additional transistor circuit frequently used in CMOS digital electronics. This circuit is called transmission gate (TG). A transmission gate is used as a bidirectional switch. The circuit consists of an n-channel transistor and a p-channel transistor in parallel. The two types of transistor are used as a p-channel FET pass on a 1 and an n-channel FET passes on a 0. Transmission gate. Ref.: Logic and Computer Design Fundamentals, Prentice-Hall, Inc. (1997) 30
7.6.2 Transmission gate logic Depending on the logic function which has to be implemented it can be advantages to use transmission gate (pass logic) rather than complementray logic. This is particularly true of XOR or multiplexers have to be implemented. Complementary Implementation Implementation of a NOR gate by using a complementary and a transmission gate approach. Ref.: B. Jacob, University of Maryland 31
7.6.2 Transmission gate logic Implementation of a XOR gate by using a complementary and a transmission gate approach. Ref.: B. Jacob, University of Maryland 32
References Michael Shur, Introduction to Electronic Devices, John Wiley & Sons; (January 1996). (Price: US$100), Audience: under graduate students Simon M. Sze, Semiconductor Devices, Physics and Technology, John Wiley & Sons; 2 nd Edition (2001). (Price: US$115), Audience: under graduate students R.F. Pierret, G.W. Neudeck, Modular Series on Solid State Devices, Volumes in the Series: Semicondcutor Fundamentals, The pn junction diode, The bipolar junction transistor, Field effect devices, (Price: US$25 per book), Audience: under graduate students Adel S. Sedra, Kenneth C. Smith, Microelectronic Circuits, Oxford University Press (1998), (Price: 100-120 Euro). 33