Original scientific paper Teperature process copensated F power detector Milenko Milićević 1 Branislava Milinković 1 Đorđe Siić Dušan Grujić 1 Lazar Saranovac 1 1 School of Electrical Engineering University of Belgrade Belgrade Serbia TES Electronic Solutions Stuttgart Gerany Journal of Microelectronics Electronic Coponents Materials Vol 46 No 1(016) 4 8 Abstract: This paper describes the design of process teperature copensated wide b radio frequency power detector in a stard UMC 013-µ F CMOS process Proposed power detector core consists of two F NMOS transistors biased for operation in weak inversion output signal of the power detector core is a linear function of input F peak voltage residual teperature dependence Additional copensation circuit is designed in order to ake the output voltage less sensitive on teperature process variation Power detector circuit has 0 db of the dynaic range is especially suitable for use in transitter chain applications The teperature copensation provides typical reduction of 50% in teperature sensitivity of the circuit Keywords: F power detector; teperature copensation; weak inversion; Bessel function; copensation circuit Teperaturno in procesno kopenziran F detector oči zvleček: Članek opisuje dizajn procesno in teperaturno kopenziranega detektorja oči širokopasovne radio frekvence v stardni UMC 013-µ F CMOS tehnologiji Jedro detektorja se sestoji iz dveh F NMOS tranzistorjev za delovanje v slabi inverziji zhodni signal detektorja je linearna funkcija vhodne F napetosti in ostanka teperaturne odvisnosti Dodatno kopenzacijsko vezje znižuje teperaturno in procesno odvisnost Dinaično obočje detektorja oči je 0 db in je posebej prieren za uporabo v prenosnih verigah Teperaturna kopenzacija tipično za 50 % zanjša vpliv teperature Ključne besede: F detektor oči; teperaturna kopenzacija; šibka inverzija; Besselova funkcija; kopenzacijsko vezje * Corresponding Author s e-ail: ilenkoilicevic@tes-dstco 1 ntroduction Power detectors are widely used in wireless counication systes in receiver transitter chain Optial gain setting of the receiver chain is highly dependent on the power level of the input signal n order to eet optiu gain power level of the input signal should be easured in real tie appropriate gain adjustent of the receiver chain should be perfored Characteristic for this application is that it requires the dynaic range of power detector circuit exceeding 50 db or ore n any applications transitter should be capable to operate with variable peak level of the output power n order to obtain accurate power gain control power detector should be eployed in the control feedback loop [1] Power detectors are also used for: power aplifier eergency shutdown in case of high VSW [] predistortion linearization of power aplifier using envelope-feedback [3] or as a part of syste for envelope eliination restoration power aplifier [4] Power detectors for transitter applications have relaxed dynaic range requireents copared to those eployed in receiver but other factors ay be of iportance Self-heating of the power aplifier affects the perforance of power detectors by changing their accuracy [5] n order to have teperature independent behavior power aplifier power detector are usually designed together due to the large utual influence [5] Another constraint for power detectors is requireent for low power consuption in order to keep high level efficiency of the overall syste There are few groups of the power detectors ixer based [6] Schottky diode [7] onolithic low power 4 MDEM Society
M Milićević et al; nforacije Mide Vol 46 No 1(016) 4 8 F peak detector [8] First two topologies are not quite suitable for CMOS F C ipleentation regarding: unavailability in stard CMOS F process bwidth liitation large chip size high power consuption etc Monolithic low power F peak detector is ost suitable for F C ipleentation due to its advantages of siplicity wide bwidth low power sall chip area [8] However it has teperature process dependence wideb precision power detectors are ostly ipleented in expensive bipolar technology [8] n this paper onolithic low power process teperature independent F peak detector has been developed t uses NMOS transistors biased in weak inversion in order to get the exponential transistor behavior Additional circuit for teperature process copensation has been proposed The new detector uses inexpensive F CMOS technology provides teperature process independent power detection without post-fabrication triing The paper structure is as following: the design of the power detector core circuit is presented in Chapter Topology design of the new teperature copensation circuit is presented in Chapter 3 Obtained siulation results post processing with possible applications are presented in Chapter 4 5 respectively Finally conclusion is introduced in Chapter 6 n order to obtain exponential behavior transistors M 1 M are biased for operation in weak inversion Transistors have the sae channel width nuber of fingers length their bias currents are equal 1 = = DC Corresponding resistors capacitors are atched naely 1 = 3 = 4 C 1 =C n this case the AC signal agnitude at gate M 1 is two ties greater than at the M gate With given assuptions instantaneous average drain currents of transistor M 1 are: Vgs1 Vt VQ V + T VOUT V cos( ω0t) D1 = S = S i e e e e VQ VT VOUT + T V V Q VT VOUT + cos( ω0t) nv 1 t id1 1 DC Se e e dt Se e 0 V = = = = T 0 (1) () Average drain current of transistor M is: VQ V T VOUT nv V t id = = DC = Se e 0 Where: V - peak aplitude of AC input signal V Q - gate DC voltage 0 (x) - odified Bessel function of order zero n - technology dependant sub-threshold slope paraeter Fro () (3) it can be seen that average drain current is increased by a factor 0 (V / V t ) when F signal is present Since the odified Bessel function of order zero is onotonically increasing the average drain current onotonically increases with F signal aplitude (3) Proposed F power detector The core of the F power detector is shown in Figure 1 However the average (DC) current of transistors M 1 M is constant set by current sources 1 Therefore the average gate-source voltage V gs ust decreases for () (3) to hold This change in average V gs due to input F signal aplitude is the basis of power detector operation For large values of x 0 (x) has an asyptotic approxiation: 0 ( ) e x π x x (4) Using equations () (3) the output voltage can be written as: + OUT = OUT OUT V V V (5) Figure 1: F power detector core scheatics V 0 VOUT = ln V 0 nv t f we apply approxiation (4) on the equation (6) we can get: (6) 5
M Milićević et al; nforacije Mide Vol 46 No 1(016) 4 8 V V OUT PD = ln() (7) Where: kt Vt = (8) q Fro equation (7) it can be recognized that the average output voltage consists of two factors First ter is proportional to the peak value of the input signal the second ter is proportional to the teperature Teperature-dependent ter can be cancelled by including an additional circuit in the design which produces the output voltage proportional solely to the teperature Teperature dependence of the signal described in equation (7) ay be iniized to a large extent by subtracting the power detector voltage fro copensation circuit output Design of teperature copensation circuit is presented in the following section 3 Copensation circuit Figure presents topology of the copensation circuit that is used for copensation of the teperature dependent part in equation (7) Like in the core of the F power detector transistors M A M B are operating in weak inversion Transistor M A has the sae diensions the sae biasing conditions as transistors M 1 M in the power detector core The width of the transistor M B is two ties greater than the width of M 1 they have sae value of bias currents Transistors M C M D M E operate as current irrors should be perfectly atched n order to keep sae drain voltages in current irrors transistor M F has been eployed it has to be atched with M A Additionally the bias resistors should also be atched A = B = E The output current D of the circuit in the Figure is given by the equation (9) V V GS1 GS D = (9) 3 Since transistors M A M B are operating in the weak inversion the output current is given with: D D D ln ln VGS1 VGS S1 S = = 3 3 (10) are equal Furtherore copensation circuit could be used as a current source for the power detector core Figure : Copensation circuit Output voltage of the circuit in Figure is given with the following equation: V COMP F ln() = VDD (1) E n order to get teperature independent signal signals at the outputs of the power detector core calibration circuit (given with equations (7) (1)) should be subtracted given the value for the copensated output voltage of the power detector circuit V 1 F VOUT VCOMP = VDD + ln() E (13) f the value of the resistor F is two ties saller than value of B we can get: V V V V = (14) OUT COMP DD Fro last equation it can be recognized that the output voltage is teperature process independent 4 Siulation results Based on the previous discussion power detector core copensation circuit are designed in stard UMC 130n CMOS F technology Paraeters of all coponents are shown in Table 1 D S ln S1 ln() = = 3 3 (11) resistor value C should be set in a way that currents D DC fro detector circuit core shown in Figure 1 6
M Milićević et al; nforacije Mide Vol 46 No 1(016) 4 8 Table 1: Paraeters of the coponents Coponents M1 M MA MF MB MC MD ME C F A B E 1 3 4 C C1 C C3 1 Paraeter W/L [μ/μ] W/L [μ/μ] W/L [μ/μ] Capacitance [pf] Current [μa] Value *(5/034) 4*(5/034) 4*(4/5) 39 1961 60000 5 10 10 Layout of coplete chip is presented in Figure 3 Figure 4: Voltage coefficient of the signal at the output of the power detector Figure 4 presents voltage sensitivity VOUT/ V of the output signal perfored at frequency of 5GHz The dynaic range of the input signal aplitude can be estiated fro this figure Lower liit is deterined by odified Bessel function approxiation given in the equation (4) Naely this approxiation is valid for input AC aplitude greater than 0 V Upper liit presents the highest peak level of the voltage input signal for which all transistors are in saturation This voltage is deterined to be V giving the operation range of the power detector of approxiately 0 db t can be concluded that power detector works with high aplitude level of the input signal what is desirable for F transitters Figure 5: Copensated (red) non-copensated (green) teperature coefficient of the output signal 5 Post processing applications Post processing can be done in analog or digital doain Each of these options will be discussed in the details including advantages drawbacks as well as possible applications 51 Analog post processing Straightforward way to cobine the power detector core with the copensation circuit is to use instruentation aplifiers to perfor subtracting aplifying Figure 3: Power detector with calibration circuit The power detector is siulated with without the copensation circuit in order to deonstrate the iproveent Siulations were perfored for AC signal agnitude of 1 V frequency of 5 GHz proveent is reached in industrial teperature range of -40 0C to 100 0C Maxiu teperature coefficient ( VOUT/ T)MAX is decreased about two ties using this technique The ost iportant paraeter for the aplifiers would be input offset in order to keep high level of accuracy Clear advantage is siple design ability to detect input aplitude independently of process or teperature variation Main disadvantage is sall dynaic range 0dB Although there are soe applications 7
M Milićević et al; nforacije Mide Vol 46 No 1(016) 4 8 where this ight be enough as; aplifier linearization techniques [9] including polar loop syste [10] aplitude envelope feedback syste [10] 5 Digital post processing Dynaic range ight be increased using digital post processing Power detector output voltage (6) copensation circuit output voltage (1) could be sapled post processed in digital doain Paraeter nv t ight be extracted fro (1) be used in (6) for extraction of the aplitude V Dynaic range is extended since there is no need for the asyptotic Bessel function approxiation (4) Drawback would be coplex design This technique could be used for broad range of applications where teperature process independent aplitude detection is needed 6 Conclusion Today inexpensive scaling CMOS technology allows large level of integration operation of the circuits at high frequencies ts ain disadvantage is liitation of the process control which leads to large variation of coponent paraeters Wide teperature operation range liits the accuracy of power detector due to teperature-dependent ters in output voltage n soe particular cases this liitation can be solved by using such circuit topologies which perforance depends only of well controlled coponent atching This paper presented design of such power detector including copensation circuit Using the proposed described circuit topology significantly lower teperature dependence of the power detector circuit has been achieved Naely axiu teperature coefficient is decreased about two ties for input signal level between 0 V V Power detector teperature dependency is iniized to the extent that it can be neglected in any industrial applications enabling its widespread use in further designs For applications which require higher dynaic range digital post processing could be applied 7 Acknowledgent This work has been supported by SENSEVE project founded by European Coission as a part of Marie Curie Progra 8 eferences 1 Xiaofang Mu; Alon Z; Zhang G; Shiaw Chang Analysis of output power variation under isatched load in Power Aplifier FEM with directional coupler Microwave Syposiu Digest 009 Ullrich Pfeiffer David Goren A 0 db Fully-ntegrated 60 GHz SiGe Power Aplifier With Autoatic Level Control EEE Journal of Solid State Circuits vol 4 Nuber 7 July 007V 3 Hyun-Min Park; Dong-hyun Baek; Jeon Kye-k; Songcheol Hong A predistortion linearizer using envelope-feedback technique with siplified carrier cancellation schee for class-a class- AB power aplifiers Microwave Theory Techniques EEE Transactions on vol48 no6 pp898904 Jun 000 4 Feipeng Wang; Kiball D; Popp J; Yang A; Lie DYC; Asbeck P; Larson L Wideb envelope eliination restoration power aplifier with high efficiency wideb envelope aplifier for WLAN 8011g applications Microwave Syposiu Digest 005 EEE MTT-S nternational vol no pp4 pp 1-17 June 005 5 Hiroyuki Nakaoto Masahiro Kudo Kiitoshi Niratsuka Toshihiko Mori Shinji Yaaura A real-tie teperature-copensated CMOS F on-chip power detector with high linearity for wireless applications ESSCC page 349-35 EEE (01) 6 P F Da Mota J M Da Silva A true power detector for F PA built-in calibration testing in Proc Design Autoation & Test in Europe Conference 011 pp 1-6 7 V Milanovic M Gaitian JC Marshall ME Zaghloul CMOS Foundry pleentation of Schottky Diodes for F Detection EEE Transactions on Electron Devices vol 43 Nuber 1 Deceber 1996 8 T Zhang W Eisenstadt M Fox A novel 5GHz F power detector Proc nternational Syposiu on Circuits Systes vol 1 pp 897-900 004 9 Steve C Cripps F Power Aplifiers for Wireless Counication Second Edition Artech House 006 10 Steve C Cripps Advance Techniques in F Power Aplifier Design Artech House 00 Arrived: 04 1 015 Accepted: 0 03 016 8