EFFICIENT LOW POWER DYNAMIC COMPARATOR FOR HIGH SPEED ADC s

EFFICIENT LOW POWER DYNAMIC COMPARATOR FOR HIGH SPEED ADC s B.Padmavathi, ME (VLSI Design), Anand Institute of Higher Technology, Chennai, India krishypadma@gmail.com Abstract In electronics, a comparator is a device that compares two voltages or currents, and switches its output to larger, smaller or equal. To obtain low power, delay reduction and high performance of the comparator, double tail dynamic comparator is used. Conventional dynamic comparator and conventional double tail comparator are called as regenerative comparators and its power is fully analyzed. Higher power consumption will reduce the life time of the voltage source. The time taken between the executions of the applied input to obtain the output is called delay. In this paper a dynamic comparator is introduced and thus the circuit of a double tail comparator is modified for low power and fast operation even in low supply voltages. In proposed double tail comparator, in order to reduce the complicated design, few transistors are added to strengthen the circuit and results in reduced power and delay time. Power consumption and delay time are significantly reduced in proposed comparator. The Simulation is done in Tanner EDA tool in 250nm Technology. Index Terms Double-tail comparator, dynamic clocked comparator. I. INTRODUCTION Comparator is a device that compares two currents or voltages and produces digital output signal which is indicating larger. After an operational amplifier, comparators are the most generally used analog simple integrated circuits. In ultra deep sub micrometer (UDSM) CMOS technologies the high speed comparators suffers from low supply voltages. If the supply voltage is smaller means, then the designing of high speed comparators is more challenging. Supply boosting methods employs the body-driven transistors current mode design and it uses dual-oxide process, which can handle higher supply voltages have been developed to meet the low voltage K.Suhanandini, Department of ECE, Anand Institute of Higher Technology, Chennai, India design challenges. To overcome the switching problems boosting and bootstrapping techniques are used. The body driven technique is used to remove the threshold voltage and it suffers from smaller transconductance. Efficient power and fastest comparators generate more kickback noise. Kickback noises are reduced by kickback reduction techniques. In electronics, Operational amplifier is designed to be used with negative feedback. It can be also used as comparator in open loop configuration. On the other hand, Comparator is especially designed for open loop configuration without any feedback. Hence it is the second most widely used device in electronic circuits after Op-amp. Comparators are mostly used in analog to digital converter (ADCs). In the conversion process, first the input signal is sampled. Then the sampled signal is applied to a number of comparators to determine the digital equivalent of the analog value. Apart from that, comparators are used in peak detectors, zero crossing detectors, BLDC operating motors, switching power regulators [Samaneh Babayan Mashhadi (2014)]. Nowadays, where demand for portable battery operated devices is increasing, a major importance is given towards low power methodologies for high speed applications. Also we have to minimize the power consumption by using smaller feature size processes. Now comparators are used in ADCs and require less power dissipation, high speed, less delay, less offset voltage, low noise, better slew rate, less hysteresis etc. In order to achieve these specifications, the building block of ADC i.e. comparator must be tightly constrained. Nowadays dynamic comparators are used in ADCs because these comparators have high speed, less power dissipation, zero static power consumption. Also back-to-back inverters are used in dynamic comparators to provide positive feedback mechanism which converts a smaller voltage difference to full scale digital level output [Samaneh Babayan- Mashhadi(2014)]. Parasitic node capacitance and output load capacitance are limited by the accuracy of such comparators. II. DYNAMIC COMPARATOR A. Offset voltage in dynamic comparator Comparators have a crucial influence on the overall performance in high-speed analog-to-digital converters. 75

Dynamic comparators are widely used in the high speed ADCs due to its low power consumption and fast speed. However, thorough traditional comparator is built by an operational amplifier [2]. To overcome the difficulties in determining the operation regions and bias conditions of transistors in a dynamic comparator. we propose a balanced method to calculate the input offset voltage when the mismatch exists, and this proves that a voltage equal to the input offset voltage is virtually applied to one of the inputs of the comparator to cancel the mismatch effects and make the comparator with mismatch to reach a balanced stage [3]. By balancing this condition, the currents in the two branches are symmetric at any time. transistor drain current. By equivocating the PMOS transistor will turn on by initiating the latch regeneration speed which is caused by back to back inverters such as, and. If < the circuits works vice versa and thus pulls the outn to and INN/INP discharges the output to ground. The delay of the comparator is comprised of two time delay and. The delay represents the capacitive discharging of the load capacitance until the first p channel transistors and turns on. B. Clocked regenerative comparator Clocked regenerative comparators are used to get low power, low delay and high speed ADC s. It has found wide applications in many high speeds ADC s since they can make fast decisions due to the strong positive feedback in the regenerative latch. By presenting many comprehensive analyses, which investigate the performance of these comparators from different aspects such as noise, offset random decision errors and kick back noise. The delay time and power of the conventional dynamic comparator and conventional dynamic double tail comparator are analyzed based on the proposed comparator. III. VARIOUS DYNAMIC COMPARATOR TECHNIQUES A. Conventional dynamic comparator technique The conventional dynamic comparator are used in analog to digital converters, with high input impedance, and no static power consumption are consumed. The operation of the comparator is that, during the rest phase when clock is equal to zero will be in off condition and the reset transistors and will pull both output nodes outp and outn to for defining a start condition and to have a valid logical level during the reset phase. In the comparison phase, when clock = transistors and are in off condition and is in on condition. Hence the output voltages such as outn and outp had been pre- charged to and thus start to discharge with different discharging rates depending on the corresponding input voltage INN/INP. By assuming > outp discharges faster than outn, and hence outp had been discharged by transistor drain current and thus fall down to - before that outn had been discharged by Fig.1.Schematic diagram of conventional dynamic comparator. The voltage at node INP is bigger than INN that is > means the drain current of transistor ( ) will causes the faster discharge at outp node when compared to the outn node where the smaller current is driven by.since and thus the small differential input, I2 can be approximated to equal and half of the tail current. The is the latching delay of two cross-coupled inverters. By assuming a voltage swing of = /2, has been obtained from an initial output voltage difference of at the falling output, for example outp.70% of the supply voltage is optimal regarding speed and yield for an input common mode voltage. The parasitic capacitances of input transistors do not affect directly the speed of the switching at the output nodes, and thus to minimize the offset it is possible to design large input transistors. Due to stacking of several transistors, a sufficiently high supply voltage is needed for a proper delay time. 76

Fig.2.Transient simulations of the conventional dynamic comparator. The drawback of this structure is that there is only one current path via tail transistor such as which allows the current for both the differential amplifier and the cross-coupled inverters. The large tail current would be desirable to enable fast regeneration in the cross-coupled inverters. differential voltage will be built up. The intermediate stage formed by and passes to the crosscoupled inverters and also provides a good shielding between input and output stage resulting in reduced value of kickback noise. Similar to the conventional dynamic comparator, the delay of the comparator comprises two main parts and. The delay says the capacitive charging of the load capacitance until the first n channel transistor and turns on after by which the latch regeneration starts. B. Conventional double tail dynamic comparator technique The conventional double tail dynamic comparator has another tail at the top of the circuit to operate at low voltages to get the better performance of the comparator. Conventional double tail dynamic comparator has less stacking and therefore can operate at lower supply voltages compared to the conventional dynamic comparator. The double tail has large current in latching stage and wider at the for fast latching independent of the input common-mode voltage and a small current in the input stage at the small for low offset voltage. During the reset phase when clock is equal to zero and are in off condition, and then the transistors and precharge the nodes fn and fp to, which in turn causes the transistors and to discharge the output nodes to ground. Fig.4.Transient simulations of conventional double tail dynamic comparator. The voltage difference at the first stage outputs at time has an effect on latch initial differential output voltage at and consequently on the latch delay. Therefore by increasing it would reduce the delay of the comparator. In this comparator, both intermediate transistors stage will be finally cut off and thus nodes at fn and fp discharges to ground. During the reset phase, these nodes have to be charged from ground to, which means power consumption is consumed. C. Double tail dynamic comparator Fig.3.Schematic diagram of conventional double tail dynamic comparator. During decision making phase when clock is equal to then and are in on condition and the transistors and are in off condition and thus the voltages at nodes fn and fp start to drop with different rates which is defined by /(. And on top of this an input dependent Due to the better performance of double tail structure in low voltages given below: a) Double tail structure using control transistor The comparator is designed based on the double tail structure. The design of the dynamic comparator is to increase in order to increase the speed of the latch regeneration. Due to this, two control transistors and have been added to the first stage in parallel to and transistors in a 77

cross-coupled manner. During reset phase when clock is equal to zero and are in off condition and static power is avoided. And thus the transistors and pulls both fn and fp nodes to, and hence the transistor and are in cut off condition. Intermediate stage transistors and reset both latch outputs to ground. During the decision phase when clock is equal to, then and are in on condition and thus the transistors and are in off condition. At the beginning of the phase, the control transistors are still in off condition since fn and fp nodes are about to. The delay says the capacitive charging of the load capacitance until the first n channel transistor and turns on after by which the latch regeneration starts. Fig.6.Transient simulations of dynamic comparator using control transistor. If fn falls continuously means then the corresponding PMOS control transistor in this case starts to turn on, pulling fp back to the, so another control transistor remains in off condition and allowing fn to be discharged completely. Like conventional double tail dynamic comparator, in which is just a function of input transistor transconductance and input voltage difference in the double tail dynamic structure as soon as the comparator detects that for instance fn node discharges faster than fp node, a PMOS transistor turns on, by pulling the other node such as the fp node back to. Therefore the difference between fn and fp increases, leading to the reduction of the time of latch regeneration speed. Fig.5.Schematic diagram of dynamic comparator using control transistor. Thus the nodes fn and fp start to drop with different discharging rates according to the input voltages. If suppose > then the node fn drops faster than fp since provides more current than. Fig.7.Schematic diagram of dynamic comparator using control transistor with NMOS transistor. b) Double tail structure using control transistor with NMOS transistor. The main design is that when one of the control transistors for example turns on a current is drawn from to the ground via input and tail transistor for example, and resulting in static power consumption. To overcome this, two NMOS switches are used below the input transistors named as and.at the beginning of the decision making phase both fn and fp nodes have been precharged to and during the reset phase, both switches are closed and fn and fp nodes start to drop with different discharging rates. Thus the comparator detects that one of the fn/fp nodes discharges faster when two control transistors act in a way to increase their voltage difference. If fp is pulling up then fn 78

should be discharged completely and hence the switch in the charging path of fp will be opened but the other switch connected to fn will be closed to allow the complete discharge of fn node. Fig.8. Transient simulations of dynamic comparator using control transistor with NMOS transistor. D. Proposed dynamic comparator with sleep approach technique The comparator is designed based on the double tail structure. The design of the dynamic comparator is to increase in order to increase the speed of the latch regeneration. Due to this, two control transistors and have been added to the first stage in parallel to and transistors in a cross-coupled manner. During reset phase when clock is equal to zero,, 3, 4 are in off condition and static power is avoided. And thus the transistors and pulls both fn and fp nodes to, and hence the transistor and are in cut off condition. Intermediate stage transistors and reset both latch outputs to ground. During the decision phase when clock is equal to, then,, 3, 4 are in on condition and thus the transistors and are in off condition. At the beginning of the phase, the control transistors are still in off condition since fn and fp nodes are about to. The delay says the capacitive charging of the load capacitance until the first n channel transistor and turns on after by which the latch regeneration starts. Fig.9. Schematic diagram of dynamic comparator using sleep approach technique. Fig.10. Transient simulations of dynamic comparator using sleep approach technique. Table 1: Comparison table. Logics used Conventional dynamic comparator Power consumed (in watts) 4.473195e- 004watts Delay Time (ns) -17.8846n 79

Conventional double tail dynamic comparator Dynamic comparator with control transistor Dynamic comparator with control transistor using NMOS transistor Proposed dynamic comparator with sleep approach 1.321605e- 003watts 2.950686e- 004watts 2.329131e- 005watts 1.546399e- 005watts IV CONCLUSION -180.1412n -199.2610n -239.0565n -243.1945n Thus power reduction is calculated using tanner EDA in 250nm technology for various circuits such as Conventional single tail dynamic comparator and conventional double tail dynamic comparator and all these circuits are tested separately. Circuits are implemented with the single tail and double tail to get low power even in small supply voltages. Simulation results infer that power reduction is more in the proposed dynamic comparator. [5] Murmann et al. B (Sep. 2006), "Impact of scaling on analog performance and associated modeling needs," IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2160-2167. [6] Miyahara.M.,Asada.Y,,Daehwa.P, & Matsuzawa. A (Nov 2008), A low-noise self-calibrating dynamic comparator for high-speed ADCs, In Proc. A-SSCC, pp. 269 272. [7] Miyahara. M., et al. (2009), A low-offset latched comparator using zero-static power dynamic offset cancellation technique, In IEEE A-SSCC, Taiwan, pp. 233 236. [8] Nikoozadeh.A, and Murmann.B (Dec. 2006), An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch, IEEE Trans. Circuits Syst.II: Exp. Briefs, vol. 53, no. 12, pp. 1398-1402. [9] Schinkel.D, Mensink.E, Kiumperink.E, van Tuijl.E and Nauta.B (Feb. 2007), A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time, ISSCC Dig. Tech. Papers, pp. 314-315 and 605. [10] Song. W, Choi. H, Kwak. S, & Song. B (1995), A 10-b 20- M sample/s low power CMOS ADC, IEEE Journal of Solid-State Circuits, 30(5), 514 521. [11] Steyaert.M, Crols.J, and Van der Plas.G (1994), "A high performance RDS-detector for low voltage applications," Analog Integrated Circuits and Signal Processing, Special issue on lowvoltage low-power analog integrated circuits, 1994. [12] Tanimoto et al.h (July1991),"Realization of a 1 V active filter using a linearization technique employing a plurality of emitter coupled pairs," IEEE J.Solid-state Circuits, vol. 26, pp.937-945, July 1991. [13] Wicht.B, Nirschl.T, and Schmitt-Landsiedel.D (July1994), Yield and speed optimization of a latch-type voltage sense amplifier, IEEE J. Solid-State Circuits, vol. 39, pp. 1148-1158. [14] Wong1 K.-L. J, and Yang C.-K. K. (May 2004), Offset compensation in comparators with minimum input-referred supply noise, IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 837 840. [15] Wong. J, et al. (May2004), Offset compensation in comparators with minimum input-referred supply noise, In IEEE JSSC, pp. 837 840. [16] Tutorial: Electronic Circuits-Op-amps Comparator, Renesas Engineer School. [17] Op-amp comparator schematic symbol-electrical Engineering Stack Exchanging [18] http://www.electronicstutorials.ws/combinations/comb-8html [19] http://www.cs.mun.cu/~paul/transistor/node1.h1tml REFERENCES [1] Cho. T, and Gray. P(1995), A 10 b, 20 Msample/s, 35 mw pipeline A/D Converter, IEEE Journal of Solid-State Circuits, 30(3), 166 172. [2] DESSOUKY. M, and KAISER. A: Very low voltage digital audio AX modulator with 88-dB dynamic range using local switchbootstrapping, IEEE J Solid-Slole Cireuits, 200 I, 36, (3) [3] He.J, Zhan.S, Chen.D, and Geiger. R.L (May 2009), Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators, IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 56, pp. 911-919. [4] Kobayashi.T, Nogami.K, Shiroto.T, and Fujimoto.Y (Apr.1993), A current controlled latch sense amplifier and a static power-saving input buffer for low-power architecture, IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523 527. 80