Power Distribution Networks with On-Chip Decoupling Capacitors

Power Distribution Networks with On-Chip Decoupling Capacitors

Mikhail h Popovich Andrey V. Mezhiba Eby G. Friedman Power Distribution Networks with On-Chip Decoupling Capacitors ABC

Mikhail Popovich University of Rochester Rochester, NY USA Andrey V. Mezhiba Intel Corporation Hillsboro, OR USA Eby G. Friedman University of Rochester Rochester, NY USA Library of Congress Control Number: 2007931772 ISBN 978-0-387-71600-8 e-isbn 978-0-387-71601-5 2008 Springer Science + Business Media, LLC All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science + Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. 987654321 springer.com

To Oksana and Elizabeth To Elizabeth To Laurie, Joseph, and Samuel

Preface The purpose of this book is to provide insight and intuition into the behavior and design of power distribution systems with decoupling capacitors for application to high speed integrated circuits. The primary objectives are threefold. First, to describe the impedance characteristics of the overall power distribution system, from the voltage regulator through the printed circuit board and package onto the integrated circuit to the power terminals of the on-chip circuitry. The second objective of this book is to discuss the inductive characteristics of on-chip power distribution grids and the related circuit behavior of these structures. Finally, the third primary objective is to present design methodologies for efficiently placing on-chip decoupling capacitors in nanoscale integrated circuits. Technology scaling has been the primary driver behind the amazing performance improvement of integrated circuits over the past several decades. The speed and integration density of integrated circuits have dramatically improved. These performance gains, however, have made distributing power to the on-chip circuitry a difficult task. Highly dense circuitry operating at high clock speeds have increased the distributed current to many tens of amperes, while the noise margin of the power supply has shrunk consistent with decreasing power supply levels. These trends have elevated the problems of power distribution and allocation of the on-chip decoupling capacitors to the forefront of several challenges in developing high performance integrated circuits. This book is based on the body of research carried out by Mikhail Popovich from 2001 to 2007 and Andrey V. Mezhiba from 1998 to 2003 at the University of Rochester during their doctoral studies under the supervision of Professor Eby G. Friedman. It is apparent to

VIII Preface the authors that although various aspects of the power distribution problem have been addressed in numerous research publications, no text exists that provides a unified focus on power distribution systems and related design problems. Furthermore, the placement of on-chip decoupling capacitors has traditionally been treated as an algorithmic oriented problem. A more electrical perspective, both circuit models and design techniques, has been used in this book for presenting how to efficiently allocate on-chip decoupling capacitors. The fundamental objective of this book is to provide a broad and cohesive treatment of these subjects. Another consequence of higher speed and greater integration density has been the emergence of inductance as a significant factor in the behavior of on-chip global interconnect structures. Once clock frequencies exceeded several hundred megahertz, incorporating on-chip inductance into the circuit analysis process became necessary to accurately describe signal delays and waveform characteristics. Although on-chip decoupling capacitors attenuate high frequency signals in power distribution networks, the inductance of the on-chip power interconnect is expected to become a significant factor in multi-gigahertz digital circuits. An important objective of this book, therefore, is to clarify the effects of inductance on the impedance characteristics of on-chip power distribution grids and to provide an understanding of related circuit behavior. The organization of the book is consistent with these primary goals. The first eight chapters provide a general description of distributing power in integrated circuits with decoupling capacitors. The challenges of power distribution are introduced and the principles of designing power distribution systems are described. A general background to decoupling capacitors is presented followed by a discussion of the use of a hierarchy of capacitors to improve the impedance characteristics of the power network. An overview of related phenomena, such as inductance and electromigration, is also presented in a tutorial style. The following seven chapters are dedicated to the impedance characteristics of on-chip power distribution networks. The effect of the interconnect inductance on the impedance characteristics of on-chip power distribution networks is investigated. The implications of these impedance characteristics on circuit behavior are also discussed. On-chip power distribution grids are described, exploiting multiple power supply voltages and multiple grounds. Techniques and algorithms for the computer-aided design and

Preface IX analysis of power distribution networks are also described; however, the emphasis of the book is on developing circuit intuition and understanding the electrical principles that govern the design and operation of power distribution systems. The remaining five chapters focus on the design of a system of on-chip decoupling capacitors. Methodologies for designing power distribution grids with on-chip decoupling capacitors are also presented. These techniques provide a solution for determining the location and magnitude of the on-chip decoupling capacitance to mitigate on-chip voltage fluctuations. Acknowledgments The authors would like to thank Alex Greene and Katelyn Stanne from Springer for their support and assistance. We are particularly thankful to Bill Joyner and Dale Edwards from the Semiconductor Research Corporation, and Marie Burnham, Olin Hartin, and Radu Secareanu from Freescale Semiconductor Corporation for their continued support of the research project that culminated in this book. The authors would also like to thank Emre Salman for his corrections and suggestions on improving the quality of the book. Finally, we are grateful to Michael Sotman and Avinoam Kolodny from Technion Israel Institute of Technology for their collaboration and support. The original research work presented in this book was made possible in part by the Semiconductor Research Corporation under Contract Nos. 99 TJ 687 and 2004 TJ 1207, the DARPA/ITO under AFRL Contract F29601 00 K 0182, the National Science Foundation under Contract Nos. CCR 0304574 and CCF 0541206, grants from the New York State Office of Science, Technology & Academic Research to the Center for Advanced Technology in Electronic Imaging Systems, and by grants from Xerox Corporation, IBM Corporation, Lucent Technologies Corporation, Intel Corporation, Eastman Kodak Company, Intrinsix Corporation, Manhattan Routing, and Freescale Semiconductor Corporation. Rochester, New York Hillsboro, Oregon June 2007 Mikhail Popovich and Eby G. Friedman Andrey V. Mezhiba

Contents 1 Introduction... 1 1.1 Evolution of integrated circuit technology... 3 1.2 Evolutionofdesignobjectives... 7 1.3 The problem of power distribution... 10 1.4 Deleterious effects of power distribution noise... 17 1.4.1 Signal delay uncertainty... 17 1.4.2 On-chipclockjitter... 17 1.4.3 Noisemargindegradation... 20 1.4.4 Degradation of gate oxide reliability.... 20 1.5 Bookoutline... 20 2 Inductive Properties of Electric Circuits... 27 2.1 Definitions of inductance... 28 2.1.1 Field energy definition... 28 2.1.2 Magnetic flux definition... 30 2.1.3 Partial inductance... 35 2.1.4 Net inductance... 40 2.2 Variation of inductance with frequency..... 43 2.2.1 Uniform current density approximation.... 44 2.2.2 Inductance variation mechanisms.... 45 2.2.3 Simple circuit model... 49 2.3 Inductive behavior of circuits... 52 2.4 Inductive properties of on-chip interconnect... 54 2.5 Summary... 58 3 Properties of On-Chip Inductive Current Loops... 59 3.1 Introduction... 59

XII Contents 3.2 Dependence of inductance on line length... 60 3.3 Inductive coupling between two parallel loop segments 67 3.4 Application to circuit analysis... 68 3.5 Summary... 69 4 Electromigration... 71 4.1 Physical mechanism of electromigration.... 72 4.2 Electromigration-induced mechanical stress... 75 4.3 Steady state limit of electromigration damage.... 76 4.4 Dependence of electromigration lifetime on the line dimensions... 78 4.5 Statistical distribution of electromigration lifetime... 81 4.6 Electromigration lifetime under AC current.... 82 4.7 Electromigration in novel interconnect technologies.. 83 4.8 Designing for electromigration reliability... 85 4.9 Summary... 86 5 High Performance Power Distribution Systems... 87 5.1 Physical structure of a power distribution system... 88 5.2 Circuit model of a power distribution system... 89 5.3 Output impedance of a power distribution system... 92 5.4 A power distribution system with a decoupling capacitor... 95 5.4.1 Impedance characteristics.... 95 5.4.2 Limitations of a single-tier decoupling scheme. 99 5.5 Hierarchical placement of decoupling capacitance... 101 5.6 Resonance in power distribution networks... 108 5.7 Fullimpedancecompensation... 114 5.8 Case study... 116 5.9 Designconsiderations... 119 5.9.1 Inductance of the decoupling capacitors... 119 5.9.2 Interconnect inductance... 120 5.10 Limitations of the one-dimensional circuit model... 121 5.11 Summary... 124 6 Decoupling Capacitance... 125 6.1 Introductiontodecouplingcapacitance... 126 6.1.1 Historical retrospective... 126 6.1.2 Decoupling capacitor as a reservoir of charge.. 127 6.1.3 Practicalmodelofadecouplingcapacitor... 129

Contents XIII 6.2 Impedance of power distribution system with decouplingcapacitors... 133 6.2.1 Target impedance of a power distribution system... 133 6.2.2 Antiresonance... 136 6.2.3 Hydraulic analogy of hierarchical placement of decouplingcapacitors... 140 6.3 Intrinsic vs intentional on-chip decoupling capacitance 145 6.3.1 Intrinsicdecouplingcapacitance... 146 6.3.2 Intentionaldecouplingcapacitance... 150 6.4 Typesofon-chipdecouplingcapacitors... 152 6.4.1 Polysilicon-insulator-polysilicon (PIP) capacitors... 153 6.4.2 MOScapacitors... 155 6.4.3 Metal-insulator-metal(MIM)capacitors... 163 6.4.4 Lateralfluxcapacitors... 165 6.4.5 Comparison of on-chip decoupling capacitors.. 169 6.5 On-chipswitchingvoltageregulator... 171 6.6 Summary... 173 7 On-Chip Power Distribution Networks... 175 7.1 Styles of on-chip power distribution networks... 176 7.1.1 Basic structure of on-chip power distribution networks... 176 7.1.2 Improving the impedance characteristics of on-chip power distribution networks.... 181 7.1.3 Evolution of power distribution networks in Alpha microprocessors... 182 7.2 Die-packageinterface... 184 7.3 Otherconsiderations... 189 7.4 Summary... 191 8 Computer-Aided Design and Analysis... 193 8.1 Design flow for on-chip power distribution networks. 194 8.2 Linear analysis of power distribution networks... 199 8.3 Modeling power distribution networks..... 201 8.4 Characterizing the power current requirements of on-chip circuits..... 207 8.5 Numerical methods for analyzing power distribution networks... 210

XIV Contents 8.6 Allocationofon-chipdecouplingcapacitors... 217 8.6.1 Charge-basedallocationmethodology... 218 8.6.2 Allocation strategy based on the excessive noise amplitude...... 220 8.6.3 Allocation strategy based on excessive charge. 221 8.7 Summary... 223 9 Inductive Properties of On-Chip Power Distribution Grids... 225 9.1 Power transmission circuit... 225 9.2 Simulationsetup... 228 9.3 Gridtypes... 228 9.4 Inductance versus line width.... 233 9.5 Dependence of inductance on grid type.... 234 9.5.1 Non-interdigitated versus interdigitated grids.. 234 9.5.2 Paired versus interdigitated grids.... 235 9.6 Dependence of Inductance on grid dimensions.... 236 9.6.1 Dependence of inductance on grid width.... 236 9.6.2 Dependence of inductance on grid length... 238 9.6.3 Sheet inductance of power grids..... 238 9.6.4 Efficient computation of grid inductance.... 239 9.7 Summary... 241 10 Variation of Grid Inductance with Frequency... 243 10.1Analysisapproach... 243 10.2 Discussion of inductance variation... 245 10.2.1 Circuit models... 245 10.2.2 Analysis of inductance variation..... 248 10.3 Summary... 250 11 Inductance/Area/Resistance Tradeoffs... 253 11.1 Inductance vs. resistance tradeoff under a constant grid areaconstraint... 253 11.2 Inductance vs. area tradeoff under a constant grid resistanceconstraint... 258 11.3 Summary... 260 12 Scaling Trends of On-Chip Power Distribution Noise... 263 12.1Priorwork... 264

Contents XV 12.2 Interconnect characteristics... 266 12.2.1 Global interconnect characteristics... 268 12.2.2 Scaling of the grid inductance... 268 12.2.3 Flip-chip packaging characteristics... 269 12.2.4Impactofon-chipcapacitance... 271 12.3 Model of power supply noise... 272 12.4 Power supply noise scaling... 274 12.4.1 Analysis of constant metal thickness scenario.. 274 12.4.2 Analysis of the scaled metal thickness scenario 275 12.4.3ITRSscalingofpowernoise... 277 12.5 Implications of noise scaling... 281 12.6 Summary... 282 13 Impedance Characteristics of Multi-Layer Grids.. 285 13.1 Electrical properties of multi-layer grids... 287 13.1.1 Impedance characteristics of individual grid layers... 287 13.1.2 Impedance characteristics of multi-layer grids. 290 13.2 Case study of a two layer grid... 292 13.2.1Simulationsetup... 293 13.2.2 Inductive coupling between grid layers... 293 13.2.3 Inductive characteristics of a two layer grid... 297 13.2.4 Resistive characteristics of a two layer grid... 298 13.2.5 Variation of impedance with frequency in a two layergrid... 300 13.3 Design implications... 301 13.4 Summary... 302 14 Multiple On-Chip Power Supply Systems... 305 14.1 ICs with multiple power supply voltages... 306 14.1.1 Multiple power supply voltage techniques... 307 14.1.2 Clustered voltage scaling (CVS)..... 309 14.1.3 Extended clustered voltage scaling (ECVS)... 310 14.2 Challenges in ICs with multiple power supply voltages 311 14.2.1Diearea... 312 14.2.2Powerdissipation... 312 14.2.3 Design complexity... 313 14.2.4Placementandrouting... 313 14.3 Optimum number and magnitude of available power supply voltages... 316

XVI Contents 14.4 Summary... 321 15 On-Chip Power Distribution Grids with Multiple Supply Voltages... 323 15.1Background... 325 15.2Simulationsetup... 326 15.3 Power distribution grid with dual supply and dual ground... 328 15.4InterdigitatedgridswithDSDG... 331 15.4.1TypeIinterdigitatedgridswithDSDG... 331 15.4.2TypeIIinterdigitatedgridswithDSDG... 333 15.5 Paired grids with DSDG... 335 15.5.1 Type I paired grids with DSDG..... 336 15.5.2 Type II paired grids with DSDG..... 337 15.6Simulationresults... 340 15.6.1 Interdigitated power distribution grids without decouplingcapacitors... 341 15.6.2 Paired power distribution grids without decouplingcapacitors... 348 15.6.3 Power distribution grids with decoupling capacitors... 349 15.6.4 Dependence of power noise on the switching frequency of the current loads... 353 15.7 Design implications... 356 15.8 Summary... 358 16 Decoupling Capacitors for Multi-Voltage Power Distribution Systems... 361 16.1 Impedance of a power distribution system... 363 16.1.1 Impedance of a power distribution system... 364 16.1.2 Antiresonance of parallel capacitors... 367 16.1.3 Dependence of impedance on power distribution systemparameters... 368 16.2 Case study of the impedance of a power distribution system... 371 16.3 Voltage transfer function of power distribution system 376 16.3.1 Voltage transfer function of a power distribution system... 376 16.3.2 Dependence of voltage transfer function on power distribution system parameters...... 378

Contents XVII 16.4 Case study of the voltage response of a power distribution system.... 381 16.4.1 Overshoot-free magnitude of a voltage transfer function... 383 16.4.2 Tradeoff between the magnitude and frequency range... 385 16.5 Summary... 389 17 On-chip Power Noise Reduction Techniques in High Performance ICs... 391 17.1 Ground noise reduction through an additional low noise on-chipground... 393 17.2 Dependence of ground bounce reduction on system parameters... 395 17.2.1 Physical separation between noisy and noise sensitive circuits... 396 17.2.2 Frequency and capacitance variations... 397 17.2.3Impedanceofanadditionalgroundpath... 399 17.3 Summary... 400 18 Effective Radii of On-Chip Decoupling Capacitors 403 18.1Background... 405 18.2 Effective radius of on-chip decoupling capacitor based onatargetimpedance... 407 18.3 Estimation of required on-chip decoupling capacitance 409 18.3.1Dominantresistivenoise... 410 18.3.2 Dominant inductive noise... 411 18.3.3Criticallinelength... 414 18.4Effectiveradiusasdeterminedbychargetime... 416 18.5 Design methodology for placing on-chip decoupling capacitors... 422 18.6 Model of on-chip power distribution network.... 422 18.7 Case study... 425 18.8 Design implications... 431 18.9 Summary... 432 19 Efficient Placement of Distributed On-Chip Decoupling Capacitors... 435 19.1Technologyconstraints... 436 19.2 Placing on-chip decoupling capacitors in nanoscale ICs 437

XVIII Contents 19.3 Design of a distributed on-chip decoupling capacitor network... 440 19.4 Design tradeoffs in a distributed on-chip decoupling capacitornetwork... 445 19.4.1 Dependence of system parameters on R 1... 446 19.4.2 Minimum C 1... 447 19.4.3 Minimum total budgeted on-chip decoupling capacitance... 448 19.5 Design methodology for a system of distributed on-chip decouplingcapacitors... 450 19.6 Case study... 453 19.7 Summary... 457 20 Impedance/Noise Issues in On-Chip Power Distribution Networks... 459 20.1Scalingeffectsinchip-packageresonance... 460 20.2 Propagation of power distribution noise.... 463 20.3 Local inductive behavior... 465 20.4 Summary... 469 21 Conclusions... 471 Appendices A B C D Mutual Loop Inductance in Fully Interdigitated Power Distribution Grids with DSDG... 477 Mutual Loop Inductance in Pseudo-Interdigitated Power Distribution Grids with DSDG... 479 Mutual Loop Inductance in Fully Paired Power Distribution Grids with DSDG... 481 Mutual Loop Inductance in Pseudo-Paired Power Distribution Grids with DSDG... 483 References... 485 Index... 509

List of Figures 1.1 Microphotographs of the first integrated circuit (IC) and first monolithic IC along with a high performance, high complexity IC..... 2 1.2 Evolution of transistor count of microprocessors and memoryics... 4 1.3 Evolution of microprocessor clock frequency.... 5 1.4 Evolution of design criteria in CMOS integrated circuits.... 7 1.5 Microphotograph of the 4004.... 8 1.6 Evolution of microprocessor power consumption.... 10 1.7 Basic power delivery system.... 11 1.8 Evolution of the average current in high performance microprocessors....... 12 1.9 Increase in power current of microprocessors with technologyscaling.... 13 1.10 ScalingoftheCMOSnoisemargins.... 14 1.11 Projections of the target impedance of a power distribution system.... 15 1.12 A grid structured power distribution network..... 16 1.13 Cycle-to-cycle jitter of a clock signal...... 18 1.14 Peak-to-peakjitterofaclocksignal.... 19 2.1 Two complete current loops.... 31 2.2 A circuit with branch points.... 34 2.3 Two segmented current loops.... 36 2.4 A straight round wire.... 38

XX List of Figures 2.5 Self and mutual partial inductance of a straight segment of wire....... 39 2.6 Loop magnetic flux in terms of partial fluxes.... 41 2.7 The signal and return current paths....... 43 2.8 Internal magnetic flux of a round conductor.... 46 2.9 Proximityeffectintwocloselyspacedlines... 46 2.10 Current loop with two alternative current return paths... 48 2.11 A cross-sectional view of two parallel current paths sharing the same current return path...... 49 2.12 A circuit model of two current paths with different inductive properties.... 49 2.13 Impedance characteristics of two current paths with dissimilar impedance characteristics....... 50 2.14 A RL ladder circuit.... 51 2.15 A line length region where signal transmission exhibits inductive behavior.... 54 2.16 The line inductance design space with significant inductive behavior.... 55 2.17 A signal line in an integrated circuit environment... 57 3.1 Two representations of a straight line inductance... 61 3.2 A complete current loop formed by two straight parallel lines.... 62 3.3 Inductance per length versus line length.... 63 3.4 Inductance per length versus line length in terms of the per cent difference..... 64 3.5 A current loop formed by two parallel lines... 65 3.6 Two loop segments connected in parallel..... 67 4.1 Electromigration induced circuit faults.... 72 4.2 Electromigration in an interconnect line.... 73 4.3 Electromigration lifetime versus line width.... 79 4.4 Grain structure of interconnect lines....... 80 4.5 Log-normal distribution of electromigration failures. 81 4.6 A train of current pulses.... 82 4.7 Via void formation in dual-damascene interconnect.. 84 5.1 A cross-sectional view of a power distribution system. 88

List of Figures XXI 5.2 A one-dimensional circuit model of the power supply system.... 90 5.3 A reduced circuit model of a power supply system.. 91 5.4 An output impedance model of a power distribution system.... 93 5.5 A power distribution system without decoupling capacitors... 93 5.6 Impedance of the power distribution system with no decouplingcapacitors... 95 5.7 A power distribution network with a decoupling capacitor.... 96 5.8 Impedance of the power distribution system with a decouplingcapacitor.... 97 5.9 The path of current flow in a power distribution systemwithadecouplingcapacitor.... 98 5.10 A circuit model of a power distribution system with a boarddecouplingcapacitance... 102 5.11 Impedance of a power distribution system with a boarddecouplingcapacitance... 103 5.12 A circuit model of a power distribution system with boardandpackagedecouplingcapacitances.... 103 5.13 Impedance of the power distribution system with boardandpackagedecouplingcapacitances.... 104 5.14 A model of output impedance of a power distribution system with board, package, and on-chip decoupling capacitances.... 105 5.15 Impedance of a power distribution system with board, package,andon-chipdecouplingcapacitances.... 106 5.16 Variation of the power current loop with frequency.. 107 5.17 A parallel resonant circuit.... 109 5.18 Asymptotic impedance characteristics of a tank circuit..... 110 5.19 Design space of resistance in a tank circuit.... 112 5.20 Decoupling capacitance requirements...... 113 5.21 Impedance characteristics of a fully compensated tank circuit..... 115 5.22 Impedance of a fully compensated power distribution system.... 116 5.23 Case study impedance characteristics...... 118 5.24 Placement of area array connections for low inductance.... 122

XXII List of Figures 6.1 Leyden jar originally developed by Ewald Georg von Kleist in 1745 and independently invented by Pieter van Musschenbroek in 1746.... 128 6.2 Capacitance of two metal lines placed over a substrate.... 129 6.3 Hydraulic model of a decoupling capacitor as a reservoirofcharge.... 130 6.4 Practicalmodelofadecouplingcapacitor... 131 6.5 Physical structure of an on-chip MOS decoupling capacitor.... 132 6.6 A circuit network representing the impedance of a power distribution system with decoupling capacitors as seen from the terminals of the current load.... 134 6.7 A circuit network representing the impedance of a power distribution system without decoupling capacitors... 135 6.8 Impedance of a power distribution system without decouplingcapacitors... 135 6.9 Antiresonance of the output impedance of a power distribution network.... 137 6.10 Impedance of a power distribution system with n identical decoupling capacitors connected in parallel. 138 6.11 Antiresonance of parallel capacitors, C 1 >C 2, L 1 = L 2,andR 1 = R 2... 139 6.12 Antiresonance of parallel capacitors....... 141 6.13 Hydraulic analogy of the hierarchical placement of decouplingcapacitors... 143 6.14 Impedance of a power distribution system with board, package,andon-chipdecouplingcapacitances.... 144 6.15 Intrinsic decoupling capacitance of the interconnect lines.... 146 6.16 Intrinsic decoupling capacitance of a non-switching circuit..... 148 6.17 N-well junction intrinsic decoupling capacitance.... 149 6.18 Banksofon-chipdecouplingcapacitors.... 150 6.19 ThinoxideMOSdecouplingcapacitor.... 151 6.20 Equivalent RC model of a MOS decoupling capacitor. 152 6.21 Layout (a) and cross section (b) of a PIP oxide-nitride-oxide(ono)capacitor... 154 6.22 Thestructureofann-typeMOScapacitor.... 156

List of Figures XXIII 6.23 Capacitance versus gate voltage (CV) diagram of an n-typemoscapacitor... 157 6.24 Charge distribution in an NMOS capacitor operating in accumulation (V gb <V fb )... 157 6.25 Accumulation charge density as a function of the applied gate voltage.... 158 6.26 Charge distribution in an NMOS capacitor operating in depletion (V fb <V gb <V t ).... 159 6.27 Charge distribution of an NMOS capacitor operating in inversion (V t <V gb )... 160 6.28 Layout (a) and cross section (b) of a deep-n + MOS capacitorconstructedinabicmosprocess.... 162 6.29 CrosssectionofaMIMcapacitor.... 163 6.30 A simplified structure of an interdigitated lateral flux capacitor (top view).... 166 6.31 Verticalfluxversuslateralflux.... 166 6.32 Reduction of the bottom plate parasitic capacitance throughfluxstealing.... 167 6.33 Wovencapacitor... 169 6.34 Switchingdecouplingcapacitors.... 173 7.1 Routed power and ground distribution networks.... 177 7.2 A mesh structured power distribution network..... 178 7.3 A multi-layer power distribution grid...... 179 7.4 On-chippowerandgroundplanes... 180 7.5 A power distribution network structured as a cascaded ring... 181 7.6 Narrowpowerlinesversuswidepowerlines.... 182 7.7 Global power distribution network in Alpha 21064 microprocessor....... 183 7.8 Closelyattachedcapacitor.... 186 7.9 Flow of power current in an IC with peripheral I/O. 187 7.10 Flow of power current in an IC with flip-chip I/O... 188 7.11 Flip-chippingridarraypackage.... 189 7.12 Interaction of the substrate and power distribution network.... 191 8.1 Design flow for on-chip power distribution networks. 195 8.2 An RLC model of an on-chip power distribution network.... 198

XXIV List of Figures 8.3 Substitution of a nonlinear load with a time-dependent current source.... 200 8.4 Characterization of the intrinsic decoupling capacitance.... 205 8.5 Exploiting the symmetry of the power and ground distribution networks to reduce the model complexity. 208 8.6 Separation of the analysis of the RLC and RC-only parts of a power distribution system....... 212 8.7 A hierarchical model of a power distribution network. 214 8.8 Flow chart for allocating on-chip decoupling capacitors... 218 8.9 Variation of ground supply voltage with time.... 222 9.1 A simple power transmission circuit....... 226 9.2 Two parallel coupled inductors.... 227 9.3 Three types of power distribution grids.... 229 9.4 Loop grid inductance versus number of lines..... 231 9.5 Inductance of grids with 1 µm 1 µm cross section lines.... 231 9.6 Inductance of grids with 1 µm 3 µm cross section lines.... 233 9.7 Grid inductance versus grid length.... 238 10.1 Threetypesofgridstructures.... 244 10.2 A cross-sectional view of two parallel current paths sharing the same current return path...... 246 10.3 A circuit model of two current paths with different inductive properties.... 246 10.4 Impedance characteristics of two paths with dissimilar impedance characteristics.... 247 10.5 Inductance of non-interdigitated grids versus frequency.... 249 10.6 Loop inductance of paired grids versus frequency.... 250 10.7 Loop inductance of interdigitated grids versus frequency.... 251 11.1 Inductance versus resistance tradeoff scenario.... 254 11.2 Grid inductance versus line width under a constant gridareaconstraint.... 255 11.3 The sheet inductance L A versus line width under a constantgridareaconstraint.... 256

List of Figures XXV 11.4 Normalized sheet inductance and sheet resistance under a constant grid area constraint...... 257 11.5 Inductance versus area tradeoff scenario.... 258 11.6 The grid inductance versus line width under a constant gridresistanceconstraint.... 259 11.7 The sheet inductance L R versus line width under a constantgridresistanceconstraint.... 259 11.8 Normalized sheet inductance L R and grid area ratio A R under a constant grid resistance constraint..... 260 12.1 An area array of on-chip power/ground I/O pads... 270 12.2 Decrease in flip-chip pad pitch with technology scaling.... 271 12.3 A simplified circuit model of the on-chip power distribution network.... 272 12.4 A model of the power distribution cell..... 273 12.5 Scaling of a power distribution grid according to the constantmetalthicknessscenario.... 275 12.6 Scaling of a power distribution grid according to the scaledmetalthicknessscenario.... 276 12.7 Increase in power current demands of microprocessors withtechnologyscaling... 278 12.8 A power distribution grid model.... 278 12.9 Scaling trends of resistive and inductive power supply noise under the constant metal thickness scenario... 280 12.10 Scaling trends of resistive and inductive power supply noise under the scaled metal thickness scenario.... 280 13.1 A multi-layer power distribution grid...... 286 13.2 Two stacks of layers comprising a multi-layer grid... 287 13.3 Impedance of the individual grid layers in a multi-layer grid... 289 13.4 Equivalent circuit of a stack of N gridlayers.... 290 13.5 Variation of the inductance and resistance of a multi-layer stack with frequency.... 291 13.6 General view of a two layer grid.... 293 13.7 An equivalent circuit diagram of a two layer grid.... 294 13.8 Alignment of two parallel grid layers with the same linepitch.... 295 13.9 Inductance of a two layer grid versus the physical offset between the two layers.... 296

XXVI List of Figures 13.10 Thecrosssectionofatwolayergrid... 296 13.11 Inductance of a two layer grid versus signal frequency. 297 13.12 Resistance of a two layer grid versus signal frequency. 299 13.13 Impedance magnitude of a two layer grid versus frequency.... 300 14.1 An example single supply voltage circuit..... 307 14.2 An example dual supply voltage circuit.... 308 14.3 Static current as a result of a direct connection between the Vdd L gate and the V H dd gate.... 309 14.4 Level converter circuit..... 309 14.5 A dual power supply voltage circuit with the clustered voltagescaling(cvs)technique.... 310 14.6 A dual power supply voltage circuit with the extended clustered voltage scaling (ECVS) technique.... 311 14.7 Layout of an area-by-area architecture with a dual power supply voltage.... 315 14.8 Layout of a row-by-row architecture with a dual power supply voltage........ 316 14.9 In-row dual power supply voltage scheme.... 317 14.10 Trend in power reduction with multi-voltage scheme as a function of the number of available supply voltages. 318 14.11 A lambda-shaped normalized path delay distribution function.... 320 14.12 Dependence of the total power of a dual power supply system on a lower power supply voltage Vdd L... 321 15.1 A multi-layer on-chip power distribution grid.... 325 15.2 Interdigitated power distribution grids under investigation.... 327 15.3 Circuit diagram of the mutual inductive coupling of the DSDG power distribution grid.... 329 15.4 Physical structure of an interdigitated power distribution grid with DSDG.... 330 15.5 Physical structure of a fully interdigitated power distribution grid with DSDG.... 332 15.6 Physical structure of a pseudo-interdigitated power distribution grid with DSDG.... 333

List of Figures XXVII 15.7 Total mutual inductance of interdigitated power distribution grids with DSDG as a function of line separation.... 335 15.8 Physical structure of a fully paired power distribution gridwithdsdg... 336 15.9 Physical structure of a pseudo-paired power distribution grid with DSDG.... 338 15.10 Total mutual inductance of paired power distribution grids with DSDG as a function of the ratio of the distance between the pairs to the line separation inside each pair (n)... 340 15.11 Maximum voltage drop for the four interdigitated power distribution grids under investigation.... 347 15.12 Maximum voltage drop for the three paired power distribution grids under investigation...... 349 15.13 Maximum voltage drop for interdigitated and paired power distribution grids under investigation.... 350 15.14 Maximum voltage drop for seven types of power distribution grids with a decoupling capacitance.... 351 15.15 Maximum voltage drop for the power distribution grid with SSSG as a function of frequency and line width for different values of decoupling capacitance.... 355 16.1 Impedance of power distribution system with two supply voltages seen from the load of the power supply V dd1... 364 16.2 Impedance of power distribution system with two supply voltages and the decoupling capacitors represented as series RLC networks.... 365 16.3 Frequency dependence of the impedance of a power distribution system with dual supply voltages, R 1 = R 12 = R 2 =10mΩ,C 1 = C 12 = C 2 = 1 nf, and L 1 = L 12 = L 2 =1nH... 366 16.4 Antiresonance of the two capacitors connected in parallel, C 2 = C 1.... 368 16.5 Antiresonance of a power distribution system with dual power supply voltages, R 1 = R 12 = R 2 =10mΩ, C 1 = C 2 = 1 nf, and L 1 = L 12 = L 2 =1nH.... 369 16.6 Impedance of the power distribution system as a function of frequency.... 370

XXVIII List of Figures 16.7 Dependence of a dual V dd power distribution system impedance on frequency for different ESL of the decouplingcapacitors... 372 16.8 The impedance of a power distribution system with dual power supply voltages as a function of frequency, R 1 = R 12 = R 2 = 100 mω, C 1 = C 2 =10nF, C 12 = 1 nf, and L 1 = L 12 = L 2 =1nH.... 373 16.9 Hierarchical model of a power distribution system with dual supply voltages and a single ground.... 375 16.10 Voltage transfer function of a power distribution network with two supply voltages and the decoupling capacitors represented as series RLC networks... 377 16.11 Dependence of the magnitude of the voltage transfer function on frequency of a dual V dd power distribution system for different values of ESR of the decoupling capacitors, R 12 =10mΩ,C 12 = C 2 = 1 nf, and L 12 = L 2 =1nH... 379 16.12 Frequency dependence of the voltage transfer function of a dual V dd power distribution system for different values of ESL of the decoupling capacitors, R 12 = R 2 = 100 mω, C 12 = C 2 = 100 nf, and L 12 =10pH... 380 16.13 Frequency dependence of the voltage transfer function of a dual V dd power distribution system..... 382 16.14 Dependence of the magnitude of the voltage transfer function of a dual V dd power distribution system on frequency for different values of the ESR and ESL of the decoupling capacitors, R 12 = R 2 =0.1Ω, C 12 =20nF,C 2 =40nF,andL 12 = L 2 =1nH.... 384 16.15 Magnitude of the voltage transfer function of an example dual V dd power distribution system as a function of frequency.... 386 17.1 An equivalent circuit for analyzing ground bounce in ansoc.... 394 17.2 Groundbouncereductiontechnique... 395 17.3 Simplified circuit of the ground bounce reduction technique.... 396 17.4 Ground bounce reduction as a function of noise frequency.... 398

List of Figures XXIX 17.5 Reduction in ground bounce as a function of capacitancevariations.... 399 18.1 Placement of an on-chip decoupling capacitor based onthemaximumeffectivedistance... 404 18.2 Projection of the maximum effective radius as determined by the target impedance d max Z for future technology generations: I max = 10 ma, V dd = 1 V, and Ripple =0.1.... 409 18.3 Linear approximation of the current demand of a power distribution network by a current source.... 410 18.4 Power distribution noise during discharge of an on-chip decoupling capacitor: I max = 100 ma, V dd =1V, t r =20ps,t f =80ps,R = 100 mω, L = 15 ph, and C dec =50pF.... 412 18.5 Critical line length of an interconnect between a decoupling capacitor and a current load.... 415 18.6 Dependence of the critical line length d crit on the rise time of the current load: I max =0.1A, V dd =1V, r =0.007 Ω/µm, and l =0.5pH/µm... 416 18.7 Design space for determining minimum required on-chip decoupling capacitance: I max = 50 ma, V dd =1V,r =0.007 Ω/µm, l =0.5pH/µm, t r = 100 ps, and t f =300ps.... 417 18.8 Circuit charging an on-chip decoupling capacitor.... 418 18.9 Design space for determining the maximum tolerable parasitic resistance and inductance of a power distribution grid: I max = 100 ma, t r = 100 ps, t f = 300 ps, C dec = 100 pf, V dd =1volt,and t ch =400ps.... 421 18.10 Design flow for placing on-chip decoupling capacitors basedonthemaximumeffectiveradii.... 423 18.11 The effective radii of an on-chip decoupling capacitor. 424 18.12 Model of a power distribution network..... 426 18.13 Effective radii of an on-chip decoupling capacitor in a power distribution system modeled as a distributed RL mesh.... 427 18.14 A schematic example allocation of on-chip decoupling capacitorsacrossanic.... 432

XXX List of Figures 19.1 Fundamental limits of on-chip interconnections.... 437 19.2 Placement of on-chip decoupling capacitors using a conventionalapproach... 438 19.3 Aconventionalon-chipdecouplingcapacitor... 439 19.4 A network of distributed on-chip decoupling capacitors... 440 19.5 A physical model of a system of distributed on-chip decouplingcapacitors... 441 19.6 A circuit model of an on-chip distributed decoupling capacitornetwork... 441 19.7 Voltage across C 1 during discharge as a function of C 1 and R 2 : I max =0.01 ma, V dd =1volt,and t r =100ps... 444 19.8 The total budgeted on-chip decoupling capacitance as a function of the parasitic resistance of the metal lines, R 1 and R 2 : I max = 10 ma, V dd =1volt, V load =0.9 volt, and t r =100ps... 449 19.9 The total budgeted on-chip decoupling capacitance as a function of the parasitic resistance of the metal lines, R 1 and R 2 : I max = 10 ma, V dd =1volt, V load =0.9 volt, and t r =100ps... 451 19.10 Design flow for determining the parameters of a system of distributed on-chip decoupling capacitors. 452 20.1 Evolution of the impedance of a power distribution system in microprocessors..... 461 20.2 Cross section of interconnect connecting the load and decouplingcapacitance.... 467 20.3 The effect of circuit scaling on the on-chip capacitance allocation... 468

List of Tables 5.1 Parameters of a case study power distribution system 117 6.1 Four common types of on-chip decoupling capacitors in a90nmcmostechnology... 170 9.1 Inductive characteristics of power/ground grids... 232 12.1 Ideal scaling of CMOS circuits... 264 12.2 Scaling analyses of power distribution noise... 267 15.1 Impedance characteristics of power distribution grids with SSSG... 342 15.2 Impedance characteristics of interdigitated power distribution grids with DSSG... 343 15.3 Impedance characteristics of interdigitated power distribution grids with DSDG... 344 15.4 Impedance characteristics of Type I paired power distribution grids with DSDG... 345 15.5 Impedance characteristics of Type II paired power distribution grids with DSDG... 346 16.1 Case study of the impedance of a power distribution system... 374 16.2 Tradeoff between the magnitude and frequency range ofthevoltageresponse... 387 17.1 Ground bounce reduction as a function of the separation between the noisy and noise sensitive circuits... 397

XXXII List of Tables 17.2 Ground bounce reduction for different values of parasitic resistance of the on-chip low noise ground.. 400 18.1 Maximum effective radii of an on-chip decoupling capacitor for a single line connecting a decoupling capacitor to a current load... 428 18.2 Maximum effective radii of an on-chip decoupling capacitor for an on-chip power distribution grid modeled as a distributed RL mesh... 429 19.1 Dependence of the parameters of a distributed on-chip decoupling capacitor network on R 1... 446 19.2 Distributed on-chip decoupling capacitor network as a function of R 1 under the constraint of a minimum C 1 447 19.3 The magnitude of the on-chip decoupling capacitors as a function of the parasitic resistance of the power/ground lines connecting the capacitors to the current load... 455 19.4 The magnitude of the on-chip decoupling capacitors as a function of the parasitic resistance of the power/ground lines connecting the capacitors to the current load for a limit on C 1... 456