Evolutionary Robotics: From Intelligent Robots to Articial Life (ER'97), T.Gomi (Ed.), pp101{125. AAI Books, 1997. Articial Evolution in the Physical World ADRIAN THOMPSON CCNR, COGS University of Sussex Brighton BN1 9QH, UK Tel: +44 1273 678754, Fax: +44 1273 671320 Email: adrianth@cogs.susx.ac.uk 1 Introduction When articial evolution is used to automatically design a structure, that structure usually exists in a software simulation, to make it easily manipulable. When evolving control systems for autonomous mobile robots [1], even when the real robot is used instead of a simulation, the actual structure undergoing evolution often an articial neural network (ANN) is usually simulated in software. Recently, however, technology has become available which allows articial evolution to manipulate the conguration of a silicon chip directly: electronic circuits can be evolved without the use of simulation, with every tness measurement being the evaluation of a physically real electronic circuit's performance at the desired task. But why should one be interested in this? After all, we can easily simulate ANNs on a standard desktop PC that are larger than the current capabilities of articial evolution, so we do not need to resort to hardware implementations because of software being too slow (pace de Garis [2]). The answer is that evolution of recongurable hardware need not be just a high speed implementation of what could easily be done in software: evolution is crafting a physical object that exists in real time and
space, and behaves according to semiconductor physics. This raises a set of opportunities for science and engineering that are not normally addressed by simulation work: 1. Evolution can exploit real-world physics that is dicult to analyse or model in simulation or theoretical studies. Once the simplifying constraints of conventional design methodologies have been dropped, this can allow highly ecient circuits to be evolved, which exploit the natural behaviour of the electronic medium. 2. The physical components have a size, shape and location, and these are crucial in determining the interactions between them. This can make the interactions richer, but in some ways more constrained, than the perfectly controllable point-to-point topological interconnections normally used when evolving in simulation. 3. The characteristics of the components and their interactions are not exactly predictable or constant over time. Evolution must nd ways of coping with this. The rst point above provides the engineering motivation: extremely ef- cient (small, low-power) circuits can be produced. The penalty for the engineer is that to do this, the second two points must also be considered. For the scientist, all three are of great interest, as they apply as much to evolution in nature and attempts to draw inspiration from it as to electronics. As we shall see, they have implications for the organisation of a physical `nervous system', whether it be natural or articial. This paper summarises some results from the author's work on the evolutionary engineering of electronics in general, with the intention of showing its relevance to the Evolutionary Robotics (ER) enterprise. In the next section, I describe the technology making the direct evolution of electronics possible. The later sections then consider the three points above in turn, showing experimental results. Only an overview is given see the references for full details. Finally, the implications for ER are summarised.
2 Technology: Evolvable Hardware A Field-Programmable Gate Array (FPGA) is a Very Large Scale Integration (VLSI) silicon chip containing a large array of components and wires. Switches distributed throughout the chip determine how each component behaves, and how they connect to the wires. By conguring these switches, an FPGA's behaviour is determined by the user `in the Field' rather than at the chip factory. In RAM-based FPGAs, the switches are electronic, and have their settings determined by bits of memory onboard the chip. The Xilinx XC6200 [21] is the rst such device ideally suited to evolutionary work [19], and a simplied view of it is given in Figure 1. It can be interfaced to a host computer so that its conguration memory can be written to by software just like normal computer memory. An Evolutionary Algorithm (EA) running on the computer can write to the FPGA's conguration memory, setting the electronic switches, and thus creating a physically real electronic circuit. This circuit can be evaluated according to its real-world performance at a task, and successively modied by the EA of choice (eg. a genetic algorithm (GA) [7, 4, 5], evolutionary programming [3], evolution strategies [13] or genetic programming [8, 9]) until satisfactory performance is achieved. Figure 2 depicts the operation of a simple GA applied in this way. Note that in this evolutionary process of automatic circuit design, there is no simulation, modelling, or analysis of the circuit. The FPGA is not programmed to follow a sequence of instructions, it is congured and then allowed to behave in real-time according to semiconductor physics: evolution is manipulating a physical medium. The electronic equipment needed is not necessarily bulky or complicated. Figure 3 shows the tiny `Khepera' robot (a common tool in ER [11]) equipped with an XC6216 FPGA onboard. With the FPGA controlling the real robot, behaving in the real world, a simple wall-avoiding behaviour has been evolved. Evolution was by a GA running on a PC connected to the robot by a serial cable, but there was no simulation of the robot or the control circuits. This simple demonstration shows that evolution of FPGA circuits is not necessarily any more complicated or dicult than evolving a software structure such as a simulated ANN.
S N S W F N S E W N E W F W N S E W N S E W E S E W F F N S E F N Figure 1: A simplied view of the XC6216 FPGA. Only those features used later in the experiments are shown. Top: A 10 10 corner of the 64 64 array of blocks; Below: the internals of an individual cell, showing the function unit at its centre. The symbol represents a multiplexer which of its four inputs is connected to the output (via an inversion) is controlled by the conguration memory. Similar multiplexers are used to implement the user-congurable function F.
Figure 2: Evolving an FPGA conguration using a simple genetic algorithm. A population of Population (initially random) bit-string genotypes is 0 1 0 maintained, each individual coding for a possible FPGA configuration. 0 0 Fitness Evaluation: Each individual is taken in turn and used to configure a real FPGA, which is then scored at how well it performs the desired task. 1 1 0 0 1 1 1 0 1 0 0 0 1 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1 0 1 1 REPEAT UNTIL SATISFACTORY 0 0 0 0 1 1 1 Fitness Scores 4.851 9.001 0.000 3.942 0.030 1 0 1 0 0 Next Generation 0 1 0 1 0 0 1 1 0 1 0 0 0 1 1 1 A new population is formed, made of the offspring of the fitter (on average) members of the old one. 0 0 0 0 1 1 1 Higher scoring individuals are more likely to parent offspring (selection). Offspring are formed by stochastically combining segmen from each parent (crossover), and by randomly inverting a few bits (mutation).
Figure 3: The miniature Khepera robot. The top two layers are an FPGA extension turret allowing onboard evolution of electronic control systems. They were designed by the author, and constructed in collaboration with the Xilinx Development Corp.
3 Evolutionary Exploitation of a Physical Medium The process of direct hardware evolution just described works by taking account of changes in the real-world performance of a circuit as variations are made to its structure. This is very dierent from the design methods followed by humans: these always take place at a more abstract level, so that the designer does not have to consider the detailed behaviour of every component and their interactions. Figure 4 gives a sketch of this crucial dierence between conventional design and evolution. Design, analysis, or simulation of any but the smallest circuits is infeasible unless some of the details of the semiconductor physics are `abstracted away' to form a simpler model. If such designs, analyses, or simulations are to say something useful about the behaviour of the real hardware, the circuits under consideration must be constrained: the details that have been suppressed in forming the abstract model must not be allowed to inuence the overall behaviour of the system at the level of description of interest. This means that circuits that can be designed (by humans), analysed, or simulated, can not put to use all of the natural behaviour of the silicon medium: some of it must be discarded for the sake of simplicity of modelling. The standard ways of doing this are embedded into all design methodologies the way the system is broken down (perhaps hierarchically) into parts, and the interactions between these parts restricted so that their collective behaviour can be readily understood from a knowledge of their individual properties. Evolution needs none of this (at least, not for the same reasons). There is no analysis, simulation, or modelling, so no constraints need to be placed on the circuits to facilitate these. Evolution proceeds by taking account of the changes in the overall behaviour as variations (usually small) are made to the circuit's structure: this means that the collective behaviour of the components can be freely exploited without having to be able to predict it from a knowledge of their individual properties. Evolution can be set free to exploit the rich structures and dynamical behaviours that are natural to the silicon medium, exploring beyond the scope of conventional design. The detailed properties of the components and their interactions can be used in composing this system-level behaviour. It takes considerable imagination to envisage what these evolved circuits could be like: the kinds of systems we
? a b = a + b a a = 0 Design by humans: Design through evolution: takes place at an abstract level. proceeds by taking account of the overall behavioural effect of variations made to the structure. Figure 4: A caricature comparison of the dierence between design by conventional methods, and through articial evolution.
are familiar with (eg. digital, discrete-time, computational, or hierarchically decomposed circuits) are but a subset of what is possible. (See [20] for the full details of this argument.) As an example of an application of these ideas in the eld of ER, consider the robot shown in Figure 5. This two-wheeled autonomous mobile robot has a diameter of 46cm, a height of 63cm, and was required to display simple wall-avoiding/room-centering behaviour in an empty 2.9m4.2m rectangular arena. For this scenario, the d.c. motors were not allowed to run in reverse and the robot's only sensors were a pair of time-of-ight sonars rigidly mounted on the robot, one pointing left and the other right. The sonars re simultaneously ve times a second; when a sonar res, its output changes from logic 0 to logic 1 and stays there until the rst echo is sensed at its transducer, at which time its output returns to 0. This experiment was the rst work designed to explore the possibilities of directly evolving real hardware [14], and at that time suitable FPGAs were not available. For this reason, an evolvable hardware architecture dubbed the `Dynamic State Machine' (DSM) was developed, to be built out of several readily available chips assembled onto a circuit-board. It is based upon a standard electronic implementation of a nite-state machine (a common simple computational architecture) using a RAM memory chip to hold a look-up table dening the machine's behaviour. The contents of this RAM chip were placed under evolutionary control. Conventionally, the dynamics of the system would be given by a `clock' which causes the machine to change from one state to the next at regular intervals (`clock ticks'), in a way easily described by Boolean (binary) logic. This is an example of a constraint introduced on the circuit's dynamics in order to allow it to be modelled in an abstract framework (in this case, Boolean logic). Thus, for the evolutionary experiment, the clocking constraint was removed. It was placed under evolutionary control whether each signal in the circuit was allowed to run freely in continuous time, or whether it would be synchronised to the clock in the usual way. For the clocked signals, the clock frequency itself was placed under evolutionary control. The clock, which used to be a constraint on the system's dynamics forcing it to behave synchronously in discrete time has been turned into a resource which can be used to further enrich the continuous-time dynamics of the circuit.
Virtual World Simulator Sonar Emulator Evolvable Hardware Sonars Wheels Rotation Sensors Figure 5: The robot known as \Mr Chips."
Figure 6 represents the resulting evolvable DSM circuit as a mixed synchronous/asynchronous recurrent logic network, where the two logic functions are implemented by the RAM chip, and are thus under evolutionary control. The `genetic latches' in the gure allow evolution to determine independently whether each signal is synchronised to the clock of evolved frequency, or whether it is free-running in continuous time. Relaxing the dynamical constraints on the circuit has so enriched its capabilities that the sonar echo signals are directly connected to its inputs, and its outputs directly drive the power stages for the motors: normally, pre- and post-processing of the sensorimotor signals would be required. This control system was evolved as a piece of real hardware, with the physical circuit controlling the real motors for all tness evaluations. For convenience, during evolution the sonar input waveforms were emulated in real-time on the basis of a `Virtual Reality' simulation of the robot's sensory environment, based on velocity measurements taken from the wheels (which were just spinning in the air). Figure 7 shows the behaviour induced in the robot by the nal evolved hardware controller: the long-exposure photograph shows the excellent performance in the real world when the real sonars were connected and the robot placed in the arena. Remarkably, the nal evolved control system goes directly from sonar echo signals to pulses sent to the motors, using only 32 bits of RAM and three ip-ops (excluding clock generation). This is a truly miniscule amount of electronics to comprise the entire sensorimotor control structure for this robust behaviour, which is able to cope with the highly misleading multiple reections which are often picked-up by the sonars. Analysis showed that the circuit had very rich dynamics, exploiting a stochastic interplay between continuous-time and discrete-time signals. It is not a nite-state machine, and could not have been designed by conventional methods because the detailed analogue continuous-time properties of the hardware (such as timedelays and metastability constants) are important to its operation: it cannot be modelled by Boolean logic. Control experiments showed that the standard synchronous nite-state machine could not perform this task, so we can conclude that evolution really has been able to explore a richer repertoire of behaviours arising from the same circuitry once the simplifying constraints necessary for designers have been removed. See [14] and [20] for full details.
MOTORS LEFT M RIGHT M LOGIC FUNCTION LOGIC FUNCTION LEFT RIGHT SONARS Figure 6: A representation of the evolvable Dynamic State Machine, as used in the experiment. Each is a `Genetic Latch' (see text).
Figure 7: Room-centering in virtual reality and (bottom right) in the real world, after 35 generations. The top pictures are of 90 seconds of behaviour, the bottom ones of 60.
4 Components Interacting in Physical Space For our next example, consider evolving the 10 10 array of FPGA cells shown in Figure 1. Again, the task is to be a simple but non-trivial one, formulated to explore fundamental issues. The circuit is to have a single input, and a single output. The input will be a square-wave audio-tone of either 1kHz or 10kHz, and circuit is to discriminate between them. Ideally, the output should go to a steady +5V as soon as one of the frequencies is present, and 0V for the other one. The task was intended as a rst step into the domains of pattern recognition and signal processing, rather than being an application in itself. One could imagine, however, such a circuit being used to demodulate frequency-modulated binary data received over a telephone line. This FPGA is intended to perform digital logic, so would normally be used with a synchronising clock, as discussed in the previous section. That would make the frequency discrimination task quite straightforward: the clock could be used to time the input period. In this experiment, however, there will be no clock can evolution exploit the rich natural unconstrained dynamics of the silicon to achieve the task? This seems almost too much to ask: all that is available is 100 FPGA cells, each intended to perform a single Boolean logic function, and each having a delay from input to output of just a few nanoseconds (billionths of a second). How could an arbitrary structure (potentially having many recurrent feedback connections) of these 100 simple high-speed logic gates be evolved to discriminate perfectly between input periods ve orders of magnitude longer than the delay through each component? Success would be signicant: as well as vindicating the `unconstrained' approach to hardware evolution, the resulting circuit (requiring no external components or clock) would be incredibly ecient in its use of silicon. The experimental arrangement is shown in Figure 8. A genetic algorithm runs on a standard PC, and congures the real FPGA for each tness evaluation. The XC6216 FPGA has 64 64 cells, so only a 10 10 corner was used. For each individual circuit, a sequence of test tones (of 1kHz and 10kHz) were applied to the pin designated as the input, and the signal at the pin chosen to be the output was monitored. The tness function was to
Output (to oscilloscope) Analogue integrator configuration Desktop PC XC6216 FPGA Tone generator Figure 8: The arrangement for the tone discriminator experiment. The 10 10 corner of cells used is shown to scale with respect to the whole FPGA. The single input to the circuit was applied as the east-going input to a particular cell on the west edge, as shown. The single output was designated to be the north-going output of a particular cell on the north edge. maximise the dierence in the average output voltage between the case when the 1kHz input was present, and the case when the 10kHz was present (see [19, 17, 6] for full details). This average output voltage was measured by the analogue integrator shown in the gure: the circuit must be evaluated as a continuous-time analogue system, now we have abandoned all of the digital design principles with which the FPGA was intended to be used. A photograph of the circuit-board carrying the FPGA and the circuitry used as part of the tness measurement is shown in Figure 9: it plugs directly into the PC, and is simple and easily built. Throughout the experiment, an oscilloscope was directly attached to the output pin of the FPGA (see Figure 8), so that the behaviour of the evolving circuits could be visually inspected. Figure 10 shows photographs of the oscilloscope screen, illustrating the improving behaviour of the best individual in the population at various times over the course of evolution. The individual in the initial random population of 50 that happened to get the highest score produced a constant +5V output at all times, irrespective of the input. It received a tness of slightly above zero just because of noise. Thus, there was no individual in the initial population that demonstrated
Figure 9: The circuitry to evolve the tone discriminator. any ability whatsoever to perform the task. After 220 generations, the best circuit was basically copying the input to the output. However, on what would have been the high part of the square wave, a high frequency component was also present, visible as a blurred thickening of the line in the photograph. This high-frequency component exceeds the maximum rate at which the FPGA can make logic transitions, so the output makes small oscillations about a voltage slightly below the normal logic-high output voltage for the high part of the square wave. After another 100 generations, the behaviour was much the same, with the addition of occasional glitches to 0V when the output would otherwise have been high. Once 650 generations had elapsed, denite progress had been made. For the 1kHz input, the output stayed high (with a small component of the input wave still present) only occasionally pulsing to a low voltage. For the 10kHz input, the input was still basically being copied to the output. By generation 1100, this behaviour had been rened, so that the output stayed almost perfectly at +5V only when the 1kHz input was present. By generation 1400, the neat behaviour for the 1kHz input had been abandoned, but now the output was mostly high for the 1kHz input, and mostly low for the 10kHz input... with very strange looking waveforms. This behaviour was then gradually improved. Notice the waveforms at generation 2550 they would seem utterly absurd to a digital designer. Even though this is a digital FPGA, and we are evolving a recurrent network of logic gates, the gates are not being used to `do' logic. Logic gates are in fact high-gain arrangements of a few transistors, so that the transistors are usually saturated
1kHz 10kHz IN 3500 2800 2550 2100 1400 1100 650 320 220 0 Figure 10: Photographs of the oscilloscope screen. Top: the 1kHz and 10kHz input waveforms. Below: the corresponding output of the best individual in the population after the number of generations marked down the side.
corresponding to logic 0 and 1. Evolution does not `know' that this was the intention of the designers of the FPGA, so just uses whatever behaviour these high-gain groups of transistors happen to exhibit when connected in arbitrary ways (many of which a digital designer must avoid in order to make digital logic a valid model of the system's behaviour). This is not a digital system, but a continuous-time, continuous valued dynamical system made from a recurrent arrangement of high-gain groups of transistors hence the unusual waveforms. By generation 2800, the only defect in the behaviour was rapid glitching present on the output for the 10kHz input. Here, the output polarity has changed over: it is now low for the 1kHz input and high for 10kHz. Fitnesses were measured such that this swap would have no eect; in general it is a good idea to allow evolution to solve the problem in as many ways as possible the more solutions there are, the easier they are to nd. In the nal photograph at generation 3500, we see the perfect desired behaviour. In fact, there were infrequent unwanted spikes in the output (not visible in the photograph); these were nally eliminated at around generation 4100. The GA was run for a further 1000 generations without any observable change in the behaviour of the best individual. The nal circuit (which I will arbitrarily take to be the best individual of generation 5000) appears to be perfect when observed by eye on the oscilloscope. If the input is changed from 1kHz to 10kHz (or vice-versa), then the output changes cleanly between a steady +5V and a steady 0V without any perceptible delay. The nal circuit is shown in Figure 11; observe the many feedback paths. No constraining preconceptions were imposed on the circuit, so evolution was given the freedom to explore the full space of possible designs.
Out In Figure 11: The nal evolved circuit. The 10 10 array of cells is shown, along with all connections that eventually connect an output to an input. Connections driven by a cell's function output are represented by arrows originating from the cell boundary. Connections into a cell which are selected as inputs to its function unit have a small square drawn on them. The actual setting of each function unit is not indicated in this diagram. Out In Figure 12: The functional part of the circuit. Cells not drawn here can be clamped to constant values without aecting the circuit's behaviour.
By empirical testing, it was possible to determine which parts of the 1010 array were actually contributing to the behaviour. Figure 12 shows this functional part of the circuit. Observe the cells shaded gray: they do inuence the system's behaviour (if an attempt is made to clamp and one of them to a constant value, then the system malfunctions), but yet they are not connected to the main part of the circuit, and there seems to be no route of connections by which they could ever inuence the output pin! These components must be interacting with the others by some subtle unconventional means (such as electromagnetic coupling or power-supply loading) which has been put to use by evolution in composing the overall system behaviour. By releasing the full repertoire of behaviours that the recongurable electronic medium can manifest, evolution has been able to craft a highly ecient complex dynamical system. Conventional design would require 1{2 orders of magnitude more silicon area to achieve the same performance with no external components or clock, and even then it would be dicult. But we have now stepped even further away from being able to understand the system in terms of familiar models. Not only do we have the rich analogue continuoustime dynamics seen in the previous section, but now the interactions between the components cannot completely be described by merely listing the wires connecting them. The functioning of the `gray cells' above shows that the interactions of the components are not solely determined by the connecting wires, but also by their positions in physical space. In particular, the spatial proximity of the components is likely to be important. In general, the size, shape, and location of the components will be important, as well as the point-to-point connections (wires) between them. These extra means of interaction are in some ways a resource to be used, but to the extent that they are unavoidable, they could also be viewed as a constraint. These issues are crucial to understanding the evolution of physical `nervous systems', whether biological or electronic, which must necessarily exist in three-dimensional space. A particularly interesting class of spatial interactions in biology is diuse neural messengers: although it is possible to incorporate these into an ANN model [10], the very phrase `neural network' betrays the extent to which it is often assumed that a topological network of point-to-point interconnections (of perfectly controllable strength) captures all of the important aspects of neural interaction.
I suggest that evolvable hardware, by providing a physical medium in which articial `nervous systems' can be evolved, may provide a tool with which the evolution of natural nervous systems and the engineering inspiration that can be drawn from them may be investigated. Conversely, it is denitely the case that neuroscience is relevant to hardware evolution. 5 Coping with Variations in Components and Interactions Up until now in this paper, I have been guilty of a small deception. I have spoken as if the only reason that human designers work within a constrained space of circuits for instance, synchronous digital logic circuits is to make the design process simple. In fact, precluding the detailed properties of the medium from contributing to the system behaviour not only supports design abstractions, but also gives robustness. Those properties that have been excluded from the designer's model (and prevented from inuencing the system's behaviour by means of constraining its structure and dynamics) can vary greatly without causing the system to malfunction. Such changes typically arise from process variations between nominally identical silicon chips, ageing, and temperature and power-supply uctuations. Once evolution is allowed to explore the full spectrum of possible behaviours that the medium can support, this `automatic' robustness is lost. A trade-o needs to be found between exploiting the properties of the medium, and being tolerant to variations in them. 1 Tolerance to variation in a property does not necessarily imply that the property is not used at all: several aspects of the medium which vary in dierent ways can be balanced against each-other to give stable overall system behaviour, or dierent mechanisms can be called into play for dierent conditions. As in the case of spatial interactions, the evolution of adequate robustness is important for all physical `nervous systems', whether electronic or biological. Nature will be a rich source of inspiration for techniques in the evolution of robustness. Rather than precluding large swathes of the natural behaviour of the medium from ever being put to use (as does conventional 1 Note that a fault is an extreme form of variation, and there are several evolutionary mechanisms by which tolerance can be achieved [15, 16, 18].
design), the natural approach in an evolutionary framework is to provide a selection pressure for robustness, and to allow evolution to build robustness into the overall system behaviour using the full set of resources available. This selection pressure may be provided by evaluating the circuits in the presence of those variations with which they are required to cope, so that to be t they must operate well under a wide set of conditions. An especially promising idea from biology is the notion of an external `timegiver' which can stabilise the timescales of the system's internal dynamics [12]. This timegiver could be inherent in the system's ongoing interaction with the environment: for example, in the tone decoder example of the previous section, the fact that the input waveform is always either 1kHz or 10kHz could be used as a time-reference. In addition, the circuit could interact with an external timegiver more explicitly. In analogy to the daily light/dark cycles that entrain circadian rhythms in animals, a stable oscillation could be applied to the evolving circuits as an extra input, at the same time as a selection pressure towards robustness is maintained. This `clock' is not a constraint on the system's dynamics evolution could choose to ignore it altogether but instead enriches the spectrum of possible dynamical behaviours with stability, which can be incorporated in subtle ways. Preliminary experiments on this `unconstrained' approach to robustness for the tone-discrimination task are encouraging, but not yet conclusive. 6 Summary: Implications for ER We have seen how evolution, when manipulating a real physical electronic medium, can exploit it with orders of magnitude more eciency than conventional design. This is possible because evolution can utilise the emergent behaviour of a collection of components without having to be able to predict or analyse it: the simplifying constraints of traditional methods can be removed, releasing the full capabilities of the physical hardware. Evolvable hardware provides the rst opportunity for the evolution of synthetic physical `nervous systems.' The components of a physical system whether it be biological or electronic have a size, shape, and location, and these are important. Robustness cannot be taken for granted. These issues need to be faced in order to reap the full engineering benets of unconstrained
hardware evolution: the potentially small, low-power, fault-tolerant circuits produced have obvious applications in Evolutionary Robotics and elsewhere. Unconstrained direct hardware evolution may thus also be a useful route to greater realism in ER models aiming to address questions in biology or wishing to take inspiration from it. Acknowledgements Gratitude to the School of Cognitive & Computing Sciences, and to Xilinx, Inc. for funding this work. Personal thanks to Phil Husbands, Dave Cli, Inman Harvey, and John Gray. References [1] D. Cli, I. Harvey, and P. Husbands. Explorations in evolutionary robotics. Adaptive Behaviour, 2(1):73{110, 1993. [2] Hugo de Garis. CAM-BRAIN: The evolutionary engineering of a billion neuron articial brain by 2001 which grows/evolves at electronic speeds inside a Cellular Automaton Machine (CAM). In E. Sanchez and M. Tomassini, editors, Towards Evolvable Hardware: The evolutionary engineering approach, volume 1062 of LNCS, pages 76{98. Springer- Verlag, 1996. [3] L. J. Fogel, A. J. Owens, and M. J. Walsh. Articial Intelligence Through Simulated Evolution. John Wiley & Sons, Inc., 1966. [4] David E. Goldberg. Genetic Algorithms in Search, Optimisation & Machine Learning. Addison Wesley, 1989. [5] Inman Harvey. Species Adaptation Genetic Algorithms: A basis for a continuing SAGA. In F. J. Varela and P Bourgine, editors, Towards a Practice of Autonomous Systems: Proc. 1st Eur. Conf. on Articial Life, pages 346{354. MIT Press, 1992. [6] Inman Harvey and Adrian Thompson. Through the labyrinth evolution nds a way: A silicon ridge. In Tetsuya Higuchi and Masaya Iwata,
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