Academic Course Description SRM University Faculty of Engineering and Technology Department of Electronics and Communication Engineering VL2107 CMOS Mixed Signal Circuit Design Third Semester, 2014-15 (Odd semester) Course (catalog) description: As many real life applications involve both analog and digital circuits, this course aims to introduce the problems in implementing both in a single silicon wafer. Compulsory/Elective course: Elective for M. Tech (VLSI Design) - II year students Credit hours: 3 credits Course coordinator(s) Instructor(s) J. Manjula, Assistant Professor (S.G), Department of ECE Name of the instructor Class handling Office location Office phone Email Consultation J.Manjula M.Tech (VLSI Design) TP12S3 manjula.j@ktr.srmuniv.ac.in Day 4 (1 3pm) Relationship to other courses Pre-requisites : VL2002, VL2004 Assumed knowledge : Knowledge on designing of analog and digital circuits References 1. Razavi, Design of analog CMOS integrated circuits, McGraw Hill, Edition 2002. 2. Razavi, Principles of data conversion system design, Wiley IEEE Press, 1st Edition, 1994. 3. Jacob Baker, CMOS Mixed-Signal circuit design, IEEE Press, 2009. 4. Gregorian, Temes, Analog MOS Integrated Circuit for signal processing, John Wiley & Sons, 1986. 5. Baker, Li, Boyce, CMOS: Circuit Design, layout and Simulation, PHI, 2000. Class schedule: Four 50 minutes Lecture sessions per week, for 15 weeks Section Schedule VLSI Design Day order 2 : Hr 1 Day order 3 : Hr 6 Page 1 of 5
Day order 4 : Hr 3 Day order 5 : Hr 4 Professional component General - 0% Basic Sciences - 0% Engineering sciences & Technical arts - 0% Professional subject - 100% Broad area: Communication Signal Processing Electronics VLSI Embedded Test Schedule - Theory S. No. Test Portions Duration 1 Cycle Test Days 1 to 18 1 hr 40 min 2 Model Exam Days 1 to 45 3 hrs Course objectives Syllabus: To know mixed signal circuits like DAC, ADC, PLL etc. To gain knowledge on filter design in mixed signal mode. To acquire knowledge on design different architectures in mixed signal mode. VL2107- CMOS Mixed Signal Circuit Design Unit I - Phase Locked Loop Characterization of a comparator, basic CMOS comparator design, analog multiplier design, PLL - simple PLL, charge-pump PLL, applications of PLL. Unit II - Sampling Circuits Basic sampling circuits for analog signal sampling, performance metrics of sampling circuits, different types of sampling switches. Sample-and-Hold Architectures- Open-loop & closed-loop architectures, open-loop architecture with miller capacitance, multiplexed-input architectures, recycling architecture, switched capacitor architecture, current-mode architecture. Unit III- D/A Converter Architectures Input/output characteristics of an ideal D/A converter,, performance metrics of D/A converter, D/A converter in terms of voltage, current, and charge division or multiplication,, switching functions to generate an analog output corresponding to a digital input. Resistor-Ladder architectures, Current steering architectures Unit IV - A/D Converter Architectures Input/output characteristics and quantization error of an A/D converter, performance metrics of pipelined architectures, Successive approximation architectures, interleaved architectures. Unit V - Integrator Based Filters Low Pass filters, active RC integrators, MOSFET-C integrators, transconductance-c integrator, discrete time integrators. Filtering topologies - bilinear transfer function and biquadratic transferfunction. Page 2 of 5
Teaching Plan Day # Topics to be covered 1. Characterization of a comparator 2. Basic CMOS comparator. Problems on the design of comparator 3. Analog multiplier design (Multiplying quad) 4. Analog multiplier design (Level shifting) 5. Analog multiplier design (using squaring circuit) - Problems 6. Simple PLL (Blocks description) 7. Simple PLL (Performance parameters) 8. Charge pump PLL 9. Applications of PLL 10. sampling circuits, Basic sampling circuits 11. Performance metrics, Problems in the design of sampling circuits 12. Types of sampling switches 13. 14. Sample and hold architectures, Open loop and closed loop architecture Open loop architecture with miller capacitance 15. Multiplexed input architecture 16. Recycling architecture 17. switched capacitor architecture 18. 19. 20. current mode architecture I/P and O/P characteristics of an ideal A/D converter Performance metrics & Problems Page 3 of 5 Reference Page No:691 Page No:685 Page No:704 Page No:710 Page No:715 Page No:532-538 Page No:532-538 Page No:, 549 Reference book No.1, Chapter 15, Page No:572 Reference book No.5,Chapter 27, Page No:756, Page No:405 Page No:407 Page No:410 Page No:19-26 Page No: 759-762 Page No: 759-762 \ Page No:45 Page No:47
21. D/A converter in terms of Voltage Page No:50 22. D/A converter in terms of Current Page No:55 23. D/A converter in terms of charge division or multiplication Page No:63 24. Switching functions Page No:70 25. D/A architectures - principle Page No:79 26. Resistor-Ladder architecture and problems Page No:79 27. Current steering architecture Page No:84 28. I/P and O/P characteristics of an ideal A/D converter Page No:96 29. Performance metrics & Problems Page No:99 30. Flash architecture & Problems Page No:101 31. Two step architecture 32. Interpolate architecture 33. folding architecture 34. Pipelined architecture 35. Successive approximation architecture 36. Interleaved architecture 37. Low pass filters & Problems 38. Active RC integrators & Problems 39. MOSFET-C integrator 40. Trans conductance integrator 41. Discrete integrator 42. 43. 44. 45. Bilinear transfer function(active RC integrators, MOSFET-C integrator) Bilinear transfer function (Transconductance integrator, Discrete integrator) Biquadratic transfer function (Active RC integrators, Biquadratic transfer function (MOSFET-C integrator) Page No:116 Page No:126 Page No:132 Page No:126 Page No:140 Page No:143 Reference book No.3,Chapter 35, Page No:393 Page No:395 Page No:404 Page No:407 Page No:411 Page No:418 Page No:419 Page No:422 Page No:423 Page 4 of 5
Evaluation methods Cycle Test - 20% Model Test - 20% Surprise Test - 5% Assignment / Term Paper - 5% Final exam - 50% Prepared by: J.Manjula, Assistant Professor(S.G), Department of ECE Dated: 27 June 2014 Revision No.: 00 Date of revision: NA Page 5 of 5