EMC Europe - Hamburg, 8 th September 008 Summary Electrical Characterization of a 64 Ball Grid Array A. Boyer (), E. Sicard (), M. Fer (), L. Courau () () LATTIS - INSA of Toulouse - France () ST-Microelectronics Central R&D - France. Context. EMC ing Issues 3. Under Test 6. Comparison between methods 7. Extension to large BGAs 8. Conclusion EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org. Context. Context Technology 0.8µm 0.µm 90nm 65nm 45nm EMC is the 3rd cause of IC redesign s and simulation tools are required to predict IC emission and susceptibility issues at early stages of design Complexity 50M 00M 50M 500M G Architectural Design IC DESIGN FLOW Tools Design Guidelines Training Packaging IC example IOs 000 µc µc 6b 6b 00 00 00 µc µc 3b 3b 300 300 004 µc+dsp µc+dsp 500 500 006 µc+dsp µc+dsp Flash,Ram Flash,Ram 000 000 008 Multicore, Multicore, DSP, DSP, FPGA, FPGA, RF RF 000 000 Design Entry Design Architect EMC Simulations Compliance? NO GO Need for specific tools, design guidelines and training GO FABRICATION EMC compliant EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 3 EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 4 The freeware platform IC-EMC. Context Dedicated to emission and susceptibility prediction based on existing standards IEC 6 967 for emission IEC 6 3 for susceptibility. Context General flow to validate emission models for ICs Simulations Measurements Spectrum Analyser VNA Spice simulations data (manufacturer) Core Probe Analog Time Domain Simulation Test board Frequency s Time-domain measure Comparison Tuning Macro-model Generation EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 5 This work Fourier Transform Fourier Transform Compare dbµv vs. frequency EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 6
IC. EMC ing Issues The IC model usually includes two parts Core The die(s) ICEM - IEC 6433 Passive Distribution Network (PDN) Internal Activity (IA) IO switching characteristics R,L,C package, length Frequency 3 MHz Band Wave length λ/4 HF 00m 5m. EMC ing Issues Band of interest 30 MHz VHF 0m.5m 300 MHz UHF m 0.5m 3 GHz SHF 0.m 5mm 30 GHz xhf 0mm.5mm Padframe, vias, 3D structure On-package discrete components EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 7 EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 8 3. under test 3. under test CMOS technology Content I/O power supply Core power supply Packaging 90 nm Bidirectional I/O structures.5 V. V LBGA 64 8 8 mm I/O Supply Vdde/Gnde Goal: accurate prediction of emission and immunity Validate of package information High precision extraction of R,L,C package elements Core Supply Vdd/Gnd I/O Supply Vdde/Gnde Core Supply Vdd/Gnd EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 9 EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 0 VNA Measurement Set-Up VNA Measurement Results VNA 00 KHz 3 GHz Power supply Non Linear Effects µh nf Optional bias tee S Measurement Calibration plane Miniature test probe under test Z Extraction Without power supply With power supply EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org
PDN Extraction from VNA Measurement TDR Measurement Results Inductance Effect CVddeGnde Cx On-chip capacitor Lpck Comparison Comparison with with simulation simulation On-Chip Capacitance Effect EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 3 EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 4 PDN Extraction from TDR Measurement On On chip chip capacitor capacitor extracted extracted from from S-parameter S-parameter gives an indication of the BGA pin assignment On-chip capacitor Each pin is assigned a model (In, Out, In/Out, Power, Ground) No information on size, pitch, die size.. E 7 EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 5 EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 6 hidden keywords in file width, height, pitch IC dimensions and positioning Cavity size Type of bonding Physical reconstruction of leads thanks to 3D reconstruction Good points Immediate reconstruction Accurate evaluation of bonding Bad points Supply layers ignored Complex bonding (double, triple) ignored EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 7 Connector divided into 6 parts Simple model assigned to each part Skin effect activated for resistance Possibility of extracting Cx, Lx Sum of all L and all C also available (6) Cavity to IC (5) Cavity to border (4) Via to cavity () Ball (3) Via width () Ball to via cavity Silicon die EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 8 3
Advanced Method PEEC Method adapted to extraction of R, L, C model SPICE compatible Total inductance Complexity of internal routings requires a precise reconstruction of package geometry lead Silicon die Bonding wire Total capacitance Ball EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 9 EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 0 Advanced Method geometrical model 3D construction of the package PEEC / Coupling extraction Geometrical Information µ o l l L = cond dv cond dv 4πA A r r P Evaluate partial inductance and capacitance matrices 4 S S r r = [ ] [ ] da da C = P πε cond cond IC-EMC Simulation Results I/O Power Supply 3.5 0.74 [ L ( nh )] = 0.74. 0.345 0.03 [ C ( pf )] = 0.03 0.85 Core Power Suppy 3.5 0.74 [ L ( nh )] = 0.74.09 Lpck =.9 nh Cpck = 0.8 pf Lpck =.9 nh RLC extraction Self Inductance vs. Pin Number 0.37 0.037 [ C ( pf) ] = 0.037 0.83 Cpck = 0.6 pf EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 6. Comparison between methods 7. Extension to Large BGAs VNA TDR Fast evaluation L package -. nh. nh. - 3.4 nh C package 0. 0.4 pf 0. 0.4 pf 0.8 0.3 pf EM simulation. - 3.9 nh 4 nh 0.7 0.45 pf 0.4 0.8 pf Good Good agreement agreement between between extracted extracted C, C, L and and simulations simulations MPC 5534 496 pins Freescale 3-bit microcontroller Estimation Estimation of of total total VDD VDD and and VSS VSS R,L,C R,L,C for for emission/immunity emission/immunity prediction prediction 3D 3D description description of of some some critical critical nets nets (clock, (clock, IO) IO) Virtex II 000 pins FPGA Estimation Estimation of of IO IO bank bank VDD VDD and and VSS VSS R,L,C R,L,C for for switching switching noise noise prediction prediction EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 3 EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 4 4
Conclusion s and simulation tools are required to predict IC emission and susceptibility at early design phases Key role of package model in IC emission and susceptibility A comparison between several methods and simulations has been presented Results correlate with information from the IC manufacturer The methods can be applied to large BGAs for emission/immunity and signal integrity prediction Thank you for attending post-banquet early session The IC-EMC Tool is available online at www.ic-emc.org EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 5 EMC Europe SEPT 8-, 008 alexandre.boyer@insa-toulouse.fr - www.ic-emc.org 6 5