design number 85739 VLSI Design Chromatic Instrument Tuner For the design of the operational amplifier, we have to take into consideration the constraints due to power supply and technology. Process specifications were obtained from the MOSIS Integrated Circuit Fabrication Sevice website. Power supply: ±2.5V Technology: C5N: 0.5 µm
Also, our desired specifications for our amplifier are: or
If, then, so had to be greater than. A good value for would be. To calculate, slew-rate and are used on the following equation: By using ICMR, the ratio can be calculated by the following equation: microsiemens = 94.25 µa/v To calculate the ratio And to calculate the ratio
has to be greater than, so All these calculations are only to have an idea the values of the MOSFETs in order to get the specifications we need on the op-amp. Regardless, most of the main changes would be made on Cadence by simulations.
The following schematic (Figure 1) is the final design of the operational amplifier that will be used in the instrument tuner design. We also show the specifications for the device. Figure 1 or
The following waveforms (Figure 2) demonstrate how the op amp performs with an inverting configuration at a gain of -4. The input sine wave is at 250mV pk-pk, and the output inverts at 1V pk-pk. Figure 2
The following waveforms (Figure 3) demonstrate how the op amp performs with a non-inverting configuration at a gain of 5. The input sine wave is at 250mV pk-pk, and the output amplifies to 1.25V. Figure 3
The following waveforms (Figure 4) demonstrate how the op amp performs with a simple voltage follower configuration. The input sine wave is at 250mV pk-pk, and the output follows to 250mV pk-pk. Figure 5
Layout of Resistor Theory The basic formula of resistance is In VLSI (Very-Large-Scale Inyegration), since the thickness of any given layer is fixed, the previous formula can be transformed as: In this equation, w is the width of the resistor, ρ' is resistance per square (sheet resistance), and N is the number of squares. In principle, any layer can be used to construct resistor; however, practically only those layers that have weak conductivity are proper for resistor layout. Practice In the process we are using, there are two layers that we usually use for resistor layout, poly and highres poly2. Poly has a sheet resistance of 25Ω/square which is suitable for resistors under 3kΩ. For resistors over 3kΩ, highres poly2, which has a sheet resistance of 1.2kΩ/square, is used. Highres poly2 is not a physical layer. It represents a doping process on poly2 layer which adds impurities to poly2, thus reduces the conductivity. In order to reduce the layout area, minimum width of poly or poly2 path (0.6µm) is applied.
Sample layout of 20kΩ resistor 1. Calculation Note: Round length to the nearest multiple of, 10.05µm. That is, a path of 0.6µm wide and 10.05µm long is needed. 2. Draw poly2 (elec) path 3. Place Contacts Figure 6 Place two M1_ELEC contacts at the two end of the poly2 path. Figure 7
4. Draw highres From the LSW (layer selection window) draw a highres rectangle to cover the area between the contacts. 5. Place pins Figure 8 Place POS and NEG metal1 pins on top of the M1_ELEC contacts. Figure 9
6. Extraction Do an extraction without any switch. Open the extracted view. A resistor symbol should be placed at the left pin. Check the value to ensure it is what you designed for. Figure 10 In this case, the value you see on the extracted view is not exactly 20kΩ, but within the allowed error range.
For our design, we will need a 15KΩ resistor to bias the current mirrors that will power the op amp. Layout Extraction Figure 11 Parameter verification Figure 12
Figure 13 Layout of Capacitor Theory In principle, a capacitor is composed of two adjacent conductor plates with certain type of dielectric in between. The capacitance is calculated based on the following formula: as: If d and ε are constants and the area is a rectangle, the previous formula can be modified Therefore, to lay out a capacitor, we have to figure out the geometric parameters of the rectangle based on C and c. Practice In the process C5N_SUBME (λ=0.30µm), the two polysilicon (poly and elec, also known as poly2) are a proper pair to form a capacitor. The thin silicon dioxide between these adjacent layers yields good capacitance value per unit area. This type of capacitor is called poly-poly2 capacitor.
Sample layout of 100fF capacitor 1. Calculation Note: Round l to the nearest multiple of ; remember in Cadence, we can only draw geometric lengths of multiple. Consequently, if w is given as 13.89µm, you have to convert it to 13.95µm before you get started. 2. Draw poly and elec layers Draw a 9µm x 13.95µm rectangle with elec (yellow). Then cover it with a poly (red), which should exceed every side of elec (yellow) by 3µm.
Figure 14 3. Cover the elec rectangle with M1_ELEC contacts and a metal1 rectangle. Use as many M1_ELEC contact as possible, without violating DRC, to cover the whole effective capacitance area (elec). Then cover the elec with a metal rectangle. The purpose of these contacts and metal1 is to minimize parasitic resistance.
Figure 15 4. Cover the 3µm extended poly edge with M1_POLY contacts and metal1. Use as many M1_POLY contacts as possible, without violating DRC (design rule check), to cover the extended poly edge. Each M1_POLY is 1.2µm wide and DRC requires 1.8µm between the contact and elec. Then cover the M1_POLY contacts with metal1. The purpose of these contacts is also to minimize parasitic resistance.
Figure 16 5. Draw a n-well to cover the whole capacitor Draw an n-well to cover the poly rectangle with 0.6µm extension to fulfill the DRC requirement. The purpose of this n-well is to minimize field leakage. Figure 17
6. Place pins Place a metal2 POS pin and a M2_M1 contact on top of a M1_POLY contact. Place a metal2 NEG pin and a M2_M1 contact on top of a M1_ELEC contact. Of course you can move the pins outside and use metal2 to connect them to the respective contacts. 7. DRC (design rule) check Check DRC, and correct all errors. Figure 18
8. Extraction Do an extraction without any switch and open the extracted view. A capacitor symbol should be placed at the upper-left corner of the inner rectangle. Choose the symbol, and check its value to ensure your layout is correct. You are not going to get an exact match since the adjustment we made to fulfill the requirement, but a reasonable error is allowed. Figure 19
Our design will require two capacitors: a compensating capacitor that will create a dominant pole for the op amp, and another that will block out the DC voltage at the final, buffer stage. The first one that was laid out the compensating capacitor,. The compensating capacitor was calculated at 3pF. Note: The arbitrary width of 60µm is a factor of. Layout Figure 19
Extraction Figure 20 Parameter verification Figure 19
The second capacitor that was laid out was the one for the final stage; it was calculated at 500fF, relatively smaller than the previous one. Note: Since the arbitrary width of 25µm is not a factor of, we also have to adjust it to 25.05µm. Layout Figure 20
Extraction Figure 21 Parameter verification Figure 22
Layout of Operational Amplifier Layout Figure 23
Extracted Figure 24
LVS: Net-lists match Figure 25