BANDWIDTH EFFICIENT TURBO CODING FOR HIGH SPEED MOBILE SATELLITE COMMUNICATIONS S. Adrian BARBULESCU, Wade FARRELL Institute for Telecommunications Research, University of South Australia, Warrendi Road, The Levels, SA 5095, AUSTRALIA. Tel : (61) 8 8302 3870, Fax : (61) 8 8302 3873 Paul GRAY, Mark RICE DSPace, Innovation House, First Avenue, Technology Park, The Levels, SA 5095, AUSTRALIA. Tel : (61) 8 8260 8140, Fax : (61) 8 8260 8141 Mail: adrian@spri.levels.unisa.edu.au, paul@spri.levels.unisa.edu.au wade@spri.levels.unisa.edu.au, mark@dspace.com.au ABSTRACT This paper describes an application of turbo codes in conjunction with 16QAM in high speed mobile satellite communications. The channel characteristics, the architecture of the modem and the performance curves for the selected turbo codes are presented. 1 INTRODUCTION The Institute for Telecommunications Research (ITR) from the University of South Australia investigated suitable modulation and error correction schemes for 2 bit/symbol bandwidth efficiency. A feasibility study was done for data rates between 4.8 kbit/s and 128 kbit/s. Rate half turbo codes obtained from puncturing a rate third turbo code [1, 2] and Gray mapping into a 16 Quadrature Amplitude Modulation (16QAM) scheme [3] is the preferred solution and some of the results are presented in this paper. Following the feasibility study, a proof of concept study which includes building a modem/codec is under way. This will allow optimisation of system parameters and the performance of field trials. The most important factors considered in selecting the coding and modulation scheme were: non-linearities due to the mobile terminal high power amplifier (HPA) multipath fading in the maritime, land transportable and aeronautical environments adjacent channel interference (ACI) and co-channel interference (CCI) phase noise link budget effective isotropic radiated power (EIRP) per channel constraints low delay constraints This paper is organised in the following sections: Section 2 describes the system considerations and the channel model used, Section 3 gives the basic architecture of the modem, and Section 4 presents the BER curves for different interleaver sizes. 2 SYSTEM CONSIDERATIONS The system requirements were to find a coding and modulation scheme that would achieve a very good performance in a non-linear fading channel environment. Adjacent carriers at a level of 6 db above that of the wanted channel at the receiver were also considered. The land transportable environment is characterised by small fading effects due to the relative motion of nearby objects. The maritime environment has in addition slow Doppler rates from ship movement and diffuse reflections at elevation angles of less than 15 degrees. At high elevation angles a carrier to multipath ratio (C/M) of more than 20 db is expected. For both these environments, the channel model used was the Rician flat fading model with a fading bandwidth of 0.7 Hz and C/M typical 15 db. The aeronautical environment is characterised by the direct line of sight and the diffuse path which
can have a delay of tens of microseconds. This is a function of the elevation angle and aircraft altitude. This last component can give rise to inter-symbol interference (ISI) due to frequency selective fading. The channel model considered is shown in Figure 1 and has a direct line of sight plus delayed Rayleigh faded component. The fading bandwidth considered was 100 Hz, C/M = 15 db, multipath delay of typically 10 µs and Doppler shift 2 khz. Multipath Delay to spectral regrowth; also the 16QAM constellation becomes distorted. Although turbo codes are now recognised as the most powerful error control codes, it was necessary to study their performance and sensitivity in conjunction with 16QAM for the above channel models. The use of turbo codes and 16QAM modulation gives approximately 3 db improvement over the best known conventional coding approaches under ideal conditions. The low operating point of the turbo codes is an advantage in a real channel because losses due to phase noise, ACI, CCI, non-linear signal distortion increase with the Signal-to-Noise Ratio (SNR), i.e. real channel impairments are dominated by thermal noise. C/M LPF Gaussian Source Figure 1 - Aeronautical channel model Pilot Symbol Assisted Modulation (PSAM) was used to provide robust performance in the fading channel environments. This scheme also provided accurate channel state information to the turbo decoder under low SNR and fading conditions. PSAM is a particular application of the separation principle where channel estimation is not affected by random data. It also provides an unambiguous carrier-phase reference and is more accurate at low SNR than other decision directed or non-data-aided methods. The drawback of this method is that it uses a small part of the available bandwidth and also reduces the SNR available for data detection due to allotting a small part of the available signal power to the pilot symbols. The pilot symbol chosen is one of the four highest energy points in the 16QAM constellation. The PSAM - based estimator calculates an SNR value for each PSAM symbol, using a running average of 10 previous PSAM symbols. The effects of non-linear HPA characteristics for higher order modulation schemes were also considered. Different back-off figures from the compression point were simulated in conjunction with varying filter roll-off factors. The effect of the HPA non-linearity is to increase the ACI due 3 BASIC ARCHITECTURE The modem is implemented in a Host PC using four dedicated cards: a Digital Signal Processing Card (DSP Card #1), an Intermediate Frequency Card (IF Card), a Data Input/Output Card (Data I/O Card), and either a DSP Card #2 or a Field Programmable Gate Array (FPGA) Card to implement the turbo decoder. A block diagram of the modem is shown in Figure 2. The Graphic User Interface (GUI) implements the man-machine interface which sets the desired configuration for the modem. Each card is interfaced with the Host PC through the Peripheral Component Interface (PCI) bus. There are also dedicated links between the cards. The data channel will normally be generated internally (in the DSP Card #1) from Pseudo Random Binary Sequence (PRBS) generators compatible with the BER test equipment. There is also provision to input data from external sources via the Data I/O Card. The hard decisions from the turbo decoder can also be provided to the Data I/O Card for an external bit error rate (BER) analyser. The DSP Card #1 and the Data I/O Card communicate via the PCI Bus. The DSP Card #1 implements both the Transmitter and the Receiver functions for the modem. The Transmitter produces baseband I and Q samples. The transmit chain is driven by the sample clock of the up-converter on the IF Card. Each time the up-converter requires a new sample it sends a sample request to the Transmitter, which responds with a new sample. The Transmitter generates the data bits internally or input them from an external source via the Data I/O Card. The Transmitter generates a Data clock pulse for the external source, via the Data I/O card, every time it requires a new data bit.
GUI Interface Control and Signalling 64kbit/s User Data Data I/O DSP Card #1 FPGA Card or DSP Card #2 IF Card Channel Simulator RF Equipment Figure 2 - Modem Architecture The following functions are performed in the Transmitter: Input or generate data bits Scramble each frame Turbo encode each frame Insert synchronisation symbols Insert PSAM symbols symbols to each frame 16QAM modulate each frame Filter each frame with a root- Nyquist filter Optionally distort each sample to simulate the effect of a HPA Output each sample to the upconverter on the IF card. The Transmitter on the DSP Card #1 also controls the up-converter on the IF card, and provides signalling information to the PC Host. Most of the parameters in the Transmitter or the Receiver are programmable. The Receiver on the DSP Card #1 receives baseband I and Q samples from the downconverter on the IF Card. The receive chain is driven by the recovered sample clock of the down-converter. Each time the down-converter has a new sample it sends a sample ready signal to the Receiver, which accepts the new sample. The Receiver outputs the decoded data bits to an external sink via the Data I/O Card. Each bit is accompanied with a clock pulse. It is also possible to perform BER measurements within the Receiver. The Receiver implements the following functions: Input each sample from the downconverter on the IF card. Filter each frame with a root- Nyquist filter Synchronise to the received signal timing, frequency, and phase 16QAM demodulate each frame Remove PSAM symbols from each frame Get the decoded bits for each frame Descramble each frame Output the decoded data, or perform a BER measurement The Receiver also initialises and controls the down-converter on the IF card. The IF Card will be programmed via the PCI bus and consists of the Up-converter section and the Down-converter section. The IF Up-converter module up-converts the modulator output to 70 MHz IF. It can also simulate frequency offset and Doppler offset. The IF Up-converter module can be supplied with a sample clock from an external source which will drive the entire transmit chain. The IF Up-converter supplies the modulator module in the Transmitter with a data request signal. The IF Down-converter down-converts the 70 MHz to baseband. It supplies baseband samples to the demodulator module in the Receiver, along with a sample clock. The demodulator
module in turn controls the sampling of the IF Down-converter. The turbo decoding is actually performed by either the DSP Card #2 - Turbo Decoder, or the FPGA Card - Turbo Decoder. The Turbo Decoder can either receive the normalised bit log-likelihood Ratios (LLR), or soft decisions for both I and Q channels and variance estimates. The Turbo Decoder returns soft decisions. One important fact to be considered is the mapping of the data and parity bits to the 16QAM symbol. Let us consider a 16-QAM scheme. At time k, k k k k k we send the symbol u = (u 1,u 2,u 3,u 4 ), through the channel and we receive the point r k in the two dimensional space. It is assumed that at time k, u 1 k and u 2 k modulate the I component and u 3 k and u 4 k modulate the Q component of a 16-QAM scheme. For a rate half coding scheme, there are two data bits and two parity bits in each symbol. The data bit is mapped to the most protected bit in each dimension. This method has the advantage of producing more accurate estimates of the information bit than of the parity bit as can be seen from Figure 3. The most protected bit curve has higher error margin than the least protected bit which is translated in different error probabilities for each bit. The mapping can be either binary mapping (BM) or Gray mapping (GM) in each dimension. The bit estimates for the most protected bit do not depend on whether BM or GM was used. For the least protected bit there is a better bit estimate when Gray mapping is used than natural mapping as can be seen from Figure 3. 5 4 Bit estimation most protected bit least protected bit(gm) least protected bit(bm) 3 2 1 rx_bit_estimate 0-1 -2-3 -4-5 -3-2 -1 0 1 2 3 rx_sym(gm: 01->-3, 00->-1, 10->+1, 11->+3)(BM: 00->-3, 01->-1, 10->+1, 11->+3) Figure 3 - Bit estimates function of the received symbol 4 SYSTEM PERFORMANCE For 2 bit/symbol bandwidth efficiency, Figures 4 to 8 show the performance of 16QAM rate half turbo codes (23, 35) simulated for interleaver sizes of 600, 1000, 2000, 4000 and 8000 bits. In Figure 7 we reproduced the performance achieved at France Telecom University (FTU) and reported in [3, Fig. 7] for 4096 bit interleaver size, 16QAM, 2 bit/sym and 3 iterations. The ITR scheme performs 0.7 db better after 3 iterations and up to 1.0 db better after 8 iterations. Figure 9 compares the performance of the rate half 16QAM scheme used in the ITR modem and the performance of the turbo trellis coded modulation scheme presented in [4] for the same 32768 bits interleaver size and 8 iterations. There is only db difference in performance at the required BER of 1.0E-6. From a hardware implementation point of view the ITR scheme based on rate half elementary encoders requires less decoding effort than for the rate 2/3 codes used in [4]. The interleaver used was as described in [5].
5 CONCLUSION This paper presented an application of turbo codes in mobile satellite communications. The paper described the system considerations, the channel model used, and the basic modem architecture. It showed an application of turbo codes in conjunction with 16QAM which can be successfully used in a non-linear fading environment. The performance of turbo codes using Gray mapping is very close to the performance of parallel concatenated trellis coded modulation [4] scheme for the same interleaver size and number of iterations. From a hardware implementation point of view, the turbo code scheme based on punctured elementary rate half convolutional codes leads to a less complicated turbo decoder scheme than in the case of rate 2/3 codes used in [4]. REFERENCES [1] C. Berrou, A. Glavieux, and P. Thitimajshima, Near Shannon limit errorcorrecting coding and decoding: turbo-codes, ICC 1993, Geneva, Switzerland, pp. 1064-1070, May 1993. [2] S. A. Barbulescu, Iterative decoding of turbo codes and other concatenated codes, Ph.D. dissertation, Aug. 1995. (http://www.itr.unisa.edu.au/~adrian) [3] S. Le Goff, A. Glavieux, and C. Berrou, Turbo-Codes and high spectral efficiency modulation, Proceedings of ICC 94, New Orleans, Louisiana, p. 648, May 1994. [4] S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara, Parallel Concatenated Trellis Coded Modulation, ICC 1996, Dallas, Tx, USA, pp. 974-978, June 1996. [5] D. Divsalar and F. Pollara, Multiple Turbo Codes for Deep-Space Communications, TDA Progress Report 42-121, JPL, Pasadena, Ca. USA, pp.66-76, May 1995. TC_B23_F35 rate 1/2 16QAM, N=600 bits 1it 2it 3it 4it 8it Figure 4 - BER for 600 bits interleaver size,
TC_B23_F35 rate 1/2 16QAM, N=1000 bits "1it" "2it" "3it" "4it" "8it" Figure 5 - BER for 1000 bits interleaver size, TC_B23_F35 rate 1/2 16QAM, N=2000 bits "1it" "2it" "3it" "4it" "8it" Figure 6 - BER for 2000 bits interleaver size,
TC_B23_F35 rate 1/2 16QAM, N=4000 bits FTU_4096_3it "1it" "2it" "3it" "4it" "8it" Figure 7 - BER for 4000 bits interleaver size, TC_B23_F35 rate 1/2 16QAM, N=8000 bits "1it" "2it" "3it" "4it" "8it" Figure 8 - BER for 8000 bits interleaver size,
TC_B23_F35 rate 1/2 16QAM, N=32768 bits, 8 iterations "JPL_2x16384" "ITR_32768" Figure 9 - BER for 32768 bits interleaver size, rate half 16QAM AWGN channel