TECNICAL DATA IN74C257A Quad 2-Input Data Selector/Multiplexer with 3-State Outputs igh-performance Silicon-ate CMOS The IN74C257A is identical in pinout to the LS/ALS257. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device selects a (4-bit) nibble from either the A or B inputs as determined by the Select input. The nibble is presented at the outputs in noninverted from when the Output Enable pin is at a low level. A high level on the Output Enable pin switches the outputs into the highimpedance state. Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to Low Input Current: 1.0 µa igh Noise Immunity Characteristic of CMOS Devices ORDERIN INFORMATION IN74C257AN Plastic IN74C257AD SOIC T A = -55 to 125 C for all packages LOIC DIARAM PIN ASSINMENT FUNCTION TABLE PIN 16 = CC PIN 8 = ND Output Enable Inputs Select Outputs Y0-Y3 X Z L L A0-A3 L B0-B3 X=don t care Z = high-impedance state A0-A3,B0-B3=the levels of the respective Nibble Inputs
MAXIMUM RATINS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to ND) -0.5 to +7.0 IN DC Input oltage (Referenced to ND) -1.5 to CC +1.5 OUT DC Output oltage (Referenced to ND) -0.5 to CC +0.5 I IN DC Input Current, per Pin ±20 ma I OUT DC Output Current, per Pin ±35 ma I CC DC Supply Current, CC and ND Pi ±75 ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -65 to + C T L Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 750 500 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - 10 mw/ C from 65 to 125 C SOIC Package: : - 7 mw/ C from 65 to 125 C mw 0 C RECOMMENDED OPERATIN CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to ND) IN, OUT DC Input oltage, Output oltage (Referenced to ND) 0 CC T A Operating Temperature, All Package Types -55 +125 C t r, t f Input Rise and Fall Time (Figure 1) CC = CC = CC = 0 0 0 1000 500 400 This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be cotrained to the range ND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either ND or CC ). Unused outputs must be left open.
DC ELECTRICAL CARACTERISTICS (oltages Referenced to ND) Symbol Parameter Test Conditio 25 C to -55 C I Minimum igh- Level Input oltage IL Maximum Low - Level Input oltage O Minimum igh- Level Output oltage OUT = or CC - I OUT 20 µa OUT = or CC - I OUT 20 µa I OUT 20 µa CC uaranteed Limit 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 85 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 125 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 Unit I OUT ma I OUT 7.8 ma 3.98 5.48 3.84 5.34 3.7 5.2 OL Maximum Low- Level Output oltage I OUT 20 µa I IN I OZ I CC Maximum Input Leakage Current Maximum Three- State Leakage Current Maximum Quiescent Supply Current (per Package) I OUT ma I OUT.7.8 ma 0. 0. 0.33 0.33 0.4 0.4 IN = CC or ND ± ±1.0 ±1.0 µa Output in igh-impedance State IN = IL or I OUT = CC or ND IN = CC or ND I OUT =0µA ±0.5 ±5.0 ±10 µa 8.0 80 160 µa
AC ELECTRICAL CARACTERISTICS (C L =50pF,Input t r =t f = ) CC Symbol Parameter 25 C to -55 C t PL, t PL t PL, t PL t PLZ, t PZ t PZL, t PZ t TL, t TL Maximum Propagation Delay, Nibble A or B to Output Y (Figures 1and 4) Maximum Propagation Delay, Select to Output Y (Figures 2 and 4) Maximum Propagation Delay, Output Enable to Output Y (Figures 3 and 5) Maximum Propagation Delay, Output Enable to Output Y (Figures 3 and 5) Maximum Output Traition Time, Any Output (Figures 1 and 4) 100 20 17 100 20 17 uaranteed Limit 85 C 125 C Unit C IN Maximum Input Capacitance - 10 10 10 pf C OUT Maximum Three-State Output Capacitance (Output in igh-impedance State) 60 12 10 125 25 21 125 25 21 190 33 190 33 75 15 13 225 45 225 45 90 18 15-15 15 15 pf C PD Power Dissipation Capacitance (Per Package) Used to determine the no-load dynamic power coumption: P D =C PD CC 2 f+i CC CC Typical @25 C, CC =5.0 39 pf Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Test Circuit Figure 5. Test Circuit EXPANDED LOIC DIARAM
N SUFFIX PLASTIC DIP (MS - 001BB) NOTES: 16 1 A F 0.25 (0.010) M T 1. Dimeio A, B do not include mold flash or protrusio. Maximum mold flash or protrusio 0.25 mm (0.010) per side. 9 8 D N B -T- C -T- K SEATIN PLANE M L J Dimeion, mm Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 C 5.33 D 0.36 0.56 F 1.14 1.78 2.54 7.62 J 0 10 K 2.92 3.81 L 7.62 8. M 0.2 0.36 N 0. D SUFFIX SOIC (MS - 012AC) 16 1 D A 0.25 (0.010) M T C M 9 8 B K P C SEATIN PLANE Symbol MIN MAX A 9.8 10 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 Dimeion, mm J 0 8 NOTES: K 0.25 1. Dimeio A and B do not include mold flash or protrusion. M 9 0.25 2. Maximum mold flash or protrusion 5 mm (0.006) per side P 5.8 6.2 for A; for B 0.25 mm (0.010) per side. R 0.25 0.5 J R x 45 F M 1.27 5.72