MC4532B 8-Bit Priority Encoder The MC4532B is cotructed with complementary MOS (CMOS) enhancement mode devices. The primary function of a priority encoder is to provide a binary address for the active input with the highest priority. Eight data inputs (D thru ) and an enable input () are provided. Five outputs are available, three are address outputs (Q thru ), one group select () and one enable output ( ). Features Diode Protection on All Inputs Supply Voltage Range = 3. to 8 Capable of Driving Two LowPower TTL Loads or One LowPower Schottky TTL Load over the Rated Temperature Range NLV Prefix for Automotive and Other Applicatio Requiring Unique Site and Control Change Requirements; AECQ Qualified and PPAP Capable This Device is PbFree and is RoHS Compliant MAIMUM RATIN (Voltages Referenced to V SS ) Rating Symbol Value Unit DC Supply Voltage Range.5 to +8. V Input or Output Voltage Range (DC or Traient) Input or Output Current (DC or Traient) per Pin V in,.5 to +.5 V V out I in, I out ± ma Power Dissipation, per Package (Note ) P D 5 mw Ambient Temperature Range T A 55 to +25 C Storage Temperature Range T stg 65 to + C Lead Temperature (8 Sec Soldering) T L 26 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Temperature Derating: D/DW Package: 7. mw/ C From 65 C To 25 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be cotrained to the range V SS (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or ). Unused outputs must be left open. TRUTH TABLE Input Output D D Q Q = Don t Care Q V SS SOIC6 D SUFFI CASE 75B MARKING DIAGRAM A WL YY, Y WW G PIN ASSIGNMENT 2 3 4 5 6 7 8 4532BG AWLYWW = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. 6 4 3 2 9 D D Q Semiconductor Components Industries, LLC, 24 July, 24 Rev. 9 Publication Order Number: MC4532B/D
MC4532B ORDERING INFORMATION MC4532BDG Device Package Shipping SOIC6 (PbFree) 48 Units / Rail MC4532BDR2G SOIC6 (PbFree) 25 / Tape & Reel NLV4532BDR2G* SOIC6 (PbFree) 25 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD8/D. *NLV Prefix for Automotive and Other Applicatio Requiring Unique Site and Control Change Requirements; AECQ Qualified and PPAP Capable. ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS ) 55 C 25 C 25 C Characteristic Symbol Min Max Min Typ (Note 2) Max Min Max Unit Output Voltage V in = or Level V OL 5..5.5.5.5.5.5.5.5.5 V in = or Level V OH 5. 4.95 9.95 4.95 4.95 9.95 4.95 5. 4.95 9.95 4.95 Input Voltage Level (V O = 4.5 or.5 ) (V O = 9. or. ) (V O = 3.5 or.5 ) V IL 5..5 3. 4. 2.25 4.5 6.75.5 3. 4..5 3. 4. (V O =.5 or 4.5 ) (V O =. or 9. ) (V O =.5 or 3.5 ) Level V IH 5. 3.5 7. 3.5 7. 2.75 5.5 8.25 3.5 7. Output Drive Current (V OH = 2.5 ) Source (V OH = 4.6 ) (V OH = 9.5 ) (V OH = 3.5 ) I OH 5. 5. 3..64.6 4.2 2.4.5.3 3.4 4.2.88 2.25 8.8.7.36.9 2.4 madc (V OL =.4 ) Sink (V OL =.5 ) (V OL =.5 ) I OL 5..64.6 4.2.5.3 3.4.88 2.25 8.8.36.9 2.4 madc Input Current I in ±. ±. ±. ±. Adc Input Capacitance (V in = ) C in 5. 7.5 pf Quiescent Current (Per Package) I DD 5. 5. 2.5.. 5. 2 3 6 Adc Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Package) ( = 5 pf on all outputs, all buffers switching) I T 5. I T = (.74 A/kHz) f + I DD I T = (3.65 A/kHz) f + I DD I T = (5.73 A/kHz) f + I DD Product parametric performance is indicated in the Electrical Characteristics for the listed test conditio, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditio. 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 3. The formulas given are for the typical characteristics only at 25 C. 4. To calculate total supply current at loads other than 5 pf: I T ( ) = I T (5 pf) + ( 5) Vfk where: I T is in A (per package), in pf, V = ( V SS ) in volts, f in khz is input frequency, and k =.5. Adc 2
MC4532B SWITCHING CHARACTERISTICS ( = 5 pf, T A = 25 C) (Note 5) Output Rise and Fall Time t TLH, = (.5 /pf) + 25 t TLH, = (.75 /pf) + 2.5 t TLH, = (.55 /pf) + 9.5 Characteristic Symbol Min t TLH, 5. Typ (Note 6) Max Unit 5 4 2 8 Propagation Delay Time to, = (.7 /pf) + 2, = (.66 /pf) + 77, = (.5 /pf) + 55, 5. 25 8 4 22 6 Propagation Delay Time to, = (.7 /pf) + 9, = (.66 /pf) 57, = (.5 /pf) + 4, 5. 75 9 65 35 8 3 Propagation Delay Time to Q n, = (.7 /pf) + 95, = (.66 /pf) + 7, = (.5 /pf) + 75, 5. 28 4 56 28 2 Propagation Delay Time D n to Q n, = (.7 /pf) + 265, = (.66 /pf) + 37, = (.5 /pf) + 85, 5. 3 7 6 34 22 Propagation Delay Time D n to, = (.7 /pf) + 95, = (.66 /pf) + 7, = (.5 /pf) + 75, 5. 5. The formulas given are for the typical characteristics only at 25 C. 6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 28 4 56 28 2 V out D D SWITCH MATRI Output Under Test Q Q V = V DS = V out Sink Current V = V DS = V out Source Current D thru D thru Q Q ETERNAL POWER SUPPLY I D 5 F PULSE GENERATOR (f o ) D D I D Q Q V SS. F Figure. Typical Sink and Source Current Characteristics Figure 2. Typical Power Dissipation Test Circuit 3
MC4532B PROGRAMMABLE PULSE GENERATOR D D Q Q V SS NOTE: Input rise and fall times are 2 D PIN NO. 5% D 5% 2 5% 3 5% 5% 2 5% 3 5% 4 5% Q Q 5 4 9 7 6 9% 5% % t TLH t TLH t TLH t TLH t TLH 5% 9% 5% % 9% 5% % 9% 5% % 9% 5% % Figure 3. AC Test Circuit and Waveforms 4
MC4532B LOGIC EQUATIONS D = D D Q = (D + + + ) Q = ( + + + ) = ( + + + ) = (D + D + + + + 5 + + ) D 9 Q 2 3 7 Q 2 3 4 5 6 4 Figure 4. Logic Diagram (Positive Logic) 5
MC4532B D D D D9 D8 D D D D D D = " WITH D in = " Q Q Q Q 3/4 MC47B Q3 Q Q Figure 5. Two MC4532B s Cascaded for 4Bit Output V SS DIGITAL TO ANALOG CONVERSION The digital eightbit word to be converted is applied to the inputs of the MC452 with the most significant bit at 7 and the least significant bit at. A clock input of up to 2.5 MHz (at = V) is applied to the MC452B. A compromise between I bias for the MC7 and R between N and Pchannel outputs gives a value of R of 33 k. In order to filter out the switching frequencies, RC should be about. ms (if R = 33 k, C.3 F). The analog 3. db bandwidth would then be dc to. khz. ANALOG TO DIGITAL CONVERSION An analog signal is applied to the analog input of the MC7. A digital eightbit word known to represent a digitized level less than the analog input is applied to the MC452 as in the D to A conversion. The word is incremented at rates sufficient to allow steady state to be reached between incrementatio (i.e. 3. ms). The output of the MC7 will change when the digital input represents the first digitized level above the analog input. This word is the digital representation of the analog word. CLOCK INPUT C E R C E R /2 MC452B /2 MC452B Q Q3 Q4 Q Q3 Q4 D D STOP WORD INCREMENTATION Q Q 7 6 5 4 3 2 A B MC452 C Z MC7 DIGITAL INPUT/OUTPUT 8-BIT WORD TO BE CONVERTED R C ANALOG OUTPUT Figure 6. Digital to Analog and Analog to Digital Converter ANALOG INPUT 6
MC4532B PACKAGE DIMENSIONS SOIC6 CASE 75B5 ISSUE K A 6 9 8 B P 8 PL.25 (.) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAIMUM MOLD PROTRUSION. (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 (.5) TOTAL IN ECESS OF THE D DIMENSION AT MAIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MA MIN MA A 9.8..386.393 B 3.8 4...7 C.35.75.54.68 D.35.49.4.9 F.4.25.6.49 G.27 BSC.5 BSC J.9.25.8.9 K..25.4.9 M 7 7 P 5.8 6.2.229.244 R.25.5..9 T SEATING PLANE G D 6 PL.25 (.) M T B S A S K C M R 45 J F SOLDERING FOOTPRINT 8 6.4 6.2 6 6.58.27 PITCH 8 9 DIMENSIONS: MILLIMETERS ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.oemi.com/site/pdf/patentmarking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 827 USA Phone: 33675275 or 8344386 Toll Free USA/Canada Fax: 33675276 or 83443867 Toll Free USA/Canada Email: orderlit@oemi.com N. American Technical Support: 82829855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 42 33 79 29 Japan Customer Focus Center Phone: 835875 7 ON Semiconductor Website: www.oemi.com Order Literature: http://www.oemi.com/orderlit For additional information, please contact your local Sales Representative MC4532B/D
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