Intel Xeon E3-1230V2 CPU Structural Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com
Structural Analysis Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc. 2012 all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. SAR-1203-801 23241TWJM Revision 1.0 Published: May 15, 2012
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 1.7 Brief Comparison to Intel 32 nm Process Technology 2 Device Overview 2.1 Package and Die 3 Layout Feature Analysis 3.1 Overview 3.2 Selected Metallization and Via Layout Features 3.3 Metal 0, Gate, and Fin Layout Features 4 Process Analysis 4.1 General Structure 4.2 Dielectrics 4.3 Metals 4.4 Vias and Contacts 4.5 MIM Capacitor 4.6 Transistor Overview 4.7 Transistor Fins 4.8 Transistor Gates 4.9 PMOS Transistors 4.10 NMOS Transistors 4.11 Isolation 4.12 Wells and Substrate 5 SRAM Analysis 5.1 Overview and Schematic 5.2 Plan View L3 Cache (High Density) SRAM Analysis 5.3 Cross-Sectional L3 Cache (High Density) SRAM Analysis 5.4 Plan-View Lower Density SRAM Analysis
Structural Analysis 6 Materials Analysis 6.1 Overview 6.2 Dielectrics 6.3 Metals 6.4 MIM Capacitors 6.5 PMOS Transistors 6.6 NMOS Transistors 7 Critical Dimensions 7.1 Die Utilization 7.2 Package, Die, and Standard Logic Cell Size 7.3 Dielectrics 7.4 Metals 7.5 Vias and Contacts 7.6 Transistors 7.7 Isolation 7.8 Wells and Substrate 7.9 L3 Cache SRAM 8 References 9 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Package Edge 2.1.4 Package and Lid 2.1.5 Package X-Ray 2.1.6 Package X-Ray Die Area 2.1.7 Solder Bump Array 2.1.8 Die Photograph 2.1.9 Die Markings 2.1.10 Die Markings (RDL Removed) 2.1.11 CPU Die Corner A 2.1.12 CPU Die Corner B 2.1.13 CPU Die Corner C 2.1.14 CPU Die Corner D 2.1.15 Analysis Sites 2.1.16 Die Utilization Analysis 2.1.17 Minimum NAND Cell Size (A) 2.1.18 Minimum NAND Cell Size (B) 3 Layout Feature Analysis 3.2.1 Metal 8 and Via 8s 3.2.2 Metal 7 and Via 7s 3.2.3 Metal 6 and Via 6s 3.2.4 Metal 6 3.2.5 Metal 5 and Via 5s 3.2.6 Metal 4 3.2.7 Metal 3 3.2.8 Metal 2 and Via 2s 3.2.9 Metal 2 3.2.10 Metal 1 and Via 1s 3.2.11 Metal 1 Pitch 3.3.1 General Gate, Metal 0, and Contact Layout 3.3.2 General Gate and Fin Layout 3.3.3 Long Gate Transistor I/O Structure 3.3.4 Long Gate Transistor Detail
Overview 1-2 4 Process Analysis 4.1.1 Die Thickness 4.1.2 General Die Structure 4.1.3 Die Edge 4.1.4 Die Seal 4.2.1 Passivation 4.2.2 SEM of ILD 8 4.2.3 SEM of ILD 7 4.2.4 TEM of ILD 6 4.2.5 TEM of ILD 5 4.2.6 TEM of ILD 4 4.2.7 TEM of ILD 3 4.2.8 TEM of ILD 2 4.2.9 TEM of ILD 1 4.2.10 TEM of ILD 0 4.2.11 TEM of PMD and STI 4.3.1 Copper Flip-Chip Stud and Metal 9 4.3.2 SEM Metal 9 4.3.3 SEM Metal 9 Minimum Pitch 4.3.4 TEM of Metal 9 Liner and Seed Layer 4.3.5 TEM of Metal 8 4.3.6 TEM of Metal 8 Liner 4.3.7 SEM of Metal 7 4.3.8 TEM of Metal 7 Liner 4.3.9 TEM of Metal 6 4.3.10 TEM of Metal 5 4.3.11 TEM of Metal 4 4.3.12 TEM of Metal 4 Liner 4.3.13 TEM of Metal 3 4.3.14 TEM of Metal 3 Liner 4.3.15 SEM of Metal 2 Minimum Pitch 4.3.16 TEM of Metal 2 Thickness 4.3.17 TEM of Metal 1 and Metal 0 4.3.18 TEM of Metal 1 4.3.19 TEM of Metal 1 Liner 4.3.20 TEM of Metal 0 4.4.1 Minimum Pitch Via 8s 4.4.2 Via 8 Profile 4.4.3 SEM Minimum Pitch Via 7s 4.4.4 Minimum Pitch Via 6s 4.4.5 TEM of Via 5 4.4.6 TEM of Via 4 4.4.7 SEM of Minimum Pitch Via 4 4.4.8 TEM of Via 1 4.4.9 TEM of Metal 1, Via 0, and Metal 0 Local Interconnect
Overview 1-3 4.4.10 TEM of Metal 1, Via 0, and Metal 0 in Gate Direction 4.4.11 TEM of Metal 0 Gate Contact 4.4.12 TEM Across Trench Contacts to NMOS Source/Drains 4.4.13 TEM Along Trench Contacts to NMOS Source/Drains 4.4.14 TEM Across Trench Contacts to PMOS Source/Drains 4.4.15 TEM Along Trench Contacts to PMOS Source/Drains 4.4.16 TEM of NMOS Contact to Gate Spacing 4.4.17 TEM of PMOS Contact to Gate Spacing 4.5.1 Optical Image MIM Capacitor General Layout 4.5.2 SEM MIM Capacitor General Layout 4.5.3 SEM MIM Capacitor Connection to Via 4.5.4 SEM MIM Capacitor and Via 8 Edge 4.5.5 TEM Detail of MIM Capacitor 4.5.6 SEM MIM Capacitor Bottom Plate Connection 4.5.7 TEM MIM Capacitor Top Plate Overlap 4.5.8 TEM MIM Capacitor Connection Detail 4.7.1 Planar and Tri-Gate Transistors 4.7.2 Fin Side Profile Roughness 4.7.3 TEM Fin Overview 4.7.4 NMOS Tri-Gate Transistor Fin 4.7.5 PMOS Tri-Gate Transistor Fin 4.7.6 SEM Tilt View of Tri-Gate Transistors 4.8.1 TEM Gate SWS and Top Fill 4.8.2 TEM PMOS Gate SWS Detail 4.8.3 TEM Gate Structure Comparison Parallel to Fin 4.8.4 TEM Gate Transition Parallel to Gate 4.8.5 TEM Gate Transition Detail Parallel to Gate 4.9.1 TEM Overview of PMOS Metal Gate Parallel to Fin 4.9.2 STEM of SiGe 4.9.3 TEM of PMOS S/D Region Along Fin 4.9.4 TEM of PMOS S/D Region Across Fin 4.9.5 TEM of Bottom of PMOS Gate Trench 4.9.6 TEM of PMOS Gate Dielectric and WF Metal 4.10.1 TEM Overview of NMOS Metal Gate Parallel to Fin 4.10.2 TEM of NMOS Gate Dielectric and WF Metal 4.11.1 TEM Overview of STI Between Fins 4.11.2 TEM of STI 4.12.1 SEM of Epi and Substrate 4.12.2 SEM of N-Well 4.12.3 SIMS of P-Epi 4.12.4 SIMS of P-Well 4.12.5 SIMS of N-Well 4.12.6 SCM of N-Wells, P-Wells, Epi, and Substrate Peripheral Region
Overview 1-4 5 SRAM Analysis 5.1.1 6T SRAM Schematic 5.2.1 L3 Cache SRAM at Metal 2 5.2.2 L3 Cache SRAM at Metal 1 5.2.3 L3 Cache SRAM at Metal 0 5.2.4 L3 Cache SRAM at Gate and Contact Level 5.2.5 L3 Cache SRAM at Gate and Fin Level 5.2.6 TEM L3 Cache SRAM at Gate and Fin Level 5.2.7 L3 Cache SRAM Near Substrate Level 5.3.1 L3 Cache SRAM NMOS Transistor Overview 5.4.1 L2 Cache at Gate and Fin Level 6 Materials Analysis 6.2.1 TEM-EDS Spectrum of Passivation 6.2.2 TEM-EDS Spectrum of ILD 8-3 6.2.3 TEM-EDS Spectrum of ILD 8-2 6.2.4 TEM-EDS Spectrum of ILD 8-1 6.2.5 TEM-EDS Spectrum of ILD 7-2 6.2.6 TEM-EDS Spectrum of ILD 7-1 6.2.7 TEM-EDS Spectrum of ILD 6-2 6.2.8 TEM-EDS Spectrum of ILD 6-1 6.2.9 TEM-EDS Spectrum of ILD 5-2 6.2.10 TEM-EDS Spectrum of ILD 5-1 6.2.11 TEM-EDS Spectrum of ILD 4-2 6.2.12 TEM-EDS Spectrum of ILD 4-1 6.2.13 TEM-EDS Spectrum of ILD 3-2 6.2.14 TEM-EDS Spectrum of ILD 3-1 6.2.15 TEM-EDS Spectrum of ILD 2-2 6.2.16 TEM-EDS Spectrum of ILD 2-1 6.2.17 TEM-EDS Spectrum of ILD 1-2 6.2.18 TEM-EDS Spectrum of ILD 1-1 6.2.19 TEM-EELS Spectrum of ILD 1 6.2.20 TEM-EDS Spectrum of ILD 0-2 6.2.21 TEM-EDS Spectrum of Gate Dielectric Plug 6.2.22 TEM-EELS Spectrum of STI and PMD 6.3.1 TEM-EDS Spectrum of Metal 9 Bulk 6.3.2 TEM-EDS Spectrum of Metal 9 Seed Layer 6.3.3 TEM-EDS Spectrum of Metal 9 Barrier Layer 6.3.4 TEM-EDS Spectrum of Via 8 Metal 8 Interface Layer 6.3.5 TEM-EDS Spectrum of Metal 5 Liner 6.3.6 TEM-EDS Spectrum of Metal 1 Liner 6.3.7 Long Count TEM-EDS Spectrum of Metal 1 Body 6.4.1 TEM-EDS Spectrum of MIM Capacitor Top Plate 6.4.2 TEM-EDS Spectrum of MIM Capacitor Bottom Plate 6.4.3 TEM-EDS Spectrum of MIM Capacitor Dielectric 6.5.1 TEM-EDS Spectrum of Bulk Gate Metal Fill
Overview 1-5 6.5.2 TEM-EELS Spectrum of Bulk Gate Metal Fill Liner 6.5.3 TEM-EDS Spectrum of PMOS Gate Fill 6.5.4 TEM-EELS Spectrum of Barrier to NMOS WF Tuning Metal 6.5.5 TEM-EDS Spectrum of Etch Stop Liner 6.5.6 TEM-EELS Spectrum of PMOS WF Metal 6.5.7 TEM-EDS Spectrum of High-k Gate Dielectric 6.5.8 TEM-EELS of Gate Oxide 6.5.9 TEM-EDS Spectrum of PMOS S/D SiGe 6.5.10 TEM-EDS Spectrum of PMOS S/D Silicide 6.6.1 TEM-EDS Spectrum of Gate WF Tuning Layer 6.6.2 TEM-EDS Spectrum of High-k Gate Dielectric 6.6.3 TEM-EELS Spectrum of NMOS S/D Metal 6.6.4 TEM-EELS Spectrum of Contact Liner
Overview 1-6 1.2 List of Tables 1 Overview 1.4.1 Related Reports Intel E3-1230V2 22 nm Tri-Gate CPU 1.4.2 Device Identification 1.5.1 Die Summary 1.6.1 Process Summary 1.7.1 Comparison of Intel 32 nm Process to 22 nm Process 2 Device Overview 2.1.1 Die Utilization 2.1.2 Package, Die, and Standard Logic Cell Size 4 Process Analysis 4.2.1 Dielectric Thicknesses 4.3.1 Metallization Vertical Dimensions 4.3.2 Metallization Horizontal Dimensions 4.4.1 Via and Contact Dimensions 4.6.1 Transistor Gate Overall Dimensions 4.6.2 Transistor Gate Layer Thickness Dimensions 4.11.1 STI Critical Dimensions 4.12.1 Die Thickness and Well Depths 5 SRAM Analysis 5.1.1 L3 Cache SRAM Transistor Dimensions 7 Critical Dimensions 7.1.1 Die Utilization 7.2.1 Package, Die, and Standard Logic Cell Size 7.3.1 Dielectric Thicknesses 7.4.1 Metallization Vertical Dimensions 7.4.2 Metallization Horizontal Dimensions 7.5.1 Via and Contact Dimensions 7.6.1 Transistor Gate Overall Dimensions 7.6.2 Transistor Gate Layer Thickness Dimensions 7.7.1 STI Critical Dimensions 7.8.1 Die Thickness and Well Depths 7.9.1 L3 Cache SRAM Transistor Dimensions
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