COMBINATIONAL LOGIC CIRCUIT First Class. Dr. AMMAR ABDUL-HAMED KHADER

Similar documents
Experiment # 3 Combinational Circuits (I) Binary Addition and Subtraction

Experiment # 4. Binary Addition & Subtraction. Eng. Waleed Y. Mousa

COMBINATIONAL CIRCUIT

Combinational Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science

4:Combinational logic circuits. 3 July

;UsetJand : Llto Record the truth. LAB EXERCISE 6.1 Binary Adders. Materials. Procedure

UNIT III. Designing Combinatorial Circuits. Adders

Binary Adder and Subtractor circuit

UNIT-IV Combinational Logic

CHAPTER 5 DESIGN OF COMBINATIONAL LOGIC CIRCUITS IN QCA

EXPERIMENT NO 1 TRUTH TABLE (1)

Module 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

Structural VHDL Implementation of Wallace Multiplier

Department of Electronics and Communication Engineering

UNIT-2: BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC CIRCUITS

UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering. Digital Computer Arithmetic ECE 666

Function Table of an Odd-Parity Generator Circuit

TABLE 3-2 Truth Table for Code Converter Example

Unit 3. Logic Design

LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM

Combinational Logic Circuits. Combinational Logic

WEEK 4.1. ECE124 Digital Circuits and Systems Page 1

Linear & Digital IC Applications (BRIDGE COURSE)

Digital Electronics. Functions of Combinational Logic

Combinational Circuits DC-IV (Part I) Notes

Sr. No. Instrument Specifications. TTL (Transistor-Transistor Logic) based on bipolar junction transistors

DESIGN OF 4 BIT BINARY ARITHMETIC CIRCUIT USING 1 S COMPLEMENT METHOD

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI

Lesson: Binary Arithmetic and Arithmetic Circuits-2. Lesson Developer: Dr. Divya Haridas

Gates and Circuits 1

MSI Design Examples. Designing a circuit that adds three 4-bit numbers

Digital System Design

Lab 2: Combinational Circuits Design

Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006

Subject: Analog and Digital Electronics Code:15CS32

Asst. Prof. Thavatchai Tayjasanant, PhD. Power System Research Lab 12 th Floor, Building 4 Tel: (02)

BCD Adder. Lecture 21 1

2 Building Blocks. There is often the need to compare two binary values.

Comparative Analysis of Various Adders using VHDL

Subtractor Logic Schematic

Gates and and Circuits

Logic Circuit Design

DESIGN OF BINARY MULTIPLIER USING ADDERS

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

DELD MODEL ANSWER DEC 2018

Number system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished

Analysis of Low Power, Area- Efficient and High Speed Multiplier using Fast Adder

Binary Addition. Boolean Algebra & Logic Gates. Recap from Monday. CSC 103 September 12, Binary numbers ( 1.1.1) How Computers Work

Laboratory Manual CS (P) Digital Systems Lab

FPGA IMPLEMENATION OF HIGH SPEED AND LOW POWER CARRY SAVE ADDER

Topic Notes: Digital Logic


Exercise 2: OR/NOR Logic Functions

DELD UNIT 3. Question Option A Option B Option C Option D Correct Option A B C

EECS 270 Winter 2017, Lecture 15 Page 1 of 8

An Optimized Implementation of CSLA and CLLA for 32-bit Unsigned Multiplier Using Verilog

CHW 261: Logic Design

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) MODEL ANSWER

Spec. Instructor: Center

Design, Implementation and performance analysis of 8-bit Vedic Multiplier

Design of Modified Shannon Based Full Adder Cell Using PTL Logic for Low Power Applications

Odd-Prime Number Detector The table of minterms is represented. Table 13.1

M.Sc. (Computer Science) Master of Computer Application MS-03 / MCA-203 Course Curriculum for Digital Electronics

Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices

A Structured Approach for Designing Low Power Adders

Digital Fundamentals

Lab Report: Digital Logic

NUMBER SYSTEM AND CODES

International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May-2014 ISSN

Electronics. Digital Electronics

Comparison among Different Adders

Introduction to Digital Logic Missouri S&T University CPE 2210 Adders

Dhanalakshmi College of Engineering

Combinational Logic. Prof.Manoj Kavedia ( )

DMI COLLEGE OF ENGINEERING

DESIGN OF MODIFIED AND UNERRING FOUR BIT BINARY SIGNED SUBTRACTOR

Analysis procedure. To obtain the output Boolean functions from a logic diagram, proceed as follows:

Chapter 1 Binary Systems

PUBLICATIONS OF PROBLEMS & APPLICATION IN ENGINEERING RESEARCH - PAPER CSEA2012 ISSN: ; e-issn:

Digital Electronics 8. Multiplexer & Demultiplexer

Government of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru

DESIGN OF HIGH SPEED 32 BIT UNSIGNED MULTIPLIER USING CLAA AND CSLA

Digital. Design. R. Ananda Natarajan B C D

Navy Electricity and Electronics Training Series


METHODS FOR TRUE ENERGY- PERFORMANCE OPTIMIZATION. Naga Harika Chinta

International Research Journal of Engineering and Technology (IRJET) e-issn:

IES Digital Mock Test

OPTIMIZED MODEM DESIGN FOR SDR APPLICATIONS

ELECTRONIC CIRCUITS. Time: Three Hours Maximum Marks: 100

Exercise 1: AND/NAND Logic Functions

Logic Design I (17.341) Fall Lecture Outline

Practical Workbook Logic Design & Switching Theory

COLLEGE OF ENGINEERING, NASIK

Power Efficient and High Speed Carry Skip Adder using Binary to Excess One Converter

Reinforce the categories of the numerals. Give the child the adult wording for numbers.

High Speed Non-Linear Carry Select Adder

Transcription:

COMBINATIONAL LOGIC CIRCUIT First Class 1

BASIC ADDER Adders are important in computers and also in other types of digital system in which numerical data are processed. An understanding of the basic operation is fundamental to the study of digital system. There are two types of adder: Half-Adder Full-Adder 2

Adder S= ABC + ABC + ABC + ABC =A(B + C)+A(B +C) = A+ B +C 3

Adder 4

Half-Adder Recall the basic rules for binary addition: 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10 The operation are performed by a logic circuit called a Half-Adder. It accepts two binary digits on its inputs and produces two binary digits on its outputs, a sum bit and a carry bit. INPUT A Sum B Carry OUTPUT 5

The Half-Adder We can observe that the sum is 1 only if the inputs are not equal. Therefore the sum can be expressed as the exclusive OR of the input variables. 6

The full-adder accept two input bits and an input carry and generates a sum output and an output carry. The difference between Full & Half-Adder is that the fulladder accepts an input carry. The Full-Adder INPUT A Sum OUTPUT Carry B Cin Cout output carry 7

The Full-Adder After A exclusive-or with B, Cin must be exclusive-ored with their result. This means, that to implement the full-adder sum function, two 2-inputs exclusive-or gates can be used Gates required for one Full-Adder A B Cin A + B A + B + Cin Gates required for Two Half- Adder to complete one Full-Adder A B Cin A + B A + B + Cin (A + B) Cin AB (A + B) Cin A B 8

The Full-Adder The full adder circuit can be constructed from two half adder circuits as shown 9

The Full-Adder Pi = Ai Bi Gi = AiBi sum Si = Pi Ci carry Ci+1 = Gi + PiCi 10

The Full-Adder Example: Determine the output for this full-adder: Solution: A (X-OR) B (X-OR) Cin = 1 + 0 + 1 = 0 with a carry of 1 11

Parallel Binary Adder Two or more full-adder are connected to form parallel binary adder. To add two binary numbers, a full-adder is required for each bit in the numbers. So for 2-bit numbers, two adders are needed; for 4-bit numbers, four adder are used and so on. 12

Parallel Binary Adder Example: Determine the sum generated by the 3-bit parallel adder, and show the intermediate carriers when the binary numbers 101 and 011 are being added. 1 0 0 1 1 1 0 1 1 1 0 0 0 13

Parallel Binary Adder Example: Determine the sum generated by the 4-bit parallel adder, 1011 Ai, 0011 Bi, Solution: 0110 Ci, 1110 Si, 0011 Ci+1 0 1 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 14

4-Bit Parallel Adder The 74LS283 IC (Integrated Circuit) is an example of 4-bit parallel adder. The pin diagram and logic symbol for this IC is shown below. Pin diagram Logic symbol 15

Adder Expanding Cascading of four 4-bit adders to form a 16-bit adder 16

Adder Expanding Example: Show how two 74LS283 adders can be connected to form an 8-bit parallel adders. Show output bits for the following 8-bit input numbers. A8..A1 = 10111001 and B8.B1= 10011110 Solution: The only connection between the two ICs is the carry output (pin9) of the lower order to the carry input (pin7) of the high-order adder, pin7 of the lower-order adder is grounded (no carry input). The total sum is:101010111 17

Adder Expanding A1 1 A2 0 A3 0 A4 1 B1 0 B2 1 B3 1 B4 1 1 2 A5 1 A6 1 A7 0 A7 1 B5 1 B6 0 B7 0 B8 1 5 6 1 0 18

Subtractors The subtraction of two binary numbers may be accomplished by taking the complement of the subtrahend and adding it to the minuend. By this method, the subtraction operation becomes an addition operation requiring full adders for its machine implementation. It is possible to implement subtraction with logic circuits in a direct manner. By this method, each subtrahend bit of the number is subtracted from its corresponding significant minuend bit to form a different bit. If the minuend bit is smaller than the subtrahend bit, a 1 is borrowed from the next significant position. The fact that a 1 has been borrowed must be conveyed to the next higher pair of bits by means of a binary signal coming out (output) of a given stage and going into (input) the next higher stage. 19

Subtractors Example: Subtract the decimal number (78) from (123) 123 (A) or X (Minuend) 78 (B) or Y (Subtrahend) 45 DIFFERENCE 20

Half Subtractor The half-subtractor B0=AB is a combinational D=A + B circuit which is used to perform subtraction of two bits. It has two inputs, A (minuend) and B (subtrahend) and two outputs D (difference) and B (borrow). AB+AB AB B0=AB D=A + B 21

Full Subtractor The full-subtractor is a combinational circuit which is used to perform subtraction of three bits. It has three inputs, A (minuend) and B (subtrahend) and C (subtrahend) and two outputs D (difference) and B (borrow) AC + AB + BC 22

Adder-Subtractor 4-Bit Adder Subtractor M=0, the circuit is an adder (B 0 = B) M=1, the circuit is a subtractor (B 1 = B, C0=1) 23

Decimal Adder Can be designed from 2 4-bit adder and external gates. So the two binary numbers are added normally with external circuit that generates the carry bit C when K+Z8Z4+Z8Z2 =1. When Binary sum is greater than 9 a correction factor=(0110)b should be added i.e. under the condition that Output carry =1 BCD adder block diagram 24