9 V - 75 W laptop adapter with tracking boost PFC pre-regulator, using the L656 and the L6566A Data Brief Features Universal input mains range: 90 64Vac - Frequency 45 65 Hz Output voltage: 9 V@4 A continuous operation Mains harmonics: Acc. to EN6000-- Class-D ST-by mains consumption: Less than 0.5 W @65Vac Overall efficiency: Better than 86% EMI: According to EN550-Class-B Safety: According to EN60950 Low profile design: 5 mm maximum height PCB single layer: single side, 70 µm, CEM-, 78x74 mm, Mixed PTH/SMT Description In this data brief of the EVL6566A-75WADP demo board, the main characteristics and features of a 75 W adapter wide-range input mains, powerfactor-corrected AC-DC adapter using the new L6566A controller and the L656 dedicated to the PFC stage are described. High efficiency and the very low standby input consumption are highlighted in the following figures and tables. The board is programmed for working at fixed frequency (65 khz) under nominal condition (9 V at 4 A). On the secondary side the TSM04 with a precise voltage reference and the optocoupler SFH67A-4 to transfer the error amplifiers information to the primary side have been used. September 007 Rev /8 For further information contact your local STMicroelectronics sales office. www.st.com 8
Efficiency EVL6566A-75WADP Efficiency Table below shows the efficiency with two different input voltages. The table begins with the nominal load at 80 W on the output and it displays the efficiency at every power decrease of 5 W. Table. Efficiency measurements 0 V-50 Hz 5 V-60 Hz Pin Pout Eff. Pin Pout Eff. 85.7 75.05 87.5% 87.4 75.06 86.0% 80.56 70.00 86.9% 80.7 70.00 86.7% 74.9 65.0 86.8% 74.4 65.0 87.4% 68.68 59.97 87.% 68.95 60.00 87.0% 6.40 55.0 88.% 6.80 55.0 86.% 56.96 50.00 87.8% 58.0 50.04 86.% 5. 45.0 86.% 5.80 45.05 87.0% 47.0 40.00 85.% 45.45 40.00 88.0% 4.0 5.05 85.5% 40.5 5.05 86.5% 4.40 0.00 87.% 5.5 0.00 85.% 9.60 5.0 84.5% 9.00 5.0 86.% 4.70 0.00 8.0%.07 0.00 86.7% 7.86 4.94 8.7% 8.6 5.05 8.0%.98 0.00 8.5%.88 0.00 84.% 6.64 5.0 75.5% 6.0 5.05 8.8%.7.99 7.9%.5.99 78.7% Above the 0 W power output, the efficiency is constant over 85%. Figure. Overall efficiency versus output power at nominal mains voltages /8
Full load Full load Figure and Figure below show the drain and gate fly-back waveforms and the relevant switching frequency at full load. Figure. waveforms at 5 V-60 Hz full load Figure. waveforms at 0 V-50 Hz full load CH: gate 6566A CH: gate 6566A /8
Light load condition (fold back frequency) EVL6566A-75WADP Light load condition (fold back frequency) To improve the efficiency at light load, a frequency shifting has been implemented on the board. Thus, at decreasing load, the frequency also decreases. Figure 4 and Figure 5 below show the drain and gate fly-back waveforms and the relevant switching frequency with a load of 0. A. Figure 4. waveforms at 5 V-60 Hz 0. A Figure 5. waveforms at 0 V-50 Hz full load CH: gate 6566A CH: gate 6566A Table below shows the efficiency when we set the power input with.4 or.7 W in two different voltage inputs with the fold back network plugged in. Table. Standby consumption Light load condition Vin = 0 V Vin = 5 V Pin.40.69.4.7 Pout.5.06.70.4 Efficiency 6.9% 6.7% 70.5% 66.7% 4/8
No-load 4 No-load Table gives the power consumption of the circuit during no-load operation. Figure 6 and Figure 7 show the main waveforms under this condition. Table. No-load consumption Vin [Vrms] Input power [W] 90 0.94 5 0.07 0 0.0 65 0.60 Figure 6. waveforms at 5 V-60 Hz no-load Figure 7. waveforms at 0 V-50 Hz no-load CH: V cc 6566A CH: V out adapter CH: V cc 6566A CH: V out adapter 5/8
Schematic EVL6566A-75WADP 6/8 5 Schematic Figure 8. EVL656A-TM-80W schematic 9V@4A 90-64Vac OTP PROT 6 8 5-5-6 5-6 0-8 9 R48 4K7 R48 4K7 R64 50K R64 50K D STTH0A D STTH0A R66 R9 R66 R9 C9 C9 HS HS R M R M 4 U SFH67A-4 U SFH67A-4 R5 K0 R5 K0 C40 0N C40 0N R69 K0 R69 K0 C C R4 R9 R4 R9 D8 STTH08A D8 STTH08A R77 R77 R5 M R5 M C6 C6 D6 LL448 D6 LL448 R0 K R0 K R9 K0 R9 K0 R9 56K R9 56K J MKDS,5/ -5,08 J MKDS,5/ -5,08 D7 BZV55-B8 D7 BZV55-B8 R M R M R7 M R7 M R58 M5770 R58 M5770 R R05 R R05 C4 47N C4 47N D LL448 D LL448 C4 C4 Q0 Q0 R7 0K R7 0K R5 R5 R4 90K R4 90K R6 R6 C9 C9 R55 R R55 R HS HS C C R6 R6 R8 R8 R78 K R78 K C4 C4 C6 N C6 N R5 470R R5 470R C C R65 K R65 K R50 K0 R50 K0 R 5K R 5K R6 K8 R6 K8 C C R47 R47 C C R R R 9K R 9K R0 K R0 K C9 C9 R5 0R56 R5 0R56 C C C4 C4 C8 N0 C8 N0 R4 R4 R4 4R7 R4 4R7 R7 R7 R5 0R56 R5 0R56 D7 STPS0H00CFP D7 STPS0H00CFP R74 47K R74 47K C8 0p C8 0p Q5 STP0NK80ZFP Q5 STP0NK80ZFP L TSL0706 - R5-4R L TSL0706 - R5-4R C0 C0 C44 N C44 N R4 K R4 K D5 STPS0H00CFP D5 STPS0H00CFP HS HS Q9 BC857C Q9 BC857C Q Q R46 5R R46 5R R M R M INV COMP MULT CS 4 VFF 5 TBO 6 PFC-OK 7 PWM-LATCH 8 PWM-STOP 9 RUN 0 ZCD GND GD VCC 4 U L656 U L656 C7 C7 C6 00u - 450V C6 00u - 450V Q Q R7 0R R7 0R C5 u C5 u D STTHL06 D STTHL06 C6 000u - 5V C6 000u - 5V R NTC 0R-S6 R NTC 0R-S6 R7 6K R7 6K R60 6K8 R60 6K8 C4 0N C4 0N R68 0K R68 0K D4.5KE50A D4.5KE50A C7 C7 R6 R6 C5 0p C5 0p R75 K8 R75 K8 N.C. GND GD 4 VCC 5 VCC_PFC 6 DIS 8 COMP 9 AC_OK 6 CS 7 MODE/SC OSC SS 4 VFF 5 VREF 0 ZCD HV U6 L6566A U6 L6566A R8 75K R8 75K R59 K R59 K T SRWEC-T0H4 T SRWEC-T0H4 R6 R6 R R + _ ~ ~ D GBU4J + _ ~ ~ D GBU4J R54 47K R54 47K J MKDS,5/ -5,08 J MKDS,5/ -5,08 CV_OUT 5 CV- 4 V_REF GND 6 CC+ CC- CC_OUT 7 VCC 8 U5 TSM04AIST U5 TSM04AIST R 7R R 7R C5 0N C5 0N L SRW5CQ-T05V0 L SRW5CQ-T05V0 L HF4-0YR0-T0 L HF4-0YR0-T0 C4 0N C4 0N R9 75K R9 75K R70 8K R70 8K D N4005 D N4005 R67 K R67 K C 000u - 5V C 000u - 5V R76 4K7 R76 4K7 R45 K R45 K R57 00R R57 00R F FUSE 4A F FUSE 4A R49 4K R49 4K R5 R7 R5 R7 R8 5K R8 5K Q STP9NK50ZFP Q STP9NK50ZFP C5-400V C5-400V R4 68K R4 68K C 47u - 50V C 47u - 50V C 00u - 5V C 00u - 5V
Revision history 6 Revision history Table 4. Document revision history Date Revision Changes 8-Sep-007 Initial release 7/8
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