IN targeting future battery-powered portable equipment and

1386 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 10, OCTOBER 1999 A 1-V CMOS D/A Converter with Multi-Input Floating-Gate MOSFET Louis S. Y. Wong, Chee Y. Kwok, and Graham A. Rigby Abstract A low-voltage D/A converter using multi-input floating-gate MOSFET within a matrix current cell architecture is described in this paper. The two-input floating-gate p-channel MOSFET of each current cell performs the combined functions of current source and current switch. The double-gate-driven MOSFET circuit technique was employed in the digital circuitry to facilitate low supply voltage operation. A 6-bit and 8-bit digitalto-analog converter (DAC) have been fabricated in standard double-poly double-metal 1.2 m CMOS technology. Measurements show a supply voltage as low as 0.9 and 1.0 V is sufficient to operate the 6-bit and 8-bit DAC, respectively, with a 5 Msamples/s conversion rate. Index Terms CMOS integrated circuits, digital analog conversion, mixed analog digital integrated circuits. I. INTRODUCTION IN targeting future battery-powered portable equipment and biomedical implant systems, it is highly desirable to have both low-voltage and low-power operations. Reducing supply voltage is one of the most effective means of minimizing power consumption. The ultimate goal is to set the supply voltage at around 1 V [1], which enables direct drive by a single NiCd, NiMH, or button-cell battery. With the current trend toward mixed-signal integrated circuit, low supply voltage is needed for both analog and digital portions of the circuit which creates major problems in many analog applications, including the D/A conversion circuitry. Although a number of low-voltage CMOS D/A converters have been published [2] [5], they require a supply voltage of at least 2 V. In this paper, a 1-V CMOS D/A converter [6] is described. It neither uses low threshold voltage transistors, which requires augmenting the standard CMOS process, nor internal charge pumping circuitry. A matrix array currentscaling D/A architecture is used. The uniqueness of this D/A converter is the multi-input floating-gate MOSFET current cell circuit (also known as neu-mos in [7]), which performs the combined function of current source and current switch. It avoids transistor cascoding and facilitates low voltage operation. In addition, the double-gate driven MOSFET technique [8] is used in implementing the digital logic circuitry for low-voltage operation and yet maintaining logic switching speed. A 6- and 8-bit D/A converter have been designed and fabricated on a 1.2- m standard CMOS process. Both converters successfully operated at 1 V. In the following sections, the architecture of the D/A converter and the design Manuscript received June 25, 1998; revised June 11, 1999. L. S. Y. Wong was with the University of New South Wales, Sydney, NSW 2052, Australia. He is now with Cochlear Ltd., Lane Cove, NSW 2066, Australia. C. Y. Kwok and G. A. Rigby are with the School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, NSW 2052, Australia. Publisher Item Identifier S 0018-9200(99)08231-1. Fig. 1. Architecture of the 8-bit floating-gate D/A converter. of the floating-gate current cell circuit are presented. The low voltage circuit technique for digital logic circuitry is also described, followed by experimental results and conclusion. II. FLOATING-GATE D/A CONVERTER The D/A converter, as shown in Fig. 1 for the case of an 8-bit converter, uses the well known current-mode architecture [9] [11] with a matrix array of current cells which gives good accuracy and guarantees monotonicity. For the 6-bit design, the matrix consists of 15 equally weighted current cells for the 4 MSB s and two binary-weighted current cells for the two LSB s [6]. In the 8-bit design, the matrix consists of 31 equally weighted current cells for the five MSB s and three binaryweighted current cells for the three LSB s, as shown in Fig. 1. Each current cell circuit consists of a local decoder, data latch, and a two-input floating-gate transistor. The latch minimizes propagation skew and reduces output glitches caused by nonuniform switching distance between current cells and decoders [9]. The floating-gate transistor performs the dual function of current source and current switch, and its detail description will be covered in Section III. The current output can be converted into voltage output by an external resistor or a transresistance amplifier. In order to minimize the integral nonlinearity (INL) error caused by process gradient error, the hierarchical symmetrical switching sequence was adopted in the matrix [10]. 0018 9200/99$10.00 1999 IEEE

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 10, OCTOBER 1999 1387 Fig. 3. Reference current mirror to generate the bias voltage V b. Fig. 2. Schematic symbol and approximate equivalent circuit representing the capacitive coupling of the two-input floating-gate PMOS transistor. III. FLOATING-GATE CURRENT CELL CIRCUIT In the conventional current source circuit [3], [9], [11], complementary drive signals are needed to switch the current steering transistors simultaneously. These transistors are biased in the saturation region to obtain high output impedance. The theoretical lowest supply voltage limit is the sum of the drainsource saturation voltage plus the gate-source voltage of another transistor. For a typical MOSIS 1.2- m CMOS process, the minimum operating supply voltage is around 1.8 V. With a two-input floating-gate p-channel MOSFET, whose symbolic representation is shown in Fig. 2, it is possible to operate at a supply voltage of 1 V. In this circuit, both current source and current switch functions are combined into a p-channel floating-gate MOSFET,. Fig. 2 is the simplified electrical model where and are the coupling capacitances formed between the floating-gate and inputs and, respectively. In practice the coupling capacitors and are located in portions of the first polysilicon layer that reside over the field oxide region [12]. is defined as the potential of the floating gate. is the gate oxide capacitance between the floating-gate and n-well, whose potential is. Although varies, depending on the operating condition of the transistor, it is relatively small compared to and. It is assumed that there is no initial stored charge in the floating gate and negligible electron injection into the floating gate during operation, in view of the 1-V supply operating range, which is well below the hot-carrier/tunnelling electric field threshold for devices fabricated in the 1.2- m CMOS process. By using the charge conservation principle, the floating-gate potential is approximately given by [7] and [12] It states that the floating gate potential, depends on both inputs, and.if then the transistor (1) is turned on into strong inversion. Similarly, if then the device enters the subthreshold region. Thus, the current source circuit can be turned on or off (subthreshold) by the digital signal, which swings between ground (GND) and. The turned on drain current is also controlled by the biasing voltage established by the reference cell in Fig. 3. Using this configuration, the minimum supply voltage is equal to the threshold voltage of plus the turn on voltage. In designing the floating-gate device, two conditions need to be satisfied. 1) When the current cell is turned on, it should deliver the required current which is established by an appropriate current mirroring arrangement (Fig. 3). 2) When the current cell is turned off, the subthreshold leakage current should be sufficiently small to minimize its contribution to the offset error of the D/A converter. With V, the supply voltage is chosen to be at 1 V. From this, it can be suggested that when is turned on, the floating-gate potential should be about 0.05 V. This range is chosen to ensure all are in strong inversion. When is turned off, it can be calculated that should be higher than 0.35 V to ensure a less than 0.1 LSB offset error. From these ranges, a conservative ratio of can be obtained by using (1) with bias voltage sitting at the midvalue V. Next, the ratio of needs to be determined. From simulation studies, the channel length of is chosen to be 1.8 m, in order to minimize the effects of mismatch and channel length modulation. With the current cell turned on, the simulated drain current of as a function of and channel width is shown in Fig. 4. In the 8-bit design delivering 960 A peak output current, each of the within the matrix array delivers 30 A. Any selection of channel width and along the 30- A line in Fig. 4 would give the required design parameters. Point A is chosen along the 30- A line in Fig. 4 ( = 100/1.8 m and pf), so that is less sensitive to, versus variations due to mismatches. Now, the binary weighted current cells B3, B2, and B1 are required to deliver 15, 7.5, and 3.75 A, respectively. Once again, the relative accuracy is much more important than the absolute accuracy. Hence, the lateral dimensions of,, and channel width of B3 are scaled down by a factor of 1 : 2 exactly, compared to the current cells within the matrix. Similarly, the scaling factor for B2 and B1 is 1 : 4 and 1 : 8 exactly, with all channel lengths maintained at 1.8 m. A similar

1388 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 10, OCTOBER 1999 Fig. 5. Schematic of CMOS inverter using DGMOS p-channel transistor. Fig. 4. Simulation of C b versus channel width for MFG at various drain currents. procedure has been applied to the 6-bit design [6], with the exception that there are only two binary-weighted LSB cells. Apart from all the benefits, there are some drawbacks in this floating-gate D/A converter. The obvious one is the additional area required for the floating-gate coupling capacitors. These floating-gate capacitors are implemented by poly2 over poly1 layers, which take up almost a quarter of the cell area, depending on the fabrication process. Another drawback is the reduced output resistance. In the floating-gate circuit, the output resistance is determined by a single transistor. This will contribute to INL error, if a voltage output is required, because of channel length modulation. However, this error can be eliminated if a transresistance amplifier is used to provide the voltage output. IV. LOW-VOLTAGE DIGITAL DECODING LOGIC Apart from the analog current source circuit, this D/A converter also requires digital circuitry for input logic decoding. With supply voltage very close to the threshold voltage, the switching speed of the digital circuits will become very slow but can be improved by using low threshold transistor processes [13], [14]. Multithreshold processes [15], [16] have also been used to achieve high-speed digital circuits while remaining compatible for analog circuit design, but it incurs additional fabrication cost. In this D/A converter design the double-gate-driven MOSFET (DGMOS) technique [8], for dynamic threshold adjustment, is used to construct the global and local clocking buffer and the data to maintain switching speed even at a very low supply voltage and keeping low static power dissipation. Fig. 5 shows an n-well CMOS inverter with a double-gate driven PMOS transistor. Two components, coupling capacitor and diode, are incorporated into the normal PMOS transistor to form the DGMOS. When the input changes from to GND, PMOS is turned on and will drop toward GND by the action of. At this instant, the PMOS sourcebody junction becomes forward biased. This reduces the effective threshold voltage of PMOS transistor, which results in larger drain conduction current and achieve a stronger pull- Fig. 6. Simulated dynamic I ds V gs curves of the DGMOS and conventional MOSFET. up action to maintaining switching speed. Since the body and gate are capacitively coupled by, the inherent PMOS source-body junction diode will charge up very quickly and eventually settles at, where is the cut-in voltage of the source-body diode. Now, if the input changes from GND back to, the NMOS transistor is turned on and PMOS is turned off. At this time, will rise from toward. Eventually it will drop down to (where is the cut-in voltage of diode ) through the discharge of the diode. At this instant, the PMOS source-body junction is reverse biased which increases the threshold voltage of the transistor and reduces the subthreshold leakage current. A comparison of curve of DGMOS and the conventional MOSFET is shown in Fig. 6, where the DGMOS curve was evaluated dynamically. At a gate voltage of 1 V, the DGMOS increases the drain current to about four times that of the conventional MOSFET. The turn off leakage current is reduced by more than an order of magnitude. In addition, this technique works over a wide supply voltage range. In order to further maintain the switching performance of the NMOS at such low voltages, the body-source junction of all NMOS in the p- substrate are slightly forward biased via of 0.3 V to reduce the threshold voltage of the NMOS slightly but not enough to cause excessive leakage current. No latch-up problem was observed. The detail design analysis, performance evaluation on silicon, and tradeoff of the DGMOS can be found in [8] and [17].

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 10, OCTOBER 1999 1389 Fig. 7. Photomicrograph of the 8-bit D/A converter. Fig. 9. Rising edge and falling edge settling waveforms for the 6-bit converter. Fig. 10. Output spectrum of the 8-bit D/A converter sampling a 980-Hz digital sinusoidal input signal at a rate of 1 Msamples/s. Fig. 8. INL error plot and DNL error plot for the 8-bit D/A converter. V. MEASURED PERFORMANCE The 6- and 8-bit D/A converters were fabricated using the MOSIS 1.2- m double-poly double-metal CMOS process but at two different foundries. The chip micrograph of the 8-bit converter is shown in Fig. 7. The minimum operating supply voltage is 0.9 V and 1 V for the 6- and 8-bit D/A converter, respectively, which is close to the transistor threshold voltage. Prior to measurement, chips were exposed to UV light (253.7 nm) to remove residual charges within the floating gates due to processing. Integral and nondifferential linearity error plots for the 6-bit converter can be found in [6]. INL and DNL error plots for the 8-bit design are shown

1390 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 10, OCTOBER 1999 TABLE I MEASURED PERFORMANCE OF THE 6- AND 8-BIT D/A CONVERTERS in Fig. 8 and. It can be seen that the maximum INL is approximately 1 LSB, this indicates that the proposed converter can provide a resolution of up to 8-bit accuracy in the 1 V supply voltage range without any trimming or calibration. Both converters are monotonic. The measured offset errors are less than 0.15 LSB, which is consistent with the design calculations. Better performance could have been obtained if the 8-bit converter had been fabricated in the same foundry as the 6-bit converter because the lambda parameter was an order of magnitude lower in the latter. A conversion rate of 5 Msample/s was measured at a supply voltage of 0.9 V and 1 V for the 6- and 8-bit converter, respectively. The maximum conversion rate is limited by the digital decoding speed rather than the analog settling time. The average power consumption at full speed are 320 and 850 W for the 6- and 8-bit converter, respectively. The output settling waveforms are very similar in both the 6- and 8-bit designs. Fig. 9 and shows the rising and falling edge settling waveforms for the 6-bit converter. The rising edge overshoot is about 0.8% of the full scale, and the falling edge is less than 0.4% of the full scale. The dynamic performance of the 8-bit D/A converter was also tested. The test set-up uses a 10-bit sequential binary counter and a preprogrammed EPROM stored with an 8-bit digital sinusoidal wave oscillating at 980 Hz, and fed into the D/A converter. The output spectrum of the converter sampling at 1 Msample/s is shown in Fig. 10. The overall signal-to-noise ratio, including distortion, is 40 db below the signal level. Table I summarizes the performance of both D/A converters. VI. CONCLUSION A low-voltage CMOS D/A converter using floating-gate MOSFET current cell circuit within a matrix current cell archi tecture and double gate driven MOSFET technique has been described. The floating-gate transistor performs the combined function of current source and current switch. By incorporating the low voltage double gate driven digital circuitry, both converters operated at 1 V supply and sampled at 5 Msamples/s. Both 6- and 8-bit D/A converters have been fabricated in standard 1.2- m double poly CMOS processes. REFERENCES [1] R. Brodersen, A. Chandrakasan, and S. Sheng, Design techniques for portable systems, in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 168 169. [2] D. Nairn, A 130W DAC for low-power video systems, in Proc. IEEE Custom Integrated Circuits Conf., 1994, pp. 511 514. [3] L. Wong and G. Rigby, A 1.8V 80MS/s pipeline CMOS D/A converter, in Proc. IREE Australian Microelectronics Conf., Oct. 1997, pp. 150 155. [4] T. Miki, Y. Nakamura, Y. Nishikawa, K. Okada, and Y. Horiba, A 10bit 50-MS/s CMOS D/A converter with 2.7 V power supply, in Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, 1992, pp. 92 93. [5] H. Kohno, Y. Nakamura, A. Kondo, H. Amishiro, T. Miki, and K. Okada, A 350MS/s 3.3 V 8-bit CMOS D/A converter using a delayed driving scheme, in Proc. IEEE Custom Integrated Circuits Conf., May 1995, pp. 211 214. [6] L. Wong, C. Kwok, and G. Rigby, A 0.9 V 5MS/s CMOS D/A converter with multi-input floating-gate MOS, in Proc. IEEE Custom Integrated Circuits Conf., May 1997, pp. 305 308. [7] T. Shibata and T. Ohmi, A functional MOS transistor featuring gatelevel weighted sum and threshold operations, IEEE Trans. Electron Devices, vol. 39, pp. 1444 1455, June 1992. [8] L. Wong and G. Rigby, A 1V CMOS digital circuits with double gate driven MOSFET, in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 292 293. [9] T. Miki, T. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, An 80-MHz 8-bit CMOS D/A converter, IEEE J. Solid-State Circuits, vol. SC-21, pp. 983 988, Dec. 1986. [10] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, A 10-b 70MS/s CMOS D/A converter, IEEE J. Solid-State Circuits, vol. 26, pp. 637 642, Apr. 1991. [11] S. Chin and C. Wu, A 10-b 125-MHz CMOS digital-to-analog converter with threshold-voltage compensated current sources, IEEE J. Solid-State Circuits, vol. 29, pp. 1374 1380, Nov. 1994. [12] H. Mehrvarz and C. Kwok, A novel multi-input floating-gate four quadrant analog MOS multiplier, IEEE J. Solid-State Circuits, vol. 31, pp. 1123 1131, Aug. 1996. [13] J. Burr and J. Shott, A 200mV self-testing encoder/decoder using standford ultra-low-power CMOS, in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 84 85. [14] B. Davari, R. Dennard, and G. Shahidi, CMOS scaling for high performance and low power The next ten years, Proc. IEEE, vol. 83, pp. 595 606, Apr. 1995. [15] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, 1 V power supply high-speed digital circuit technology with multithreshold-voltage CMOS, IEEE J. Solid-State Circuits, vol. 30, pp. 847 853, Aug. 1995. [16] T. Douseki, S. Shigematu, Y. Tanabe, M. Harada, H. Inokawa, and T. Tsuchiya, A 0.5 V SIMOX-MTCMOS circuits with 200 ps logic gate, in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 84 85. [17] L. Wong, Low voltage CMOS analog integrated circuit design, Ph.D. dissertation, Univ. New South Wales, Sydney, Australia, pp. 128 146, 1998.