STW8NC90Z N-CHANNEL 900V Ω - 7.6A TO-247 Zener-Protected PowerMESH III MOSFET

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Transcription:

N-CHANNEL 900V - 1.1 Ω - 7.6A TO-247 Zener-Protected PowerMESH III MOSFET TYPE V DSS R DS(on) I D STW8NC90Z 900 V < 1.38 Ω 7.6 A TYPICAL R DS (on) = 1.1 Ω EXTREMELY HIGH dv/dt CAPABILITY GATE- TO-SOURCE ZENER DIODES 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED DESCRIPTION The third generation of MESH OVERLAY Power MOSFETs for very high voltage exhibits unsurpassed on-resistance per unit area while integrating back-to-back Zener diodes between gate and source. Such arrangement gives extra ESD capability with higher ruggedness performance as requested by a large variety of single-switch applications. APPLICATIONS SINGLE-ENDED SMPS IN MONITORS, COMPUTER AND INDUSTRIAL APPLICATION WELDING EQUIPMENT ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V DS Drain-source Voltage (V GS = 0) 900 V V DGR Drain-gate Voltage (R GS = 20 kω) 900 V V GS Gate- source Voltage ±25 V I D Drain Current (continuos) at T C = 25 C 7.6 A I D Drain Current (continuos) at T C = 100 C 4.8 A I DM ( ) Drain Current (pulsed) 30 A P TOT Total Dissipation at T C = 25 C 190 W Derating Factor 1.51 W/ C I GS Gate-source Current (*) ±50 ma V ESD(G-S) Gate source ESD(HBM-C=100pF, R=15KΩ) 4 KV dv/dt (1) Peak Diode Recovery voltage slope 3 V/ns T stg Storage Temperature 65 to 150 C T j Max. Operating Junction Temperature 150 C ( )Pulse width limited by safe operating area (1)I SD 7.6A, di/dt 100A/µs, V DD V (BR)DSS, T j T JMAX. (*)Limited only by maximum temperature allowed July 2000 TO-247 1/8

THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 0.66 C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 C/W Rthc-sink Thermal Resistance Case-sink Typ 0.1 C/W T l Maximum Lead Temperature For Soldering Purpose 300 C AVALANCHE CHARACTERISTICS Symbol Parameter Max Value Unit I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max) 7.6 A E AS Single Pulse Avalanche Energy (starting T j = 25 C, I D = I AR, V DD = 50 V) 430 mj ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF V (BR)DSS Drain-source Breakdown Voltage I D = 250 µa, V GS = 0 900 V BV DSS / T J I DSS I GSS ON (1) DYNAMIC Breakdown Voltage Temp. Coefficient Zero Gate Voltage Drain Current (V GS = 0) Gate-body Leakage Current (V DS = 0) I D = 1 ma, V GS = 0 1 V/ C V DS = Max Rating 1 µa V DS = Max Rating, T C = 125 C 50 µa V GS = ±20V ±10 µa V GS(th) Gate Threshold Voltage V DS = V GS, I D = 250 µa 3 4 5 V R DS(on) Static Drain-source On V GS = 10 V, I D = 3.8 A 1.1 1.38 Ω Resistance I D(on) On State Drain Current V DS > I D(on) x R DS(on)max, V GS =10V 7.6 A g fs (1) Forward Transconductance V DS > I D(on) x R DS(on)max, I D =3.8A 9 S C iss Input Capacitance 3550 pf C oss Output Capacitance V DS = 25V, f = 1 MHz, V GS = 0 205 pf C rss Reverse Transfer Capacitance 25 pf 2/8

ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON (RESISTIVE LOAD) t d(on) Turn-on Delay Time V DD = 450V, I D = 4A 36 ns t r Rise Time R G = 4.7Ω V GS = 10V (see test circuit, Figure 3) 12 ns Q g Total Gate Charge 73 102 nc Q gs Gate-Source Charge V DD = 720V, I D = 8 A, V GS = 10V 18 nc Q gd Gate-Drain Charge 27 nc SWITCHING OFF (INDUCTIVE LOAD) t r(voff) Off-voltage Rise Time V DD = 720V, I D = 8 A, 36 ns t f Fall Time R G =4.7Ω, V GS = 10V 45 ns t c Cross-over Time (see test circuit, Figure 5) 77 ns SOURCE DRAIN DIODE I SD Source-drain Current 7.6 A I SDM (2) Source-drain Current (pulsed) 30 A V SD (1) Forward On Voltage I SD = 7.6 A, V GS = 0 1.6 V t rr Reverse Recovery Time I SD = 8 A, di/dt = 100A/µs, 860 ns Q rr Reverse Recovery Charge V DD = 50V, T j = 150 C 10 µc I RRM Reverse Recovery Current (see test circuit, Figure 5) 24 A GATE-SOURCE ZENER DIODE BV GSO Gate-Source Breakdown Voltage Igs=± 1mA (Open Drain) 25 V αt Voltage Thermal Coefficient T=25 C Note(3) 1.3 10-4 / C Rz Dynamic Resistance I GS = 50 ma 90 Ω Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. V BV = αt (25 -T) BV GSO (25 ) PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to souce. In this respect the 25V Zener voltage is appropiate to achieve an efficient and cost-effective intervention to protect the device s integrity. These integrated Zener diodes thus avoid the usage of external components. 3/8

Safe Operating Area Thermal Impedance Output Characteristics Transconductance Transfer Characteristics Static Drain-source On Resistance 4/8

Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temp. Source-drain Diode Forward Characteristics Normalized On Resistance vs Temperature 5/8

Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit 6/8

TO-247 MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 4.7 5.3 0.185 0.209 D 2.2 2.6 0.087 0.102 E 0.4 0.8 0.016 0.031 F 1 1.4 0.039 0.055 F3 2 2.4 0.079 0.094 F4 3 3.4 0.118 0.134 G 10.9 0.429 H 15.3 15.9 0.602 0.626 L 19.7 20.3 0.776 0.779 L3 14.2 14.8 0.559 0.582 L4 34.6 1.362 L5 5.5 0.217 M 2 3 0.079 0.118 P025P 7/8

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2000 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 8/8

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