MAX77, MAX7 P Supervisory Circuits The MAX77/7 are costeffective system supervisor circuits designed to monitor in digital systems and provide a reset signal to the host processor when necessary. No external components are required. The reset output is driven active within sec of falling through the reset voltage threshold. Reset is maintained with ms of delay time after rise above the reset threshold. The MAX77/7 have a low quiescent current of at = 3.3, an activehigh and activelow with a pushpull output. The output is guaranteed valid down to =.. The MAX77/7 have a Manual Reset MR input and a +.5 threshold detector for powerfail input PFI. These devices are available in a Micro and SOIC package. Features Precision Supplyoltage Monitor MAX77:.63 Reset Threshold oltage MAX7: Standard Reset Threshold oltages (Typical):.3, 3.,.93,.63 Reset Threshold Available from.6 to.9 with m Increments (Factory Option) ms (Typ) Reset Timeout Delay A ( = 3.3 ) Quiescent Current Active_High and Active_Low Reset Output Guaranteed _L and Output alid to =. oltage Monitor for PowerFail or LowBattery Warning Pin SOIC or Micro Package PbFree Packages are Available xxx A Y W Micro CUA SUFFIX CASE 6A = Specific Device Code = Assembly Location = Year = Week = PbFree Package SOIC ESA SUFFIX CASE 75 PIN CONFIGURATION MARKING DIAGRAMS xxx AYW xxxxx ALYW xxxxx = Specific Device Code AL = Assembly Lot Code Y = Year W = Week = PbFree Package (Note: Microdot may be in either location) Applications Computers Embedded System Battery Powered Equipment Critical P Power Supply Monitor MR 3 Micro NC 7 PFO 6 PFI 5 (Top iew) SOIC MR PFI 3 7 6 NC 5 PFO (Top iew) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, 5 August, 5 Rev. Publication Order Number: MAX77/D
MAX77, MAX7 MR + GENERATOR PFI TH +.5 PFO Figure. Representative Block Diagram MAXIMUM RATINGS (Note ) Rating Symbol alue Unit Supply oltage 6. Output oltage out.3 to ( +.3) Output Current (All Outputs) I out ma Input Current ( and ) I in ma Thermal Resistance JunctiontoAir R JA C/W Micro SOIC 7 Operating Ambient Temperature T A to +5 C Storage Temperature Range T stg to +5 C LatchUp Performance Positive Negative I LATCHUP 3 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. This device series contains ESD protection and exceeds the following tests: Human Body Model per MILSTD3, Method 35. Machine Model Method.. The maximum package power dissipation limit must not be exceeded. PD T J(max) TA with T J(max) = 5 C R JA ma
MAX77, MAX7 ELECTRICAL CHARACTERISTICS ( =. to 5.5, T A = C to +5 C, unless otherwise noted. Typical values are at T A = 5 C, = 3.3.) Characteristics Symbol Min Typ Max Unit Operating oltage Range. 5.5 Supply Current = 3.3 = 5.5 Reset Threshold MAX77 T A = +5 C T A = C to +5 C MAX7 T A = +5 C T A = C to +5 C MAX7T T A = +5 C T A = C to +5 C MAX7S T A = +5 C T A = C to +5 C MAX7R T A = +5 C T A = C to +5 C Reset Threshold Hysteresis HYS. TH m Falling Reset Delay ( = TH +. to TH. ) t PD S Reset Active Timeout Period t RP 33 ms _L, _H Output Low oltage., I ol = A.7, I ol =. ma.5, I ol = 3. ma _L, _H Output High oltage., I oh = 5 A.7, I oh = 5 A.5, I oh = A I CC TH ol oh.56.5.3.5 3.3 3..9.5.59.55... MR_L Pullup Resistance R MRI 5 K MR_L Pulse Width ( TH (max) 5.5 ) t MR. S MR_L Glitch Rejection ( TH (max) 5.5 ). S MR_L High_level Input Threshold ( TH (max) 5.5 ) IH.7 MR_L Low_level Input Threshold ( TH (max) 5.5 ) IL.3 6.63.3 3..93.63.7.75.5.5 3.3 3.5.97 3..67.7.3.3.3 A MR_L to _L and _H Output Delay ( TH (max) 5.5 ) t MD. S PFI Input Threshold ( = 3.3, PFI Falling)..5.3 PFI Input Current 5. 5 na PFI to PFO Delay ( = 3.3, OERDRIE = 5 m) 3. S PFO_L Output Low oltage =.7, I ol =. ma =.5, I ol = 3. ma ol.3.3 PFO_L Output High oltage =.7, I oh = 5 A =.5, I oh = A oh.. 3
MAX77, MAX7 PIN DESCRIPTION (Pin No. with parentheses is for Micro package.) Pin No. Symbol Description (3) ÁÁÁ Manual Reset Input. MR can be driven from TTL/CMOS logic or from a manual Reset switch. This input, when ÁÁÁ floating, is internally pulled up to with 5 k resistor. () ÁÁÁ Supply oltage: C = nf is recommended as a bypass capacitor between and. 3 (5) ÁÁÁ Ground Reference (6) ÁÁÁ Power Fail oltage Monitor Input. When PFI is less than.5, PFO goes low. Connect PFI to or when not used. ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ MR ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ PFIÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 5 (7) PFO Power Fail Monitor Output. When PFI is less than.5, it goes low and sinks current. Otherwise, it remains high. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 6 () NC Nonconnective Pin ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 7 () Active Low can be triggered by ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CC below the threshold level or by a low signal on MR. It remains low for ms (typ.) after rises above the reset threshold. ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ () Active high output the inverse of one. I OUT, OUTPUT SINK CURRENT (ma) 3. T A = 5 C in =.5 T A = 5 C out = in..5 6 in.5..5..5 in =. 6 in. in.5.5..5... 3.. 5. 6. out, OUTPUT OLTAGE () in, INPUT OLTAGE () I OUT, OUTPUT SOURCE CURRENT (ma) Figure. MAX77/7 Series.6 Reset Output Sink Current vs. Output oltage Figure 3. MAX77/7 Series.6 Reset Output Source Current vs. Input oltage I OUT, OUTPUT SINK CURRENT (ma) 6 T A = 5 C.5 in =.5 in =. in =.5..5..5 3. I out, OUTPUT SOURCE CURRENT (ma) 6 T A = 5 C out = in. in.5 6 in. in.5... 3.. 5. 6. out, OUTPUT OLTAGE () in, INPUT OLTAGE () Figure. MAX77/7 Series.93 Reset Output Sink Current vs. Output oltage Figure 5. MAX77/7 Series.93 Reset Output Source Current vs. Input oltage
MAX77, MAX7 I out, OUTPUT SINK CURRENT (ma) 3 T A = 5 C in =. 5 in = 3. 5 in =. 5 I out, OUTPUT SOURCE CURRENT (ma) T A = 5 C 6 out = in. in.5 in. 6 in.5... 3.. 5.... 3.. 5. 6. out, OUTPUT OLTAGE () in, INPUT OLTAGE () DET, DETECTOR THRESHOLD OLTAGE (OLTS) 65 6 65 6 65 6 595 59 55 5 Figure 6. MAX77/7 Series.9 Reset Output Sink Current vs. Output oltage 5 5 DET+ DET 5 75 T A, AMBIENT TEMPERATURE ( C) DET, DETECTOR THRESHOLD OLTAGE (OLTS) 3 3 3 39 3 37 Figure 7. MAX77/7 Series.9 Reset Output Source Current vs. Input oltage DET+ DET 36 5 5 5 5 75 T A, AMBIENT TEMPERATURE ( C) DET, DETECTOR THRESHOLD OLTAGE (OLTS) 5 5 9 96 9 9 9 Figure. MAX77/7 Series.6 Detector Threshold oltage vs. Temperature DET+ DET 5 5 5 5 75 T A, AMBIENT TEMPERATURE ( C) Figure 9. MAX77/7 Series.9 Detector Threshold oltage vs. Temperature T PD,, FALLING DELAY ( s) 5 35 3 5 5 5 Figure. MAX77/7 Series.93 Detector Threshold oltage vs. Temperature TH =.9 TH =.93 TH =.6 6 T A, AMBIENT TEMPERATURE ( C) Figure. MAX77/7 Series Falling Reset Delay vs. Temperature 5
MAX77, MAX7 APPLICATIONS INFORMATION Microprocessor Reset To generate a processor reset, the manual Reset input allows different reset sources. A pushbutton switch can be one of these. It is effectively debounced by the. s minimum reset pulse width. As MR is TTL/CMOS logic compatible, it can be driven by an external logic line. TH TH t RP t RP MR t MD t MR Figure. and MR Timing Transient Rejection The MAX77/7 provides accurate monitoring and reset timing during powerup, powerdown, and brownout/sag conditions, and rejects negative glitches on the power supply line. Figure 3 shows the maximum transient duration vs. maximum negative excursion (overdrive) for glitch rejection. For a given overdrive, the point of the curve is the maximum width of the glitch allowed before the device generates a reset signal. Transient immunity can be improved by adding a capacitor ( nf for example) in close proximity to the pin of the MAX77/7. MAXIMUM TRANSIENT DURATION ( s) 3 5 5 5 TH =.9 TH = 3. TH =.6 3 5 7 9 3 5 TH Duration Overdrive COMPARATOR OERDRIE (m) Figure 3. Maximum Transient Duration vs. Overdrive for Glitch Rejection at 5 C 6
MAX77, MAX7 Signal Integrity During PowerDown The MAX77/7 output is valid until falls below.. Then, the output becomes an open circuit and no longer sinks current. This means CMOS logic inputs of the P will be floating at an undetermined voltage. Most digital systems are completely shutdown well above this voltage. However, in the case must be maintained valid to =, a pull down resistor must be connected from to ground to discharge stray capacitances and hold the output low (Figure ). This resistor value, though not critical, should be chosen large enough not to load and small enough to pull it to ground. R = k will be suitable for most applications. components are required to follow the reset I/O of the P, the buffer should be connected as shown with the solid line. MAX77/7.7 k BUFFER P BUFFERED TO OTHER SYSTEM COMPONENTS MAX77/7 Figure. Ensuring alid to = R k Interfacing with Ps with Bidirectional I/O Pins Some Ps have bidirectional reset pins. If, for example, the output is driven high and the P wants to put it low, indeterminate logic level may result. This can be avoided by adding a.7 k resistor in series with the output of the MAX77/7 (Figure 5). If there are other components in the system that require a reset signal, they should be buffered so as not to load the reset line. If the other Figure 5. Interfacing to Bidirectional Reset I/O Monitoring Additional Supply Levels When connecting a voltage divider to PFI and adjusting it properly, you can monitor a voltage different than the unregulated DC one. As shown in Figure 6, to increase noise immunity, hysteresis may be added to the powerfail comparator just by a resistor between PFO and PFI. Not to unbalance the potential divider network, R3 should be times the sum of the two resistors R and R. If required, a capacitor between PFI and will reduce the sensitivity of the circuit to highfrequency noise on the line being monitored. The PFO output may be connected to MR input to generate a low level on the when _ drops out of tolerance. Thus a is generated when one of the two voltages is below its threshold level. _3 _ PFO R MAX77/7 P R MR PFI PFO R3 L H _ L.5 R.5 R.5 cc_ R3 H.5 ( R R R3 R R3 ) HYS H L R cc_ R3 Figure 6. Monitoring Additional Supply Levels 7
MAX77, MAX7 ORDERING INFORMATION Device Marking Reset Threshold () Package Shipping MAX77ESAT S77.63 SOIC 5 Tape & Reel MAX77ESATG S77.63 SOIC (PbFree) 5 Tape & Reel MAX7ESAT S7.3 SOIC 5 Tape & Reel MAX7ESATG S7.3 SOIC (PbFree) 5 Tape & Reel MAX7RESAT S7R.63 SOIC 5 Tape & Reel MAX7RESATG S7R.63 SOIC (PbFree) 5 Tape & Reel MAX7SESAT S7S.93 SOIC 5 Tape & Reel MAX7SESATG S7S.93 SOIC (PbFree) 5 Tape & Reel MAX7TESAT S7T 3. SOIC 5 Tape & Reel MAX7TESATG S7T 3. SOIC (PbFree) 5 Tape & Reel MAX77CUAT SAC.63 Micro Tape & Reel MAX77CUATG SAC.63 Micro (PbFree) Tape & Reel MAX7CUAT SAD.3 Micro Tape & Reel MAX7CUATG SAD.3 Micro (PbFree) Tape & Reel MAX7RCUAT SAG.63 Micro Tape & Reel MAX7RCUATG SAG.63 Micro (PbFree) Tape & Reel MAX7SCUAT SAF.93 Micro Tape & Reel MAX7SCUATG SAF.93 Micro (PbFree) Tape & Reel MAX7TCUAT SAE 3. Micro Tape & Reel MAX7TCUATG SAE 3. Micro (PbFree) Tape & Reel For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D.
MAX77, MAX7 PACKAGE DIMENSIONS Micro CASE 6A ISSUE F PIN ID K T SEATING PLANE.3 (.5) G A B D PL. (.3) M T B S A S C H J L NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 9.. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED.5 (.6) PER SIDE.. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED.5 (.) PER SIDE. 5. 6A OBSOLETE, NEW STANDARD 6A. MILLIMETERS INCHES DIM MIN MAX MIN MAX A.9 3... B.9 3... C..3 D.5...6 G.65 BSC.6 BSC H.5.5..6 J.3.3.5.9 K.75 5.5.7.99 L..7.6. SOLDERING FOOTPRINT*. X..3.5 X 3..6..67 5...65 6X.56 SCALE : mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 9
MAX77, MAX7 PACKAGE DIMENSIONS SOIC CASE 757 ISSUE AG Y B X A 5 S.5 (.) M Y M K NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 9.. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.7 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 75 THRU 756 ARE OBSOLETE. NEW STANDARD IS 757. Z H G D C.5 (.) M Z Y S X S SEATING PLANE. (.) N X 5 M J MILLIMETERS INCHES DIM MIN MAX MIN MAX A. 5..9.97 B 3...5.57 C.35.75.53.69 D.33.5.3. G.7 BSC.5 BSC H..5.. J.9.5.7. K..7.6.5 M N.5.5.. S 5. 6... SOLDERING FOOTPRINT*.5.6 7..75..55.6..7.5 SCALE 6: mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Micro is a trademark of International Rectifier. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Phoenix, Arizona 53 USA Phone: 977 or 336 Toll Free USA/Canada Fax: 9779 or 3367 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 955 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, Meguroku, Tokyo, Japan 535 Phone: 3577335 ON Semiconductor Website: Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MAX77/D