Si5C N-Channel 3 V (-S) MOSFET PROUCT SUMMARY V S (V) R S(on) ( ) I (A) a Q g (Typ.) 3. at V GS = V 6.3 at V GS =.5 V 6 nc ChipFET 6-8 FEATURES TrenchFET Power MOSFET Material categorization: For definitions of compliance please see /doc?999 APPLICATIONS Load Switch - Notebook PC Ordering Information: Si5C-T-GE3 (Lead (Pb)-free and Halogen-free) S Bottom View G Marking Code AF XXX Part # Code Lot Traceability and ate Code G S N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (T A = 5 C, unless otherwise noted) Parameter Symbol Limit Unit rain-source Voltage V S 3 V Gate-Source Voltage V GS ± 5 T C = 5 C 6a T Continuous rain Current (T J = 5 C) C = 7 C I 6 a T A = 5 C 6 a T A = 7 C 6 a A Pulsed rain Current I M T C = 5 C Continuous Source-rain iode Current I 5. a S T A = 5 C. b, c Single Pulse Avalanche Current I AS 6 L =. mh Avalanche Energy E AS.8 mj T C = 5 C 6.5 Maximum Power issipation a T C = 7 C P W T A = 5 C.5 b, c T A = 7 C.6 b, c Operating Junction and Storage Temperature Range T J, T stg - 55 to 5 C Soldering Recommendations (Peak Temperature) d, e 6 THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambient b, f t 5 s R thja 5 C/W Maximum Junction-to-Foot (rain) Steady State R thjf 5 Notes: a. Package limited. b. Surface mounted on x FR board. c. t = 5 s. d. See solder profile (/doc?7357). The ChipFET 6-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 8 C/W. ocument Number: 73776 S3-97-Rev. C, -Feb-3 THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT /doc?9
Si5C SPECIFICATIONS (T J = 5 C, unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit Static rain-source Breakdown Voltage V S V GS = V, I = 5 µa 3 V V S Temperature Coefficient V S /T J 9. I = 5 µa V GS(th) Temperature Coefficient V GS(th) /T J -.6 mv/ C Gate-Source Threshold Voltage V GS(th) V S = V GS, I = 5 µa..3 V Gate-Source Leakage I GSS V S = V, V GS = ± 5 V ± ns V S = 3 V, V GS = V Zero Gate Voltage rain Current I SS V S = 3 V, V GS = V, T J = 55 C µa On-State rain Current a I (on) V S 5 V, V GS = V A V GS V, I =.8 A rain-source On-State Resistance a.. R S(on) V GS.5 V, I =. A..3 Forward Transconductance a g fs V S = 5 V, I =.8 A 7 S ynamic b Input Capacitance C iss 95 Output Capacitance C oss V S = 5 V, V GS = V, f = MHz 3 pf Reverse Transfer Capacitance C rss 8 V S = 5 V, V GS = V, I =.8 A 3 Total Gate Charge Q g 7 nc Gate-Source Charge Q gs V S = 5 V, V GS =.5 V, I =.8 A 3. Gate-rain Charge Q gd. Gate Resistance R g f = MHz. Turn-On elay Time t d(on) 7 6 Rise Time t r V = 5 V, R L =.63 75 3 Turn-Off elay Time t d(off) I 5.7 A, V GEN =.5 V, R g = 33 Fall Time t f 8 Turn-On elay Time t d(on) 5 ns Rise Time t r V = 5 V, R L =.5 38 57 Turn-Off elay Time t d(off) I 6 A, V GEN = V, R g = 6 Fall Time t f 9 rain-source Body iode Characteristics Continuous Source-rain iode Current I S T C = 5 C 6 Pulse iode Forward Current I SM A Body iode Voltage V S I S =.3 A, V GS = V.8. V Body iode Reverse Recovery Time t rr 36 ns Body iode Reverse Recovery Charge Q rr I F =.3 A, di/dt = A/µs, 7 nc Reverse Recovery Fall Time t a T J = 5 C 9 Reverse Recovery Rise Time t b 5 ns Notes: a. Pulse test; pulse width 3 µs, duty cycle %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ocument Number: 73776 S3-97-Rev. C, -Feb-3 THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT /doc?9
Si5C TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) V GS = V 5 I - rain Current (A) 3 V GS = thru 5 V V GS = 3 V I - rain Current (A) 3 T J = 5 C T J = 5 C V GS = V..6..8. 3. V S - rain-to-source Voltage (V) Output Characteristics T J = - 55 C..6..8. 3. V GS - Gate-to-Source Voltage (V) Transfer Characteristics. 5 - On-Resistance (mω) R S(on).3. V GS =.5 V V GS = V C - Capacitance (pf) 9 6 3 C oss C iss C rss. 8 6 3 I - rain Current (A) On-Resistance vs. rain Current and Gate Voltage 5 5 5 3 V S - rain-to-source Voltage (V) Capacitance.8 - Gate-to-Source Voltage (V) V GS 8 6 I = 6 A V S = 5 V V S = V - On-Resistance (Normalized) R S(on).6....8 V GS = V, I =.8 A V GS =.5 V, I =. A 6 8 Q g - Total Gate Charge (nc) Gate Charge.6-5 - 5 5 5 75 5 5 T J -Junction Temperature ( C) On-Resistance vs. Junction Temperature ocument Number: 73776 S3-97-Rev. C, -Feb-3 3 THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT /doc?9
Si5C TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) - Source Current (A) I S.. T A = 5 C T A = 5 C - On-Resistance (Ω) R S(on).6.5..3.. T A = 5 C I =.8 A T A = 5 C.....6.8... V S -Source-to-rain Voltage (V) Source-rain iode Forward Voltage. 6 8 V GS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage. 5.8 (V) V GS(th).6... I = 5 µa Power (W) 3.8.6. - 5-5 5 5 75 5 5-3 - - 6 T J - Temperature ( C) Time (s) Threshold Voltage Single Pulse Power Limited by R S(on)* -rain Current (A) I.... T A = 5 C Single Pulse BVSS Limited ms ms ms s s C V S - rain-to-source Voltage (V) * V GS > minimum V GS at which R S(on) is specified Safe Operating Area, Junction-to-Ambient ocument Number: 73776 S3-97-Rev. C, -Feb-3 THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT /doc?9
Si5C TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) 6 8 I -raincurrent (A) 8 Package Limited Power issipation (W) 6 5 5 75 5 5 T C - Case Temperature ( C) Current erating* 5 5 75 5 5 T C - Case Temperature ( C) Power erating * The power dissipation P is based on T J(max.) = 5 C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. ocument Number: 73776 S3-97-Rev. C, -Feb-3 5 THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT /doc?9
Si5C TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) Normalized Effective Transient Thermal Impedance t uty Cycle =.5. Notes:.. P M.5 t t.. uty Cycle, = t. Per Unit Base = R thja = 8 C/W Single Pulse 3. T JM - T A = P M Z (t) thja. Surface Mounted. - -3 - - 6 Square Wave Pulse uration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance. uty Cycle =.5...5.. - Single Pulse -3 - - Square Wave Pulse uration (s) Normalized Thermal Transient Impedance, Junction-to-Foot maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?73776. 6 ocument Number: 73776 S3-97-Rev. C, -Feb-3 THE PROUCTS ESCRIBE HEREIN AN THIS OCUMENT ARE SUBJECT TO SPECIFIC ISCLAIMERS, SET FORTH AT /doc?9
Package Information 6-8 ChipFET L 8 7 6 5 5 6 7 8 E E 3 3 S e b c x Backside View X./.3 R A C ETAIL X NOTES:. All dimensions are in millimeaters.. Mold gate burrs shall not exceed.3 mm per side. 3. Leadframe to molded body offset is horizontal and vertical shall not exceed.8 mm.. imensions exclusive of mold gate burrs. 5. No mold flash allowed on the top and bottom lead surface. MILLIMETERS INCHES im Min Nom Max Min Nom Max A...39.3 b.5.3.35... c..5...6.8 c.38.5.95 3.5 3..6.. E.85.9.975.7.75.78 E.55.65.7.6.65.67 e.65 BSC.56 BSC L.8...7 S.55 BSC. BSC 5 Nom ECN: C-358 Rev. F, 9-Jan- WG: 557 5 Nom ocument Number: 75 5-Jan-
AN8 Single-Channel 6-8 ChipFET Power MOSFET Recommended Pad Pattern and Thermal Performance INTROUCTION New ChipFETs in the leadless 6-8 package feature the same outline as popular 6-8 resistors and capacitors but provide all the performance of true power semiconductor devices. The 6-8 ChipFET has the same footprint as the body of the LITTLE FOOT TSOP-6, and can be thought of as a leadless TSOP-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much larger SO-8. This technical note discusses the single-channel ChipFET 6-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance. 8 mil 68 mil PIN-OUT Figure shows the pin-out description and Pin identification for the single-channel 6-8 ChipFET device. The pin-out is similar to the TSOP-6 configuration, with two additional drain pins to enhance power dissipation and thermal performance. The legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary. Single 6-8 ChipFET 6 mil 8 mil FIGURE. Footprint With Copper Spreading The pad pattern with copper spreading shown in Figure improves the thermal area of the drain connections (pins,,3,6.7,8) while remaining within the confines of the basic footprint. The drain copper area is.5 sq. in. or 3.5 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. An example of this method is implemented on the Evaluation Board described in the next section (Figure 3). S G THE VISHAY SILICONIX EVALUATION BOAR FOR THE SINGLE 6-8 ocument Number: 76 -ec-3 Bottom View FIGURE. For package dimensions see the 6-8 ChipFET package outline drawing (http:///doc?75). BASIC PA PATTERNS The basic pad layout with dimensions is shown in Application Note 86, Recommended Minimum Pad Patterns With Outline rawing Access for MOSFETs, (http:///doc?786). This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The ChipFET 6-8 evaluation board measures.6 in by.5 in. Its copper pad pattern consists of an increased pad area around the six drain leads on the top-side approximately.8 sq. in. 3. sq. mm and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions. The outer package outline is for the 8-pin IP, which will allow test sockets to be used to assist in testing. The thermal performance of the 6-8 on this board has been measured with the results following on the next page. The testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square FR pcb with copper on both sides of the board.
AN8 Front of Board Back of Board ChipFET vishay.com FIGURE 3. THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the 6-8 ChipFET measured as junction-to-foot thermal resistance is 5 C/W typical, C/W maximum for the single device. The foot is the drain lead of the device as it connects with the body. This is identical to the SO-8 package R jf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. Junction-to-Ambient Thermal Resistance (dependent on pcb size) The typical R ja for the single-channel 6-8 ChipFET is 8 C/W steady state, compared with 68 C/W for the SO-8. Maximum ratings are 95 C/W for the 6-8 versus 8 C/W for the SO-8. The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 5 C/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 33 C/W reduction was obtained by maximizing the copper from the drain on the larger square pcb. Thermal Resistance (C/W) 6 8 Min. Footprint Single EVB Square PCB Testing To aid comparison further, Figure illustrates ChipFET 6-8 thermal performance on two different board sizes and three different pad patterns. The results display the thermal performance out to steady state and produce a graphic account of how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of R ja for the single 6-8 ChipFET are : ) Minimum recommended pad pattern (see Figure ) on the evaluation board size of.5 in x.6 in. ) The evaluation board with the pad pattern described on Figure 3. 3) Industry standard square pcb with maximum copper both sides. 56 C/W C/W 78 C/W -5 SUMMARY - -3 - - Time (Secs) FIGURE. Single 6 8 ChipFET The thermal results for the single-channel 6-8 ChipFET package display similar power dissipation performance to the SO-8 with a footprint reduction of 8%. Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size. ASSOCIATE OCUMENT 6-8 ChipFET ual Thermal performance, AN8 (http:///doc?77). ocument Number: 76 -ec-3
Application Note 86 RECOMMENE MINIMUM PAS FOR 6-8 ChipFET.93 (.357) APPLICATION NOTE. (.559).8 (.3).36 (.9).6 (.65).6 (.6). (.) Recommended Minimum Pads imensions in Inches/(mm) Return to Index Return to Index ocument Number: 7593 Revision: -Jan-8
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