Features 4 Ω Switch Connection between Two Ports Minimal Propagation Delay through the Switch Low I CC Zero Bounce in Flow-through Mode Control Inputs Compatible with TTL Level Description December 2012 The FST3245 switch provides eight-bits of high-speed CMOS TTL-compatible bus switching in a standard 245 pin-out. The low on resistance allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The device is organized as an eight-bit switch. When /OE is LOW, the switch is ON and port A is connected to port B. When /OE is HIGH, the switch is OPEN and a high-impedance state exists between the two ports. Ordering Information Part Number Operating Temperature Range Package Packing Method FST3245MTCX -40 to +85 C 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4 mm Wide Tape and Reel Logic Diagram A 0 2 18 B 0 A 7 9 11 B 7 /OE 19 Figure 1. Logic Diagram 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com FST3245 Rev. 1.0.3
Pin Configuration NC A 0 A 1 A 2 1 2 3 4 20 19 18 17 V CC /OE B 0 B 1 A 3 5 16 B 2 A 4 6 15 B 3 A 5 7 14 B 4 A 6 8 13 B 5 A 7 9 12 B 6 GND 10 11 B 7 Figure 2. Pin Configuration Pin Descriptions Pin # Pin Names Description 1 NC No Connnect 19 /OE Bus Switch Enable 2,3,4,5,6,7,8,9 A 0,A 1,A 2,A 3,A 4,A 5,A 6,A 7 Bus A 10 GND Ground 11,12,13,14,15,16,17,18 B 7,B 6,B 5,B 4,B 3,B 2,B 1,B 0 Bus B 20 V CC Supply Voltage Truth Table Input /OE LOW HIGH Function Connect Disconnect FST3245 Rev. 1.0.3 2
Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V CC Supply Voltage -0.5 7.0 V V S DC Switch Voltage -0.5 7.0 V V IN DC Input Voltage (1) -0.5 7.0 V I IK DC Input Diode Current, V IN < 0 V -50 ma I OUT DC Output Sink Current 128 ma I CC / I GND DC V CC / GND Current ±100 ma T STG Storage Temperature Range -65 +150 C Note: 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V CC Power Supply Operating 4.0 5.5 V V IN Input Voltage 0 5.5 V V OUT Output Voltage 0 5.5 V t r, t f Input Rise and Fall Time Switch Control Input (2) 0 5 Switch I/O 0 DC T A Operating Temperature, Free Air -40 +85 C Note: 2. Unused control inputs must be held HIGH or LOW. They may not float. ns/v FST3245 Rev. 1.0.3 3
DC Electrical Characteristics Typical values are at V CC = 5.0 V and T A = 25 C. Symbol Parameter Conditions V CC (V) T A =-40 to +85 C Min. Typ. Max. V IK Clamp Diode Voltage I IN = -18 ma 4.5-1.2 V V IH High-Level Input Voltage 4.0 to 5.5 2.0 V V IL Low-Level Input Voltage 4.0 to 5.5 0.8 V I IN Input Leakage Current 0 V IN 5.5 V 5.5 ±1.0 µa I OZ Off-state Leakage Current 0 A, B V CC 5.5 ±1.0 µa R ON Switch On Resistance (3) I CC ΔI CC Quiescent Supply Current Increase in I CC per Input V IN = 0 V, I IN = 64 ma 4.5 4 7 V IN = 0 V, I IN = 30 ma 4.5 4 7 V IN = 2.4 V, I IN = 15 ma 4.5 8 15 V IN = 2.4 V, I IN = 15 ma 4.0 11 20 V IN = V CC or GND, I OUT = 0 One Input at 3.4 V, Other Inputs at V CC or GND Units 5.5 3 µa 5.5 2.5 ma Note: 3. Measured by the voltage drop between the A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the A or B pins. Ω AC Electrical Characteristics T A = -40 to +85 C, C L = 50 pf, and R U = R D = 500 Ω. Symbol Parameter Conditions t PHL, t PLH V CC = 4.5 5.5 V V CC = 4.0 V Min. Max. Min. Max. Units Propagation Delay Bus-to-Bus (4) V IN = Open 0.25 0.25 ns Figure Figure 3 Figure 4 t PZH,t PZL Output Enable Time V IN = 7 V for t PZL V IN = Open for t PZH 1.5 5.9 6.4 ns Figure 3 Figure 4 t PHZ, t PLZ Output Disable Time V IN = 7 V for t PLZ V IN = Open for t PHZ 1.5 6.0 5.7 ns Figure 3 Figure 4 Note: 4. This parameter is guaranteed by design, but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical on resistance of the switch and the 50 pf load capacitance when driven by an ideal voltage source (zero output impedance). Capacitance T A = +25 C, f = 1 MHz. Capacitance is characterized, but not tested. Symbol Parameter Conditions Typ. Units C IN Control Pin Input Capacitance V CC = 5.0 V 3 pf C I/O Input/Output Capacitance V CC, /OE = 5.0 V 5 pf FST3245 Rev. 1.0.3 4
AC Loadings and Waveforms Notes: Input driven by 50 Ω source terminated in 50 Ω. C L includes load and stray capacitance. Input PRR = 1.0 MHz, t w = 500 ns. Figure 3. AC Test Circuit Figure 4. AC Waveforms FST3245 Rev. 1.0.3 5
Physical Dimensions Figure 5. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4 mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ FST3245 Rev. 1.0.3 6
FST3245 Rev. 1.0.3 7
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