FEATURES n Wide Input Votage Range: 3V to 8V n Low Quiescent Current: 46 n Low Dropout Votage: 3 n Output Current: 5mA n PWRGD Fag with Programmabe Deay n No Protection Diodes Needed n Adjustabe Output from 1.24V to 6V n 1 Quiescent Current in Shutdown n Stabe with 1μF Output Capacitor n Stabe with Ceramic, Tantaum, and Auminum Capacitors n Reverse-Battery Protection n No Reverse Current Fow from Output to Input n Therma Limiting n Thermay Enhanced 12-Lead MSOP and 1-Pin (3mm 3mm) DFN Packages APPLICATIONS n Low Current High Votage Reguators n Reguator for Battery-Powered Systems n Teecom Appications n Automotive Appications LT311 5mA, 3V to 8V Low Dropout Micropower Linear Reguator with PWRGD DESCRIPTION The LT 311 is a high votage, micropower, ow dropout inear reguator. The device is capabe of suppying 5mA of output current with a dropout votage of 3. Designed for use in battery-powered high votage systems, the ow quiescent current (46 operating and 1 in shutdown) is we controed in dropout, making the LT311 an idea choice. The LT311 incudes a PWRGD fag to indicate output reguation. The deay between reguated output eve and fag indication is programmabe with a singe capacitor. The LT311 aso has the abiity to operate with very sma output capacitors; it is stabe with ony 1μF on the output. Sma ceramic capacitors can be used without the addition of any series resistance (ESR) as is common with other reguators. Interna protection circuitry incudes reversebattery protection, current imiting, therma imiting, and reverse current protection. The LT311 features an adjustabe output with a 1.24V reference votage. The device is avaiabe in the thermay enhanced 12-ead MSOP and the ow profi e (.75mm) 1-pin (3mm 3mm) DFN package, both providing exceent therma characteristics., LT, LTC and LTM are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. TYPICAL APPLICATION 5V Suppy with Shutdown 35 Dropout Votage V IN 3V TO 8V V SHDN <.3V >2.V 1μF OUTPUT OFF ON 1.6M POWER GOOD IN OUT LT311 75k SHDN ADJ PWRGD GND C T 249k 1pF V OUT 5V 5mA 1μF 311 TA1 DROPOUT VOLTAGE () 3 25 2 15 1 5 1 2 3 4 5 OUTPUT CURRENT (ma) 311 TA2 311f 1
LT311 ABSOLUTE MAXIMUM RATINGS IN Pin Votage...±8V OUT Pin Votage...±6V Input-to-Output Differentia Votage...±8V ADJ Pin Votage...±7V SHDN Pin Votage...±8V C T Pin Votage... 7V,.5V PWRGD Pin Votage... 8V,.5V Output Short-Circuit Duration... Indefinite (Note 1) Storage Temperature Range... 65 C to 15 C Operating Junction Temperature (Notes 3, 1, 11) LT311E, LT311I... 4 C to 125 C LT311H... 4 C to 15 C Lead Temperature (Sodering, 1 sec) MSE Package Ony... 3 C PIN CONFIGURATION TOP VIEW TOP VIEW OUT ADJ GND NC PWRGD 1 1 IN 2 3 11 9 8 NC SHDN 4 5 7 6 NC C T NC OUT ADJ GND NC PWRGD 1 2 3 4 5 6 13 12 11 1 9 8 7 NC IN NC SHDN NC C T DD PACKAGE 1-LEAD (3mm 3mm) PLASTIC DFN T JMAX = 15 C, θ JA = 43 C/W, θ JC = 16 C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB MSE PACKAGE 12-LEAD PLASTIC MSOP T JMAX = 15 C, θ JA = 4 C/W, θ JC = 16 C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT311EDD#PBF LT311EDD#TRPBF LDKQ 1-Lead (3mm 3mm) Pastic DFN 4 C to 125 C LT311IDD#PBF LT311IDD#TRPBF LDKQ 1-Lead (3mm 3mm) Pastic DFN 4 C to 125 C LT311EMSE#PBF LT311EMSE#TRPBF 311 12-Lead Pastic MSOP 4 C to 125 C LT311HMSE#PBF LT311HMSE#TRPBF 311 12-Lead Pastic MSOP 4 C to 15 C LT311IMSE#PBF LT311IMSE#TRPBF 311 12-Lead Pastic MSOP 4 C to 125 C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT311EDD LT311EDD#TR LDKQ 1-Lead (3mm 3mm) Pastic DFN 4 C to 125 C LT311IDD LT311IDD#TR LDKQ 1-Lead (3mm 3mm) Pastic DFN 4 C to 125 C LT311EMSE LT311EMSE#TR 311 12-Lead Pastic MSOP 4 C to 125 C LT311HMSE LT311HMSE#TR 311 12-Lead Pastic MSOP 4 C to 15 C LT311IMSE LT311IMSE#TR 311 12-Lead Pastic MSOP 4 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: http://www.inear.com/eadfree/ For more information on tape and ree specifi cations, go to: http://www.inear.com/tapeandree/ 2 311f
LT311 ELECTRICAL CHARACTERISTICS (LT311E, LT311I) The denotes the specifi cations which appy over the 4 C to 125 C operating temperature range, otherwise specifi cations are T J = 25 C. PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Input Votage I LOAD = 5mA 2.8 4 V ADJ Pin Votage (Notes 2, 3) V IN = 3V, I LOAD = 1mA 1.228 1.24 1.252 V 4V < V IN < 8V, 1mA < I LOAD < 5mA 1.215 1.24 1.265 V Line Reguation (Note 2) ΔV IN = 3V to 8V, I LOAD = 1mA 1 12 Load Reguation (Note 2) V IN = 4V, ΔI LOAD = 1mA to 5mA V IN = 4V, ΔI LOAD = 1mA to 5mA 6 15 25 Dropout Votage V IN = V OUT(NOMINAL) (Notes 4, 5) GND Pin Current V IN = V OUT(NOMINAL) (Notes 4, 6) I LOAD = 1mA I LOAD = 1mA I LOAD = 1mA I LOAD = 1mA I LOAD = 5mA I LOAD = 5mA I LOAD = ma I LOAD = 1mA I LOAD = 1mA I LOAD = 5mA 1 15 19 2 26 35 3 37 55 Output Votage Noise C OUT = 1μF, I LOAD = 5mA, BW = 1Hz to 1kHz, V OUT = 1.24V 1 μv RMS ADJ Pin Bias Current (Note 7 ) 3 1 na Shutdown Threshod V OUT = Off to On 1.3 2 V V OUT = On to Off.3 1.1 V SHDN Pin Current (Note 8) V SHDN = V V SHDN = 6V Quiescent Current in Shutdown V IN = 6V, V SHDN = V 1 5 PWRGD Trip Point % of Nomina Output Votage, Output Rising 85 9 94 % PWRGD Trip Point Hysteresis % of Nomina Output Votage 1.1 % PWRGD Output Low Votage I PWRGD = 5 14 25 C T Pin Charging Current 3 6 C T Pin Votage Differentia V CT(PWRGD High) V CT(PWRGD Low) 1.67 V Rippe Rejection V IN = 7V (Avg), V RIPPLE =.5V P-P, f RIPPLE = 12Hz, I LOAD = 5mA 65 85 db Current Limit V IN = 7V, V OUT = V V IN = 4V, ΔV OUT =.1V (Note 2) 6 14 ma ma Input Reverse Leakage Current V IN = 8V, V OUT = V 6 ma Reverse Output Current (Note 9) V OUT = 1.24V, V IN < 1.24V (Note 2) 8 15 46 15 41 1.9.5.1 9 2 7 3.3 2.5 ma ELECTRICAL CHARACTERISTICS (LT311H) The denotes the specifi cations which appy over the 4 C to 15 C operating temperature range, otherwise specifi cations are T J = 25 C. PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Input Votage I LOAD = 5mA 2.8 4 V ADJ Pin Votage (Notes 2, 3) V IN = 3V, I LOAD = 1mA 1.228 1.24 1.252 V 4V < V IN < 8V, 1mA < I LOAD < 5mA 1.215 1.24 1.265 V Line Reguation (Note 2) ΔV IN = 3V to 8V, I LOAD = 1mA 1 12 Load Reguation (Note 2) V IN = 4V, ΔI LOAD = 1mA to 5mA V IN = 4V, ΔI LOAD = 1mA to 5mA 6 15 25 311f 3
LT311 ELECTRICAL CHARACTERISTICS (LT311H) The denotes the specifi cations which appy over the 4 C to 15 C operating temperature range, otherwise specifi cations are at T J = 25 C. PARAMETER CONDITIONS MIN TYP MAX UNITS Dropout Votage V IN = V OUT(NOMINAL) (Notes 4, 5) GND Pin Current V IN = V OUT(NOMINAL) (Notes 4, 6) 4 I LOAD = 1mA I LOAD = 1mA I LOAD = 1mA I LOAD = 1mA I LOAD = 5mA I LOAD = 5mA I LOAD = ma I LOAD = 1mA I LOAD = 1mA I LOAD = 5mA 1 15 22 2 26 38 3 37 575 Output Votage Noise C OUT = 1μF, I LOAD = 5mA, BW = 1Hz to 1kHz, V OUT = 1.24V 1 μv RMS ADJ Pin Bias Current (Note 7) 3 1 na Shutdown Threshod V OUT = Off to On 1.3 2 V V OUT = On to Off.3 1.1 V SHDN Pin Current (Note 8) V SHDN = V V SHDN = 6V Quiescent Current in Shutdown V IN = 6V, V SHDN = V 1 5 PWRGD Trip Point % of Nomina Output Votage, Output Rising 85 9 95 % PWRGD Trip Point Hysteresis % of Nomina Output Votage 1.1 % PWRGD Output Low Votage I PWRGD = 5 14 25 C T Pin Charging Current 3 6 C T Pin Votage Differentia V CT(PWRGD High) V CT(PWRGD Low) 1.67 V Rippe Rejection V IN = 7V (Avg), V RIPPLE =.5V P-P, f RIPPLE = 12Hz, I LOAD = 5mA 65 85 db Current Limit V IN = 7V, V OUT = V V IN = 4V, ΔV OUT =.1V (Note 2) 6 14 ma ma Input Reverse Leakage Current V IN = 8V, V OUT = V 6 ma Reverse Output Current (Note 9) V OUT = 1.24V, V IN < 1.24V (Note 2) 8 15 Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The LT311 is tested and specifi ed for these conditions with the ADJ pin connected to the OUT pin. Note 3: Operating conditions are imited by maximum junction temperature. The reguated output votage specifi cation wi not appy for a possibe combinations of input votage and output current. When operating at maximum input votage, the output current range must be imited. When operating at maximum output current, the input votage range must be imited. Note 4: To satisfy requirements for minimum input votage, the LT311 is tested and specified for these conditions with an externa resistor divider (249k bottom, 49k top) for an output votage of 3.3V. The externa resistor divider wi add a 5 DC oad on the output. Note 5: Dropout votage is the minimum input to output votage differentia needed to maintain reguation at a specifi ed output current. In dropout, the output votage wi be equa to (V IN V DROPOUT ). Note 6: GND pin current is tested with V IN = V OUT(NOMINAL) and a current source oad. This means the device is tested whie operating cose to its 46 15 41 1.9.5.1 125 225 75 3.5 2.5 ma dropout region. This is the worst-case GND pin current. The GND pin current wi decrease sighty at higher input votages. Note 7: ADJ pin bias current f ows into the ADJ pin. Note 8: SHDN pin current f ows out of the SHDN pin. Note 9: Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output votage. This current f ows into the OUT pin and out the GND pin. Note 1: The LT311 reguators are tested and specifi ed under puse oad conditions such that T J T A. The LT311E reguators are 1% tested at T A = 25 C. Performance of the LT311E over the fu 4 C to 125 C operating junction temperature range is assured by design, characterization and correation with statistica process contros. The LT311I reguators are guaranteed over the fu 4 C to 125 C operating junction temperature range. The LT311H is tested to the LT311H Eectrica Characteristics tabe at 15 C operating junction temperature. High junction temperatures degrade operating ifetimes. Operating ifetime is derated at junction temperatures greater than 125 C. Note 11: This IC incudes overtemperature protection that is intended to protect the device during momentary overoad conditions. Junction temperature wi exceed 125 C (LT311E/LT311I) or 15 C (LT311H) when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reiabiity. 311f
TYPICAL PERFORMANCE CHARACTERISTICS T J = 25 C, uness otherwise noted. LT311 DROPOUT VOLTAGE () Dropout Votage Guaranteed Dropout Votage Dropout Votage 4 35 T J 125 C 3 T 25 J 25 C 2 15 1 5 DROPOUT VOLTAGE () 6 = TEST POINTS 5 4 T J 125 C 3 T J 25 C 2 1 DROPOUT VOLTAGE () 4 35 I L = 5mA 3 25 I L = 1mA 2 15 I L = 1mA 1 5 1 2 3 4 5 OUTPUT CURRENT (ma) 311 G1 5 1 15 2 25 3 35 4 45 5 OUTPUT CURRENT (ma) 311 G2 5 25 25 5 75 1 125 15 311 G3 QUIESCENT CURRENT () 8 7 6 5 4 3 2 1 5 Quiescent Current ADJ Pin Votage Quiescent Current V IN = 6V R L = I L = V SHDN = V IN V SHDN = GND 25 25 5 75 1 125 15 311 G4 ADJ PIN VOLTAGE (V) 1.25 1.248 1.246 1.244 1.242 1.24 1.238 1.236 1.234 1.232 1.23 5 I L = 1mA 25 25 5 75 1 125 15 311 G5 QUIESCENT CURRENT () 8 7 6 5 4 3 2 1 T J = 25 C R L = V SHDN = V IN 1 2 3 4 5 6 7 8 9 1 INPUT VOLTAGE (V) 311 G6 GND PIN CURRENT (ma) 2. 1.8 1.6 1.4 1.2 1..8.6.4.2 GND Pin Current GND Pin Current vs I OUT SHDN Pin Threshod R L = 24.8Ω I L = 5mA* R L = 124Ω I L = 1mA* R L = 1.24k, I L = 1mA* 1 2 3 4 5 6 7 8 9 1 INPUT VOLTAGE (V) T J = 25 C *FOR V OUT = 1.24V R L = 49.6Ω I L = 25mA* 311 G7 GND PIN CURRENT (ma) 2. 1.8 1.6 1.4 1.2 1..8.6.4.2 V IN = V OUT(NOMINAL) +1V T J = 25 C 5 1 15 2 25 3 35 4 45 5 OUTPUT CURRENT (ma) 311 G8 SHDN PIN THRESHOLD (V) 1.6 1.4 1.2 1..8.6.4.2 5 25 25 5 75 1 125 15 311 G9 311f 5
LT311 TYPICAL PERFORMANCE CHARACTERISTICS T J = 25 C, uness otherwise noted. SHDN PIN CURRENT ().28.24.2.16.12.8.4 SHDN Pin Current SHDN Pin Current ADJ Pin Bias Current T J = 25 C CURRENT FLOWS OUT OF SHDN PIN SHDN PIN CURRENT ().6.5.4.3.2.1 V SHDN = V CURRENT FLOWS OUT OF SHDN PIN ADJ PIN BIAS CURRENT (na) 12 1 8 6 4 2.5 1 1.5 2 2.5 3 3.5 4 4.5 5 SHDN PIN VOLTAGE (V) 311 G1 5 25 25 5 75 1 125 15 311 G11 5 25 25 5 75 1 125 15 311 G12 PWRGD TRIP POINT (% OF OUTPUT VOLTAGE) 95 94 93 92 91 9 89 88 87 86 85 5 PWRGD Trip Point PWRGD Output Low Votage C T Charging Current OUTPUT FALLING OUTPUT RISING 25 25 5 75 1 125 15 311 G13 PWRGD OUTPUT LOW VOLTAGE () 2 18 16 14 12 1 8 6 4 2 5 I PWRGD = 5 25 25 5 75 1 125 15 311 G14 C T CHARGING CURRENT () 4. 3.5 3. 2.5 2. 1.5 1..5 5 PWRGD TRIPPED HIGH 25 25 5 75 1 125 15 311 G15 C T COMPARATOR THRESHOLD (V) 2. 1.8 1.6 1.4 1.2 1..8.6.4.2 5 C T Comparator Threshod Current Limit Current Limit V CT(HIGH) V CT(LOW) 25 25 5 75 1 125 15 311 G16 CURRENT LIMIT (ma) 18 16 14 12 1 8 6 4 2 V OUT = V T J = 25 C 1 2 3 4 5 6 7 8 9 1 INPUT VOLTAGE (V) 311 G17 CURRENT LIMIT (ma) 2 18 16 14 12 1 8 6 4 2 V IN = 7V V OUT = V 5 25 25 5 75 1 125 15 311 G18 6 311f
TYPICAL PERFORMANCE CHARACTERISTICS T J = 25 C, uness otherwise noted. LT311 REVERSE OUTPUT CURRENT () 16 14 12 1 8 Reverse Output Current Reverse Output Current Input Rippe Rejection ADJ PIN CLAMP (SEE APPLICATIONS INFORMATION) 6 T J = 25 C 4 V IN = V CURRENT FLOWS 2 INTO OUTPUT PIN V OUT = V ADJ 1 2 3 4 5 6 7 8 9 1 OUTPUT VOLTAGE (V) 311 G19 REVERSE OUTPUT CURRENT () 8 7 6 5 4 3 2 1 V IN = V V OUT = V ADJ = 1.24V 5 25 25 5 75 1 125 15 311 G2 RIPPLE REJECTION (db) 9 88 86 84 82 8 78 76 74 72 7 5 V IN = 7V +.5V P-P RIPPLE AT f = 12Hz I L = 5mA V OUT = 1.24V 25 25 5 75 1 125 15 311 G21 RIPPLE REJECTION (db) 1 9 8 7 6 5 4 3 2 1 Input Rippe Rejection Minimum Input Votage Load Reguation V IN = 7V + 5 RMS RIPPLE I L = 5mA, V OUT = 1.24V C OUT = 1μF CERAMIC C OUT = 1μF CERAMIC 1 1 1k 1k 1k 1M FREQUENCY (Hz) 311 G22 MINIMUM INPUT VOLTAGE (V) 4. 3.5 3. 2.5 2. 1.5 1..5 I L = 5mA 5 25 25 5 75 1 125 15 311 G23 LOAD REGULATION () 2 4 6 8 1 ΔI L = 1mA TO 5mA V OUT = 1.24V 12 5 25 25 5 75 1 125 15 311 G24 OUTPUT NOISE SPECTRAL DENSITY (μv/ Hz) 1 1.1.1.1 1 Output Noise Spectra Density Output Noise (1Hz to 1kHz) Transient Response V OUT = 1.24V C OUT = 1μF I L = 5mA 1 1k 1k 1k FREQUENCY (Hz) 311 G25 V OUT 1μV/DIV V OUT = 1.24V C OUT = 1μF I L = 5mA WORST-CASE NOISE 1ms/DIV 311 G26 OUTPUT VOLTAGE DEVIATION (V) LOAD CURRENT (ma).3.2.1.1.2 V IN = 6V 5 V OUT SET FOR 5V C IN = 1μF CERAMIC 25 C OUT = 1μF CERAMIC ΔI LOAD = 1mA TO 5mA 1 2 3 4 5 6 7 8 9 1 TIME (μs) 311 G27 311f 7
LT311 PIN FUNCTIONS (DFN/MSOP) OUT (Pin 1/Pin 2): Output. The output suppies power to the oad. A minimum output capacitor of 1μF is required to prevent osciations. Larger capacitors wi be required for appications with arge transient oads to imit peak votage transients. See the Appications Information section for more information on output capacitance and reverse output characteristics. ADJ (Pin 2/Pin 3): Adjust. This is the input to the error ampifi er. This pin is internay camped to ±7V. It has a bias current of 3nA which fows into the pin (see the curve abeed ADJ Pin Bias Current vs Temperature in the Typica Performance Characteristics section). The ADJ pin votage is 1.24V referenced to ground, and the output votage range is 1.24V to 6V. GND (Pins 3, 11/Pins 4, 13): Ground. The exposed backside of the package (Pin 11/Pin 13) is an eectrica connection for GND. As such, to ensure optimum device operation and therma performance, the Exposed Pad must be connected directy to Pin 3/Pin 4 on the PC board. NC (Pins 4, 7, 9/Pins 1, 5, 8, 1, 12): No Connection. These pins have no interna connection. Connecting NC pins to a copper area for heat dissipation provides a sma improvement in therma performance. PWRGD (Pin 5/Pin 6): Power Good. The PWRGD fag is an open-coector fag to indicate that the output votage has increased above 9% of the nomina output votage. There is no interna pu-up on this pin; a pu-up resistor must be used. The PWRGD pin wi change state from an open-coector pu-down to high impedance after both the output is above 9% of the nomina votage and the capacitor on the C T pin has charged through a 1.67V differentia. The maximum pu-down current of the PWRGD pin in the ow state is 5. C T (Pin 6/Pin 7): Timing Capacitor. The C T pin aows the use of a sma capacitor to deay the timing between the point where the output crosses the PWRGD threshod and the PWRGD fag changes to a high impedance state. Current out of this pin during the charging phase is 3. The votage difference between the PWRGD ow and PWRGD high states is 1.67V (see the Appications Information section). SHDN (Pin 8/Pin 9): Shutdown. The SHDN pin is used to put the LT311 into a ow power shutdown state. The output wi be off when the SHDN pin is pued ow. The SHDN pin can be driven either by 5V ogic or open-coector ogic with a pu-up resistor. The pu-up resistor is ony required to suppy the pu-up current of the open-coector gate, normay severa microamperes. If unused, the SHDN pin must be tied to a ogic high or V IN. IN (Pin 1/Pin 11): Input. Power is suppied to the device through the IN pin. A bypass capacitor is required on this pin if the device is more than six inches away from the main input fiter capacitor. In genera, the output impedance of a battery rises with frequency, so it is advisabe to incude a bypass capacitor in battery-powered circuits. A bypass capacitor in the range of 1μF to 1μF is sufficient. The LT311 is designed to withstand reverse votages on the IN pin with respect to ground and the OUT pin. In the case of a reverse input votage, which can occur if a battery is pugged in backwards, the LT311 wi act as if there is a diode in series with its input. There wi be no reverse current fow into the LT311 and no reverse votage wi appear at the oad. The device wi protect both itsef and the oad. Exposed Pad (Pin 11/Pin 13): Ground. The Exposed Pad must be sodered to the PCB. 8 311f
APPLICATIONS INFORMATION The LT311 is a 5mA high votage/ow dropout reguator with micropower quiescent current and shutdown. The device is capabe of suppying 5mA at a dropout votage of 3. The ow operating quiescent current (46) drops to 1 in shutdown. In addition to ow quiescent current, the LT311 incorporates severa protection features which make it idea for use in battery-powered systems. The device is protected against both reverse input and reverse output votages. In battery backup appications where the output can be hed up by a backup battery when the input is pued to ground, the LT311 acts ike it has a diode in series with its output and prevents reverse current fow. LT311 Adjustabe Operation The LT311 has an output votage range of 1.24V to 6V. The output votage is set by the ratio of two externa resistors as shown in Figure 1. The device servos the output to maintain the votage at the adjust pin at 1.24V referenced to ground. The current in R1 is then equa to 1.24V/R1 and the current in R2 is the current in R1 pus the ADJ pin bias current. The ADJ pin bias current, 3nA at 25 C, fows through R2 into the ADJ pin. The output votage can be cacuated using the formua in Figure 1. The vaue of R1 shoud be ess than 25k to minimize errors in the output votage caused by the ADJ pin bias current. Note that in shutdown the output is turned off and the divider current wi be zero. The adjustabe device is tested and specified with the ADJ pin tied to the OUT pin and a 5 DC oad (uness otherwise specifi ed) for an output votage of 1.24V. Specifications for output votages greater than 1.24V wi be proportiona to the ratio of the desired output votage to 1.24V; (V OUT /1.24V). For exampe, oad reguation for an output current change of 1mA to 5mA is 6 (typica) at V OUT = 1.24V. At V OUT = 12V, oad reguation is: 12V 6 = 58 124. V Output Capacitance and Transient Response The LT311 is designed to be stabe with a wide range of output capacitors. The ESR of the output capacitor affects stabiity, most notaby with sma capacitors. A minimum output capacitor of 1μF with an ESR of 3Ω or ess is recommended to prevent osciations. The LT311 is a micropower device and output transient response wi be a function of output capacitance. Larger vaues of output capacitance decrease the peak deviations and provide improved transient response for arger oad current changes. Bypass capacitors, used to decoupe individua components powered by the LT311, wi increase the effective output capacitor vaue. Extra consideration must be given to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dieectrics, each with different behavior across temperature and appied votage. The most common dieectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dieectrics are good for providing high capacitances V R2 OUT = V ADJ 1 + + (I ADJ )(R2) R1 V ADJ = 1.24V I ADJ = 3nA AT 25 C OUTPUT RANGE = 1.24V TO 6V V IN IN OUT LT311 ADJ GND R2 R1 + V OUT 311 F1 Figure 1. Adjustabe Operation 311f 9
LT311 APPLICATIONS INFORMATION in a sma package, but they tend to have strong votage and temperature coefficients, as shown in Figures 2 and 3. When used with a 5V reguator, a 16V 1μF Y5V capacitor can exhibit an effective vaue as ow as 1μF to 2μF for the DC bias votage appied and over the operating temperature range. The X5R and X7R dieectrics resut in more stabe characteristics and are more suitabe for use as the output capacitor. The X7R type has better stabiity across temperature, whie the X5R is ess expensive and is avaiabe in higher vaues. Care sti must be exercised when using X5R and X7R capacitors; the X5R and X7R codes ony specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can sti be significant enough to drop capacitor vaues beow appropriate eves. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating votage shoud be verifi ed. Votage and temperature coefficients are not the ony sources of probems. Some ceramic capacitors have a piezoeectric response. A piezoeectric device generates votage across its terminas due to mechanica stress, simiar to the way piezoeectric acceerometer or microphone works. For a ceramic capacitor, the stress can be induced by vibrations in the system or therma transients. PWRGD Fag and Timing Capacitor Deay The PWRGD fag is used to indicate that the ADJ pin votage is within 1% of the reguated votage. The PWRGD pin is an open-coector output, capabe of sinking 5 of current when the ADJ pin votage is ow. There is no interna pu-up on the PWRGD pin; an externa pu-up resistor must be used. When the ADJ pin rises to within 1% of its fina reference vaue, a deay timer is started. At the end of this deay, programmed by the vaue of the capacitor on the C T pin, the PWRGD pin switches to a high impedance and is pued up to a ogic eve by an externa pu-up resistor. To cacuate the capacitor vaue on the C T pin, use the foowing formua: ICT tdelay CTIME = V V CT( HIGH) CT( LOW) Figure 4 shows a bock diagram of the PWRGD circuit. At start-up, the timing capacitor is discharged and the PWRGD pin wi be hed ow. As the output votage increases and the ADJ pin crosses the 9% threshod, the JK f ipfop is reset, and the 3 current source begins to charge the timing capacitor. Once the votage on the C T pin reaches the V CT(HIGH) threshod (approximatey 1.7V at 25 C), the capacitor votage is camped and the PWRGD pin is set to a high impedance state. CHANGE IN VALUE (%) 2 2 4 6 8 BOTH CAPACITORS ARE 16V, 121 CASE SIZE, 1 F X5R Y5V 1 2 4 6 8 1 12 14 DC BIAS VOLTAGE (V) 311 F2 Figure 2. Ceramic Capacitor DC Bias Characteristics 16 CHANGE IN VALUE (%) 4 2 2 4 6 X5R Y5V 8 BOTH CAPACITORS ARE 16V, 121 CASE SIZE, 1 F 1 5 25 25 5 75 1 125 TEMPERATURE ( C) 311 F3 Figure 3. Ceramic Capacitor Temperature Characteristics 1 311f
LT311 APPLICATIONS INFORMATION During norma operation, an interna gitch fiter wi ignore short transients (<15μs). Longer transients beow the 9% threshod wi reset the JK fip-f op. This f ip-f op ensures that the capacitor on the C T pin is quicky discharged a the way to the V CT(LOW) threshod before restarting the time deay. This provides a consistent time deay after the ADJ pin is within 1% of the reguated votage before the PWRGD pin switches to high impedance. Therma Considerations The power handing capabiity of the device wi be imited by the maximum rated junction temperature (125 C, LT311E/ LT311I or 15 C, LT311H). The power dissipated by the device wi be made up of two components: 1. Output current mutipied by the input/output votage differentia: I OUT (V IN V OUT ) and, 2. GND pin current mutipied by the input votage: I GND V IN The GND pin current is found by examining the GND pin current curves in the Typica Performance Characteristics section. Power dissipation wi be equa to the sum of the two components isted above. The LT311 series reguators have interna therma imiting designed to protect the device during overoad conditions. For continuous norma conditions, the maximum junction temperature rating of 125 C (LT311E/ LT311I) or 15 C (LT311H) must not be exceeded. It is important to give carefu consideration to a sources of therma resistance from junction to ambient. Additiona heat sources mounted nearby must aso be considered. ADJ V REF 9% + J K Q I CT 3 + C T V CT(LOW).1V V CT(HIGH) V BE ( 1.1V) PWRGD 311 F4 For surface mount devices, heat sinking is accompished by using the heat spreading capabiities of the PC board and its copper traces. Copper board stiffeners and pated through-hoes can aso be used to spread the heat generated by power devices. The foowing tabe ists therma resistance for severa different board sizes and copper areas. A measurements were taken in sti air on 3/32" FR-4 board with one ounce copper. Tabe 1. MSOP Measured Therma Resistance COPPER AREA THERMAL RESISTANCE TOPSIDE BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT) 25 sq mm 25 sq mm 25 sq mm 52 C/W 1 sq mm 25 sq mm 25 sq mm 54 C/W 225 sq mm 25 sq mm 25 sq mm 58 C/W 1 sq mm 25 sq mm 25 sq mm 64 C/W Tabe 2. DFN Measured Therma Resistance COPPER AREA THERMAL RESISTANCE TOPSIDE BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT) 25 sq mm 25 sq mm 25 sq mm 52 C/W 1 sq mm 25 sq mm 25 sq mm 54 C/W 225 sq mm 25 sq mm 25 sq mm 58 C/W 1 sq mm 25 sq mm 25 sq mm 64 C/W The therma resistance junction-to-case (θ JC ), measured at the Exposed Pad on the back of the die, is 16 C/W. Continuous operation at arge input/output votage differentias and maximum oad current is not practica due to therma imitations. Transient operation at high input/ output differentias is possibe. The approximate therma time-constant for a 25sq mm 3/32" FR-4 board, with maximum topside and backside area for one ounce copper, is three seconds. This time-constant wi increase as more therma mass is added (i.e., vias, arger board and other components). For an appication with transient high power peaks, average power dissipation can be used for junction temperature cacuations as ong as the puse period is significanty ess than the therma time constant of the device and board. Figure 4. PWRGD Circuit Bock Diagram 311f 11
LT311 APPLICATIONS INFORMATION Cacuating Junction Temperature Exampe 1: Given an output votage of 5V, an input votage range of 24V to 3V, an output current range of ma to 5mA, and a maximum ambient temperature of 5 C, what wi the maximum junction temperature be? The power dissipated by the device wi be equa to: I OUT(MAX) (V IN(MAX) V OUT ) + (I GND V IN(MAX) ) Where: I OUT(MAX) = 5mA V IN(MAX) = 3V I GND at (I OUT = 5mA, V IN = 3V) = 1mA So: P = 5mA (3V 5V) + (1mA 3V) = 1.28W The therma resistance wi be in the range of 52 C/W to 64 C/W depending on the copper area. So, the junction temperature rise above ambient wi be approximatey equa to: 1.28W 58 C/W = 74 C The maximum junction temperature wi then be equa to the maximum junction temperature rise above ambient pus the maximum ambient temperature or: T JMAX = 5 C + 74 C = 124 C Exampe 2: Given an output votage of 5V, an input votage of 48V that rises to 72V for 5ms (max) out of every 1ms, and a 5mA oad that steps to 5mA for 5ms out of every 25ms, what is the junction temperature rise above ambient? Using a 5ms period (we under the time-constant of the board), power dissipation is as foow: P1 (48V IN, 5mA oad) = 5mA (48V 5V) + (2 48V) =.23W P2 (48V IN, 5mA oad) = 5mA (48V 5V) + (1mA 48V) = 2.2W P3 (72V IN, 5mA oad) = 5mA (72V 5V) + (2 72V) =.35W P1 (72V IN, 5mA oad) = 5mA (72V 5V) + (1mA 72V) = 3.42W 12 Operation at the different power eves is as foows: 76% operation at P1, 19% for P2, 4% for P3, and 1% for P4. P EFF = 76%(.23W) + 19%(2.2W) + 4%(.35W) + 1%(3.42W) =.64W With a therma resistance in the range of 52 C/W to 64 C/W, this transates to a junction temperature rise above ambient of 33 C to 41 C. High Temperature Operation Care must be taken when designing LT311 appications to operate at high ambient temperatures. The LT311 works at eevated temperatures but erratic operation can occur due to unforeseen variations in externa components. Some tantaum capacitors are avaiabe for high temperature operation, but ESR is often severa ohms; capacitor ESR above 3Ω is unsuitabe for use with the LT311. Ceramic capacitor manufacturers (Murata, AVX, TDK and Vishay Vitramon at this writing) now offer ceramic capacitors that are rated to 15 C using an X8R dieectric. Device instabiity wi occur if the output capacitor vaue and ESR are outside design imits at eevated temperature and operating DC votage bias (see information on capacitor characteristics under Output Capacitance and Transient Response). Check each passive component for absoute vaue and votage ratings over the operating temperature range. Leakage in capacitors, or from soder fux eft after insufficient board ceaning, adversey affects the ow quiescent current operation. Consider junction temperature increase due to power dissipation in both the junction and nearby components to ensure maximum specifi cations are not vioated for the LT311E/LT311H/LT311I or externa components. Protection Features The LT311 incorporates severa protection features which make it idea for use in battery-powered circuits. In addition to the norma protection features associated with monoithic reguators, such as current imiting and therma imiting, the device is protected against reverse-input votages, and reverse votages from output-to-input. 311f
LT311 APPLICATIONS INFORMATION Current imit protection and therma overoad protection are intended to protect the device against current overoad conditions at the output of the device. For norma operation, the junction temperature shoud not exceed 125 C (LT311E/LT311I) or 15 C (LT311H). The input of the device wi withstand reverse votages of 8V. Current f ow into the device wi be imited to ess than 6mA (typicay ess than 1) and no negative votage wi appear at the output. The device wi protect both itsef and the oad. This provides protection against batteries which can be pugged in backwards. The ADJ pin of the adjustabe device can be pued above or beow ground by as much as 7V without damaging the device. If the input is eft open-circuit or grounded, the ADJ pin wi act ike an open-circuit when pued beow ground, and ike a arge resistor (typicay 1k) in series with a diode when pued above ground. If the input is powered by a votage source, puing the ADJ pin beow the reference votage wi cause the device to try and force the current imit out of the output. This wi cause the output to go to an unreguated high votage. Puing the ADJ pin above the reference votage wi turn off a output current. In situations where the ADJ pin is connected to a resistor divider that woud pu the ADJ pin above its 7V camp votage if the output is pued high, the ADJ pin input current must be imited to ess than 5mA. For exampe, a resistor divider is used to provide a reguated 1.5V output from the 1.24V reference when the output is forced to 6V. The top resistor of the resistor divider must be chosen to imit the current into the ADJ pin to ess than 5mA when the ADJ pin is at 7V. The 53V difference between the OUT and ADJ pin is divided by the 5mA maximum current into the ADJ pin yieds a minimum top resistor vaue of 1.6k. In circuits where a backup battery is required, severa different input/output conditions can occur. The output votage may be hed up whie the input is either pued to ground, pued to some intermediate votage, or is eft open-circuit. Current fow back into the output wi foow the curve shown in Figure 5. The rise in reverse output current above 7V occurs from the breakdown of the 7V camp on the ADJ pin. With a resistor divider on the reguator output, this current wi be reduced depending on the size of the resistor divider. When the IN pin of the LT311 is forced beow the OUT pin or the OUT pin is pued above the IN pin, input current wi typicay drop to ess than 2. This can happen if the input of the LT311 is connected to a discharged (ow votage) battery and the output is hed up by either a backup battery or a second reguator circuit. The state of the SHDN pin wi have no effect on the reverse output current when the output is pued above the input. 16 REVERSE OUTPUT CURRENT () 14 12 1 8 ADJ PIN CLAMP (SEE ABOVE) 6 T J = 25 C 4 V IN = V CURRENT FLOWS 2 INTO OUTPUT PIN V OUT = V ADJ 1 2 3 4 5 6 7 8 9 1 OUTPUT VOLTAGE (V) 311 F5 Figure 5. Reverse Output Current 311f 13
LT311 TYPICAL APPLICATIONS 5V Buck Converter with Low Current Keep Aive Backup V IN 5.5V* TO 6V C3 4.7 F 1V CERAMIC 4 15 14 V IN SHDN SYNC GND 6 BOOST LT1766 1, 8, 9, 16 SW BIAS FB V C 2 1 12 11 C C 1nF C2.33 F D1 1MQ6N R1 15.4k R2 4.99k D2 D1N914 L1 15 H C1 1 F 1V SOLID TANTALUM + V OUT 5V 1A/25mA EFFICIENCY (%) 1 9 8 7 6 Buck Converter Effi ciency vs Load Current V OUT = 5V L = 68 H V IN = 1V V IN = 42V OPERATING CURRENT LOW HIGH 1k 1 8 5 IN SHDN OUT LT311 ADJ PWRGD GND C T 3, 11 6 1pF 1 2 75k 249k 311 TA3 * FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY INCREASE L1 TO 3 H FOR LOAD CURRENTS ABOVE.6A AND TO 6 H ABOVE 1A. LT311 PIN NUMBERS ARE FOR THE DD PACKAGE. 5.25.5.75 1. 1.25 LOAD CURRENT (A) 311 TA4 LT311 Automotive Appication V IN 12V (FUTURE 42V) + 1 F NO PROTECTION DIODE NEEDED! IN OUT LT311 SHDN ADJ GND 75k 249k 1 F LOAD: CLOCK, SECURITY SYSTEM ETC OFF ON LT311 Teecom Appication V IN 48V (72V TRANSIENT) 1 F IN OUT LT311 SHDN ADJ GND 75k 249k NO PROTECTION DIODE NEEDED! 1 F LOAD: SYSTEM MONITOR ETC + BACKUP BATTERY OFF ON 311 TA5 14 311f
LT311 PACKAGE DESCRIPTION DD Package 1-Lead Pastic DFN (3mm 3mm) (Reference LTC DWG # 5-8-1699).675 ±.5 R =.115 TYP 6 1.38 ±.1 3.5 ±.5 2.15 ±.5 1.65 ±.5 (2 SIDES) PACKAGE OUTLINE.25 ±.5.5 BSC 2.38 ±.5 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 TOP MARK (SEE NOTE 6) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS.2 REF 3. ±.1 (4 SIDES).75 ±.5..5 1.65 ±.1 (2 SIDES) 2.38 ±.1 (2 SIDES) 1.25 ±.5.5 BSC BOTTOM VIEW EXPOSED PAD 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 5 (DD) DFN 113 MSE Package 12-Lead Pastic MSOP, Exposed Die Pad (Reference LTC DWG # 5-8-1666 Rev B) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845.12 (.112.4).889.127 (.35.5) 2.845.12 (.112.4) 1 6.35 REF 5.23 (.26) MIN GAUGE PLANE.254 (.1) 1.651.12 (.65.4).42.38.65 (.165.15) (.256) TYP BSC RECOMMENDED SOLDER PAD LAYOUT DETAIL A 6 TYP 3.2 3.45 (.126.136) 4.9.152 (.193.6) 12 4.39.12 (.159.4) (NOTE 3) 12 11 1 9 8 7 7 DETAIL B.46.76 (.16.3) REF 3..12 (.118.4) (NOTE 4).12 REF DETAIL B CORNER TAIL IS PART OF THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE.18 (.7) DETAIL A.53.152 (.21.6) 1.1 (.43) MAX 1 2 3 4 5 6.86 (.34) REF NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE SEATING PLANE.22.38 (.9.15) TYP.65 (.256) BSC 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED.152mm (.6") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED.152mm (.6") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.12mm (.4") MAX.116.58 (.4.2) MSOP (MSE12) 68 REV B Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 311f 15
LT311 TYPICAL APPLICATION Constant Brightness for Indicator LED over Wide Input Votage Range 48V CAN VARY FROM 4V TO 8V RETURN OFF ON 1 F 48V I LED = 1.24V/R SET IN OUT LT311 SHDN ADJ GND R SET 311 TA6 1 F RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1121/ LT1121HV LT1676 16 15mA, Micropower, LDO 6V, 44mA (I OUT ), 1kHz, High Efficiency Step-Down DC/DC Converter V IN : 4.2V to 3V/36V, V OUT(MIN) = 3.75V, V DO =.42V, I Q = 3, I SD = 16, Reverse Battery Protection, SOT-223, S8 and Z Packages V IN : 7.4V to 6V, V OUT(MIN) = 1.24V, I Q = 3.2mA, I SD = 2.5, S8 Package LT1761 1mA, Low Noise Micropower, LDO V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.3V, I Q = 2, I SD <1, Low Noise < 2μV RMS, Stabe with 1μF Ceramic Capacitors, ThinSOT TM Package LT1762 15mA, Low Noise Micropower, LDO V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.3V, I Q = 25, I SD <1, Low Noise < 2μV RMS, MS8 Package LT1763 5mA, Low Noise Micropower, LDO V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.3V, I Q = 3, I SD <1, Low Noise < 2μV RMS, S8 Package LT1764/ LT1764A 3A, Low Noise, Fast Transient Response, LDO V IN : 2.7V to 2V, V OUT(MIN) = 1.21V, V DO =.34V, I Q = 1mA, I SD <1, Low Noise < 4μV RMS, A Version Stabe with Ceramic Capacitors, DD and TO22-5 Packages LT1766 6V, 1.2A (I OUT ), 2kHz, High Effi ciency V IN : 5.5V to 6V, V OUT(MIN) = 1.2V, I Q = 2.5mA, I SD = 25, TSSOP-16/E Package Step-Down DC/DC Converter LT1776 4V, 55mA (I OUT ), 2kHz, High V IN : 7.4V to 4V, V OUT(MIN) = 1.24V, I Q = 3.2mA, I SD = 3, N8 and S8 Packages Efficiency Step-Down DC/DC Converter LT1956 6V, 1.2A (I OUT ), 5kHz, High Effi ciency V IN : 5.5V to 6V, V OUT(MIN) = 1.2V, I Q = 2.5mA, I SD = 25, TSSOP-16/E Package Step-Down DC/DC Converter LT1962 3mA, Low Noise Micropower, LDO V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.27V, I Q = 3, I SD <1, Low Noise < 2μV RMS, MS8 Package LT1963/ LT1963A LT1965 1.5A, Low Noise, Fast Transient Response, LDO 1.1A, Low Noise, Low Dropout Linear Reguator V IN : 2.1V to 2V, V OUT(MIN) = 1.21V, V DO =.34V, I Q = 1mA, I SD <1, Low Noise < 4μV RMS, A Version Stabe with Ceramic Capacitors, DD, TO22-5, ST-223 and S8 Packages 31 Dropout Votage, Low Noise = 4μV RMS, V IN : 1.8V to 2V, V OUT : 1.2V to 19.5V, Stabe with Ceramic Capacitors, TO-22, DDPak, MSOP and 3mm 3mm DFN Packages LT39 2mA, 3 I Q Micropower LDO 28 Dropout Votage, Low I Q = 3, V IN : 1.6V to 2V, ThinSOT and SC-7 Packages LT31/ LT31H LT312/ LT312H LT313/ LT313H LT314/HV LT38/ LT38-1 5mA, 3V to 8V, Low Noise Micropower LDO 25mA, 4V to 8V, Low Dropout Micropower Linear Reguator 25mA, 4V to 8V, Low Dropout Micropower Linear Reguator 2mA, 3V to 8V, Low Dropout Micropower Linear Reguator 1.1A, Paraeabe, Low Noise, Low Dropout Linear Reguator ThinSOT is a trademark of Linear Technoogy Corporation. V IN : 3V to 8V, V OUT(MIN) = 1.275V, V DO =.3V, I Q = 3, I SD = 1, Low Noise < 1μV RMS, MS8E Package, H Grade = +14 C T JMAX V IN : 4V to 8V, V OUT : 1.24V to 6V, V DO =.4V, I Q = 4, I SD <1, TSSOP-16E and 4mm 3mm DFN-12 Packages, H Grade = +14 C T JMAX V IN : 4V to 8V, V OUT : 1.24V to 6V, V DO =.4V, I Q = 65, I SD <1, TSSOP-16E and 4mm 3mm DFN-12 Packages, H Grade = +14 C T JMAX, PWRGD Fag V IN : 3V to 8V (1V for 2ms, HV Version), V OUT : 1.22V to 6V, V DO =.35V, I Q = 7, I SD <1, ThinSOT and 3mm 3mm DFN-8 Packages 3 Dropout Votage (2-Suppy Operation), Low Noise = 4μV RMS, V IN : 1.2V to 36V, V OUT : V to 35.7V, Current-Based Reference with One Resistor V OUT Set; Directy Paraeabe (No Op Amp Required), Stabe with Ceramic Capacitors, TO-22, SOT-223, MSOP and 3mm 3mm DFN Packages; LT38-1 Features an Integrated Baast Resistor LT 88 PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA 9535-7417 (48) 432-19 FAX: (48) 434-57 www.inear.com LINEAR TECHNOLOGY CORPORATION 28 311f