Working with ADCs, OAs and the MSP430 Bonnie Baker HPA Senior Applications Engineer Texas Instruments 2006 Texas Instruments Inc, Slide 1 Agenda An Overview of the MSP430 Data Acquisition System SAR Converters The INS and OUTS of the SAR converter Useful Applications Using Op Amps Op Amp Configurations Driving SAR Converters 2006 Texas Instruments Inc, Slide 2 1
Where to Find ADCs and Op Amps OP OP AMP MUX FILTER Voltage Reference Source A/D REF Sensor Interface Voltage Reference Source Buffer Gain Difference Amplifier Instrumentation Amplifier Filter Level Shift Anti-Alias Filter Band-pass Filter Programmable Gain Amp Instrumentation Amp A/D Converter Driver Voltage Reference Source DDS Synthesis μ C Valve Actuator Driver Line Driver 4-20mA Driver POWER AMP D/A 2006 Texas Instruments Inc, Slide 3 ADC Architectures There are many different ADC Architectures Successive Approximation (SAR) Sigma Delta (SD) Slope or Dual Slope Pipeline Flash...as in quick, not memory All converters in the MSP430 chips are SAR and Sigma Delta types SAR determines the digital word By approximating the input signal Using an iterative process How the Sigma Delta converter determines the digital word By oversampling Applying Digital Filtering 2006 Texas Instruments Inc, Slide 4 2
Op Amp Architectures The Different Types Op Amp Architectures Single Supply Rail to Rail In Rail to Rail Out CMOS or Bipolar Dual Supply All Op Amps (OAs) in the MSP430 chips are Single Supply, CMOS Our CMOS Op amp Easily Configured with the MSP430 Controller General Purpose, Buffer, Comparator, PGA, Differential Amp Easily Programmed for Optimized Gain Bandwidth etc 2006 Texas Instruments Inc, Slide 5 Agenda An Overview of the MSP430 Data Acquisition System SAR Converters The INS and OUTS of the SAR converter Useful Applications Using Op Amps Op Amp Configurations Driving SAR Converters 2006 Texas Instruments Inc, Slide 6 3
The SAR ADC Most Serial ADCs are SARs or Sigma Deltas The MSP439 SAR Converter SAR ADC = Successive Approximation Register, Analog-to-Digital Converter ADC12 12-bit Analog-to-Digital Converter SARs are Best for General Purpose Apps Very Prevalent for Signal Level Applications: Data Loggers, Temp Sensors, Bridge Sensors, General Purpose In the Market SARs Can be 8 to 18 bits of resolution Speed range: >10 ksps to < 5 Msps SAR Analog to Digital Converter Usually require a Low-pass Filter before Analog Input 2006 Texas Instruments Inc, Slide 7 System Integration Using an A/D MSP430 Input Signal Source Amp Filter Analog SAR to Digital Analog to Converter Digital Converter Micro- Controller Engine Output Filter DAC or PWM 2006 Texas Instruments Inc, Slide 8 4
SAR Converter Block Diagram V S S 1 R IN (2 kω) Cap array is both the sample cap and a DAC 16C 2C C C S C _ Shift Register S A R 1/2 V REF Control Logic V SS V REF 2006 Texas Instruments Inc, Slide 9 Successive Approximation Concept FS 3/4FS 1/2FS Bit = 1 TEST MSB Bit = 0 TEST MSB -1 Bit = 1 TEST MSB -2 Bit = 0 TEST LSB Analog input 1/4FS 0 DAC Output Time Digital Output Code = 1010 2006 Texas Instruments Inc, Slide 10 5
ADC Ideal Transfer Function 111 110 Digital Output Code 101 100 011 010 Ideal transfer function 001 000 0 1/4 FS 1/2 FS 3/4 FS Analog Input Voltage FS 2006 Texas Instruments Inc, Slide 11 ADC with Offset and Gain Error Digital Output Code 111 110 101 100 011 010 Actual transfer function Ideal transfer function y = a (1b)x where y=digital out x=analog in a=offset err b=gain err Every Ideal Code has Offset Error added Every ideal code is Multiplied by Gain Error 001 000 0 1/4 FS 1/2 FS 3/4 FS Analog Input Voltage FS 2006 Texas Instruments Inc, Slide 12 6
Offset/Gain Impact on Dynamic Range 4096 Digital Code OUT Analog Voltage IN Worse case Dynamic Range = 4082 bits = 11.995 bits V REF Gain Error Offset Error ADC12 specifications Offset E O typ = ±2 LSB E O max = ±4 LSB Gain E G typ = ±1.1 LSB E G max = ±2 LSB (= ±0.0488%) 1 LSB = (V R -V R- )/ 2 12 Easy to calibrate 2006 Texas Instruments Inc, Slide 13 DNL and INL Errors 111 INL < 0 Actual transfer function 110 Digital Output Code 101 100 011 DNL < 0 Ideal transfer function 010 001 000 Analog Voltage In 2006 Texas Instruments Inc, Slide 14 7
INL/DNL/Noise Impact on Dynamic Range 4096 Digital Code OUT Analog Voltage IN INL, DNL rms ADC Noise V REF ADC12 specifications DNL error E D max = ±1.7 LSB INL error E I max = ±1 LSB 1 LSB = (V R -V R- )/ 2 12 INL, DNL and Noise errors move across the entire range Impacts the Effective Number of Bits (ENOB) Not Easily calibrated Effects Accuracy 2006 Texas Instruments Inc, Slide 15 ADC Input Impedance Analog Input D ESD V CC Mux Resistance R S D ESD Leakage current R I = 2kΩ Sample Cap C I = 40pF V SS Input Internal Impedance is Relatively Low A High Impedance Source Increases Sample Cap Charging Time Rise Time of Voltage on CI ~ (RS RI) * CI 2006 Texas Instruments Inc, Slide 16 8
Sample Cap Charging Time 1400 ns (min) Sample Period Start Conversion Conversion Complete SAMPCON ADC12OSC/ADC12DIV 1 2 3 4 5 6 7 8 9 10 11 12 13 D ADC12MEMx 11 9 D D D D D D D D D D D 10 8 7 6 5 4 3 2 1 0 Desired Voltage on C I V C Rise Time of (R S R I ) * C I Final Voltage on C I 2006 Texas Instruments Inc, Slide 17 Alternative High Resolution Devices ADC12 Resolution = 12 bits Minimum LSB size = VREF / 2n = 1.5 V / 212 = 366 mv # channels = 12 to 16 (depends on part number) ADS8341 Resolution = 16 bits Minimum LSB size = VREF / 2n = 2.7 V / 216 = 41.2 mv # channels = 4 ADS1100 Resolution = 16 bits Minimum LSB size = VREF / 2n = 2*2.7 V / 216 = 82.4 mv # channels = 1 2006 Texas Instruments Inc, Slide 18 9
Agenda An Overview of the MSP430 Data Acquisition System SAR Converters The INS and OUTS of the SAR converter Useful Applications Using Op Amps Op Amp Configurations Driving SAR Converters 2006 Texas Instruments Inc, Slide 19 Operational Amplifiers Most Prevalent Building Block in Analog Circuits Very Flexible - Large Variety of Functions Circuits We Will Talk About General Purpose Op amp Unity Gain Buffer Comparator PGA (Programmable Gain Amplifier) Differential Amplifier R IN R F 2006 Texas Instruments Inc, Slide 20 10
Where to Find Op Amps OP OP AMP MUX FILTER Voltage Reference Source A/D REF Sensor Interface Voltage Reference Source Buffer Gain Difference Amplifier Instrumentation Amplifier Filter Level Shift Anti-Alias Filter Band-pass Filter Programmable Gain Amp Instrumentation Amp A/D Converter Driver Voltage Reference Source DDS Synthesis μ C Valve Actuator Driver Line Driver 4-20mA Driver POWER AMP D/A 2006 Texas Instruments Inc, Slide 21 Ideal Op Amp POWER SUPPLY No min or max Voltage I SUPPLY = 0 Amps Power Supply Rejection = INPUT Input Current (I B ) = 0 Input Impedance (Z IN ) = Input Voltage ( ) no limits Zero Noise Zero DC error Common-Mode Rejection = - V DD V SS OUTPUT = V SS to V DD I OUT = Slew Rate = Z OUT = 0 Ω SIGNAL TRANSFER Open Loop Gain = Bandwidth = 0 Zero Harmonic Distortion $0.00 2006 Texas Instruments Inc, Slide 22 11
Open Loop vs Closed Loop Design OAFCx = 011 Open Loop Configuration In Comparator mode V REF OAFCx = 000 Closed Loop Configuration Always a Connection from Output to Inverting Input Gain is Dependant on Resistors R IN = High for > V REF Low for < V REF R F = ( 1 R F / R IN ) ( ) 2006 Texas Instruments Inc, Slide 23 Comparator Mode OAFCx = 011 Temperature Sensor V A (t) R NTC R PAR R REF Px.y R REF MSP430FG43x NTC R PAR Px.x V TH t = 0 t = t1 t = t2 Time V A C INT OAxI0 Comparator Timer V TH = 0.25V CC R NTC RPAR R REF --------------- = ---------- t NTC RPAR t REF 2006 Texas Instruments Inc, Slide 24 12
General Op amp Mode OAFCx = 000 OA0O OAxI1 MSP430FG43x V IN OAxI0 V REF 2006 Texas Instruments Inc, Slide 25 General Op amp Mode OAFCx = 000 Non-inverting Gain R F CAx MSP430FG43x V REF = 0.5V CC V R IN REF OA0O OA0I1 OA0I0 = (1 R F/ R IN ) V REF *R F /R IN 2006 Texas Instruments Inc, Slide 26 13
General Op amp Mode OAFCx = 000 Inverting Gain R IN R F V REF = 0.5V CC OA0O OA0I1 OA0I0 CAx MSP430FG43x V REF = 0.5V CC = V REF (1 R F/ R IN ) *R F /R IN 2006 Texas Instruments Inc, Slide 27 Data Acquisition System Analog Gain and Signal Conditioning Cell Analog Low Pass Filter (LPF) Analog to Digital Conversion (ADC) Digital Filter Input Signal Analog Output Signal Digital 2006 Texas Instruments Inc, Slide 28 Figure 4.1 14
Noise Reduction with a Low Pass Filter Noise Reduction or Anti-aliasing Filter R 23 C 22 R 21 R 22 - C 21 OA ADC12 V REF 2006 Texas Instruments Inc, Slide 29 Anti-alias Filter :: Nyquist Theorem Signal at the Input of the A/D Converter f ALIASED = f IN -Nf S Find N by making f ALIASED < f s / 2 Digital Representation at the Output of the Converter Analog Input N = 0 (1) (2) N = 1 N = 2 (3) N = 3 (4) (5) N = 4 f S /2 3f S /2 5f S /2 7f S /2 0 f S 2f S 3f S 4f S Sampled Output Representation N = 0 (2) (1) (4) (3) (5) 0 f S /2 f S 2006 Texas Instruments Inc, Slide 30 15
Filter Pro Software Filter synthesis tool for designing Multi-section filter Low-pass Filter High-pass active filter Supports 2nd to 10th order Multiple-feedback (MFB) Filter Topology Sallen-Key Filter Topology www.ti.com 2006 Texas Instruments Inc, Slide 31 Operational Amp Output Swing Rail-to-Rail Output Operation does not Exist How Close the Amplifier s Output can Come to the Power Supplies (or rails ) and still be Linear MSP430FG43x = (VSS 200mV) {min} to (VCC- 200mV) {max} = ( 1 R F / R IN ) R IN R F 2006 Texas Instruments Inc, Slide 32 16
Operational Amp Output Swing 10 Offset Voltage, V OS (mv) 0-10 -20-30 -40 0 1 2 3 3.6 4 Output Voltage, (V) 2006 Texas Instruments Inc, Slide 33 Unity Gain Buffer Mode OAFCx = 001 OAxI0 MSP430FG43x OA ADC12 Op Amp Internally connected as a buffer Non-inverting input available on a Controller pin Op Amp Output connected directly to ADC12 2006 Texas Instruments Inc, Slide 34 17
Op Amp Input Voltage Range RRIP ON = (VSS - 0.1V) {min} to (VCC 0.1) {max} Charge pump on input stage is turned on Great Feature, not all amps have this! RRIP OFF = (VSS - 0.1V) {min} to (VCC - 1.2) {max} (Appropriate for Gains > 2) 2006 Texas Instruments Inc, Slide 35 PGA Mode Non-inverting Mode OAFCx = 100 = G DACs or external R BOTTOM R R R R 2R - 2R MSP430FG44x Ax int/ext 4R 4R R TOP RRIP off OAxCTL1 111100x1 G=16 110100x1 G=8 101100x1 G=3.33 100100x1 G=4 011100x1 G=2.67 010100x1 G=2 001100x0 G=1.33 000100x0 G=1 AV SS RRIP on PGA Non-inverting 2006 Texas Instruments Inc, Slide 36 18
PGA Mode Inverting Mode OAFCx = 110 = G V REF (1 G) DACs or external R R BOTTOM R R V REF - R 2R 2R MSP430FG44x Ax int/ext 4R 4R R TOP RRIP off OAxCTL1 111110x1 G=-15 110110x1 G=-7 101110x1 G=-4.33 100110x1 G=-3 011110x1 G=2.67 010110x1 G=-1.67 001110x1 G=-1 000110x0 G=-0.33 PGA Inverting RRIP on 2006 Texas Instruments Inc, Slide 37 Bridge Network MSP430FG43x R 23 μcontroller V REF1 - C 22 Functions R L1 R L2 R L2 R L1 R 1 INA326 G = 2 (R 2 /R 1 ) = 245 R 21 R 22 C 21 - OA SAR ADC 12 bits LCL- 816G R 2 C 1 V REF2 2006 Texas Instruments Inc, Slide 38 19
Summary 12-bit SAR Converter ADC12 12-bit Resolution and Accuracy Excellent Dynamic Range For more Resolution Discrete Options Operational Amplifier OA Standard Single Supply CMOS Op Amp Rail-to-rail Input Rail-to-rail Output Six Configurations or Modes For more Accuracy Discrete Options For more Complexity Discrete Options MSP430 Analog Options Very Useful! 2006 Texas Instruments Inc, Slide 39 20