Utra Low On-Resistance Surface Mount (IRFR3303) Straight Lead (IRFU3033) Advanced Process Technoogy Fast Switching Fuy Avaanche Rated Lead-Free Description G IRFR3303PbF IRFU3303PbF HEXFET Power MOSFET D S PD - 95070A V DSS = 30V R DS(on) = 0.03Ω Fifth Generation HEXFETs from Internationa Rectifier utiize advanced processing techniques to achieve extremey ow on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are we known for, provides the designer with an extremey efficient and reiabe device for use in a wide variety of appications. The D-Pak is designed for surface mounting using vapor phase, infrared, or wave sodering techniques. The straight ead version (IRFU series) is for through-hoe mounting appications. Power dissipation eves up to.5 watts are possibe in typica surface mount appications. Absoute Maximum Ratings D-Pak TO-252AA I-Pak TO-25AA Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 33 I D @ T C = 0 C Continuous Drain Current, V GS @ V 2 A I DM Pused Drain Current 20 P D @T C = 25 C Power Dissipation 57 W Linear Derating Factor 0.45 W/ C V GS Gate-to-Source Votage ± 20 V E AS Singe Puse Avaanche Energy 95 mj I AR Avaanche Current 8 A E AR Repetitive Avaanche Energy 5.7 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 50 T STG Storage Temperature Range Sodering Temperature, for seconds 300 (.6mm from case ) C Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 2.2 R θja Junction-to-Ambient (PCB mount)** 50 C/W R θja Junction-to-Ambient www.irf.com 2/4/04
Eectrica Characteristics @ T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 30 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Votage Temp. Coefficient 0.032 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 0.03 Ω V GS = V, I D = 8A V GS(th) Gate Threshod Votage 2.0 4.0 V V DS = V GS, I D = 250µA g fs Forward Transconductance 9.3 S V DS = 25V, I D = 8A I DSS Drain-to-Source Leakage Current 25 V µa DS = 30V, V GS = 0V 250 V DS = 24V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 20V na Gate-to-Source Reverse Leakage -0 V GS = -20V Q g Tota Gate Charge 29 I D = 8A Q gs Gate-to-Source Charge 7.3 nc V DS = 24V Q gd Gate-to-Drain ("Mier") Charge 3 V GS = V, See Fig. 6 and 3 t d(on) Turn-On Deay Time V DD = 5V t r Rise Time 99 I D = 8A ns t d(off) Turn-Off Deay Time 6 R G = 3Ω t f Fa Time 28 R D = 0.8Ω, See Fig. Between ead, L D Interna Drain Inductance 4.5 6mm (0.25in.) nh from package G L S Interna Source Inductance 7.5 and center of die contact C iss Input Capacitance 750 V GS = 0V C oss Output Capacitance 400 pf V DS = 25V C rss Reverse Transfer Capacitance 40 ƒ =.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 33 (Body Diode) showing the A I SM Pused Source Current integra reverse G 20 (Body Diode) p-n junction diode. S V SD Diode Forward Votage.3 V T J = 25 C, I S = 8A, V GS = 0V t rr Reverse Recovery Time 53 80 ns T J = 25 C, I F = 8A Q rr Reverse RecoveryCharge 94 40 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 590µH R G = 25Ω, I AS = 8A. (See Figure 2) ƒ I SD 8A, di/dt 40A/µs, V DD V (BR)DSS, T J 50 C Puse width 300µs; duty cyce 2%. Cacuated continuous current based on maximum aowabe junction temperature; Package imitation current = 20A. This is appied for I-PAK, L S of D-PAK is measured between ead and center of die contact ** When mounted on " square PCB (FR-4 or G- Materia ). For recommended footprint and sodering techniques refer to appication note #AN-994
I D, Drain-to-Source Current (A) 00 0 0. VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 0.0 T J = 25 C 0. 0 V DS, Drain-to-Source Votage (V) I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 20µs PULSE WIDTH 4.5V T J = 50 C 0. 0 V DS, Drain-to-Source Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-Source Current (A) 0 T J= 50 C T J = 25 C V DS= 5V 25V 20µs PULSE WIDTH 0. 4 5 6 7 8 9 V GS, Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) 2.0 I D = 30A.5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 0 20 40 60 T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized On-Resistance Vs. Temperature
C, Capacitance (pf) 400 VGS = 0V, f = MHz Ciss = Cgs Cgd, C ds SHORTED 200 Crss = Cgd Coss = Cds Cgd 00 C iss 800 C oss 600 400 C rss 200 0 0 V DS, Drain-to-Source Votage (V) V GS, Gate-to-Source Votage (V) 20 6 2 8 4 I = D 8A V DS = 24V V DS = 5V FOR TEST CIRCUIT SEE FIGURE 3 0 0 5 5 20 25 30 Q G, Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current (A) 00 0 T J = 25 C T J = 50 C V GS = 0 V 0. 0.0.0 2.0 3.0 4.0 5.0 V SD,Source-to-Drain Votage (V) I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us 0us ms TC = 25 C ms TJ = 50 C Singe Puse 0 V DS, Drain-to-Source Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating Area
I D, Drain Current (A) 35 30 25 20 5 LIMITED BY PACKAGE R G V GS V V DS Puse Width µs Duty Factor 0. % R D D.U.T. Fig a. Switching Time Test Circuit - V DD 5 V DS 90% 0 25 50 75 0 25 50 T C, Case Temperature ( C) % V GS t d(on) t r t d(off) t f Fig 9. Maximum Drain Current Vs. Case Temperature Fig b. Switching Time Waveforms Therma Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J= P DM x Z thjc TC 0.0 0.0000 0.000 0.00 0.0 0. t, Rectanguar Puse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Therma Impedance, Junction-to-Case
L V DS D.U.T. R G V - DD V I AS t p 0.0Ω Fig 2a. Uncamped Inductive Test Circuit V (BR)DSS t p E AS, Singe Puse Avaanche Energy (mj) 200 50 0 50 TOP BOTTOM I D 8.0A A 8A 0 25 50 75 0 25 50 Starting T, Junction Temperature ( J C) V DS V DD Fig 2c. Maximum Avaanche Energy Vs. Drain Current I AS Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF V Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge I G I D Current Samping Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Appied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4. For N-Channe HEXFETS
D-Pak (TO-252AA) Package Outine Dimensions are shown in miimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR20 WITH ASSEMBLY LOT CODE 234 ASS EMBLED ON WW 6, 999 IN THE ASSEMBLY LINE "A" Note: "P" in assemby ine position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 96A 2 34 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 6 LINE A OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 2 34 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 999 WEEK 6 A = AS S E MBL Y S IT E CODE
I-Pak (TO-25AA) Package Outine Dimensions are shown in miimeters (inches) I-Pak (TO-25AA) Part Marking Information EXAMPLE: THIS IS AN IRFU20 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 9, 999 IN THE ASSEMBLY LINE "A" Note: "P" in assemby ine pos ition indicates "Lead-F ree" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 99A 56 78 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 9 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE IRFU20 56 78 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 999 WEEK 9 A = ASSEMBLY SITE CODE
D-Pak (TO-252AA) Tape & Ree Information Dimensions are shown in miimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA-54. 3 INCH NOTES :. OUTLINE CONFORMS TO EIA-48. 6 mm Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, USA Te: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for saes contact information.2/04
Note: For the most current drawings pease refer to the IR website at: http://www.irf.com/package/