TVS Diode Transient Voltage Suppressor Diodes ESD5V3L1B Series Bi-directional Low Capacitance ESD / Transient Protection Diode ESD5V3L1B-02LRH ESD5V3L1B-02LS Data Sheet Revision 1.1, 2012-10-15 Final Power Management & Multimarket
Edition 2012-10-15 Published by Infineon Technologies AG 81726 Munich, Germany 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Revision History Revision 1, 2011-08-04 Page or Item Subjects (major changes since previous revision) Revision 1.1, 2012-10-15 5 Table 2-1 updated 8/9 Figure 3-3 and Figure 3-4 updated Trademarks of Infineon Technologies AG AURIX, BlueMoon, C166, CanPAK, CIPOS, CIPURSE, COMNEON, EconoPACK, CoolMOS, CoolSET, CORECONTROL, CROSSAVE, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPIM, EiceDRIVER, eupec, FCOS, HITFET, HybridPACK, I²RF, ISOFACE, IsoPACK, MIPAQ, ModSTACK, my-d, NovalithIC, OmniTune, OptiMOS, ORIGA, PRIMARION, PrimePACK, PrimeSTACK, PRO-SIL, PROFET, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SIPMOS, SMARTi, SmartLEWIS, SOLID FLASH, TEMPFET, thinq!, TRENCHSTOP, TriCore, X-GOLD, X-PMU, XMM, XPOSYS. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, KEIL, PRIMECELL, REALVIEW, THUMB, µvision of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. murata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Satellite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update 2010-10-26 Final Data Sheet 3 Revision 1.1, 2012-10-15
Bi-directional Low Capacitance ESD / Transient Protection Diode 1 Bi-directional Low Capacitance ESD / Transient Protection Diode 1.1 Features ESD / transient protection of signal lines in low voltage applications according to: IEC61000-4-2 (ESD): ±20 kv (air / contact) IEC61000-4-4 (EFT): 40 A (5/50 ns) Bi-directional, symmetrical working voltage up to V RWM = ±5.3 V Low capacitance: C L = 5 pf (typical) Low clamping voltage, low dynamic resistance down to: R DYN = 0.23 Ω (typical) Pb-free (RoHS compliant) and halogen free package, very small form factor: 0.62 x 0.32 x 0.31 mm 3 1.2 Application Examples Keypad, touchpad, buttons, convenience keys LCD displays, Camera, audio lines, mobile communication, Consumer products (E-Book, MP3, DVD, DSC...) Notebooks tablets and desktop computers and their peripherals 1.3 Product Description Pin 1 Pin 2 Pin 1 Pin 1 marking (lasered) TSLP-2 Pin 1 Pin 2 Pin 2 TSSLP-2 a) Pin configuration b) Schematic diagram Figure 1-1 Pin Configuration and Schematic Diagram PG-TS(S)LP-2_Dual_Diode_Serie_PinConf_and_SchematicDiag.vsd Table 1-1 Ordering Information Type Package Configuration Marking code ESD5V3L1B-02LRH PG-TSLP-2-17 1 line, bi-directional 4 ESD5V3L1B-02LS PG-TSSLP-2-1 1 line, bi-directional C Final Data Sheet 4 Revision 1.1, 2012-10-15
Characteristics 2 Characteristics Table 2-1 Maximum Ratings at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Min. Typ. Max. ESD contact discharge 1) V ESD 20 kv Peak pulse current (t p = 8/20 μs) 2) I PP 3 2.5 A Peak pulse power (t p = 8/20 μs) 2) P PP 39 30 W Operating temperature range T OP -40 125 C Storage temperature T stg -65 150 C 1) V ESD according to IEC61000-4-2 2) I PP according IEC61000-4-5 Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 2.1 Electrical Characteristics at T A = 25 C, unless otherwise specified Figure 2-1 Definitions of electrical characteristics Final Data Sheet 5 Revision 1.1, 2012-10-15
Characteristics Table 2-2 DC Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Reverse working voltage V RWM -5.3 5.3 V Breakdown voltage V BR 6 10 V I BR = 1 ma Reverse current I R 100 na V R = 5.3 V Table 2-3 RF Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Line capacitance C L 4 7 pf V R = 0 V, f = 1 MHz Series inductance L S 0.4 nh PG-TSLP-2-17 0.2 PG-TSSLP-2-1 Table 2-4 ESD Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Clamping voltage 1) V CL 10.2 V I TLP = 16 A, from Pin 1 to Pin 2 13.2 I TLP = 30 A, from Pin 1 to Pin 2 12.1 I TLP = 16 A, from Pin 2 to Pin 1 17.2 I TLP = 30 A, from Pin 2 to Pin 1 Clamping voltage 2) 8.5 I PP = 1 A, from Pin 1 to Pin 2 9.8 I PP = 2.5 A, from Pin 1 to Pin 2 8.5 I PP = 1 A, from Pin 2 to Pin 1 10.4 I PP = 2.5 A, from Pin 2 to Pin 1 Dynamic resistance 2) R DYN 0.22 Ω Pin 1 to Pin 2 0.37 Ω Pin 2 to Pin 1 1) Please refer to Application Note AN210 [1]. TLP parameter: Z 0 = 50 Ω, t p = 100ns, t r = 300ps, averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristics between I PP1 = 10 A and I PP2 = 40 A. 2) I PP according to IEC61000-4-5 (t p = 8/20 μs) Final Data Sheet 6 Revision 1.1, 2012-10-15
Typical Characteristics at T A = 25 C, unless otherwise specified 3 Typical Characteristics at T A = 25 C, unless otherwise specified 10-6 10-7 10-8 I R [A] 10-9 10-10 10-11 10-12 -10-8 -6-4 -2 0 2 4 6 8 10 V R [V] Figure 3-1 Reverse current: I R = f(v R ) 7 6 5 C L [pf] 4 3 2 1 0-6 -5-4 -3-2 -1 0 1 2 3 4 5 6 V R [V] Figure 3-2 Line capacitance: C L = f(v R ), f = 1MHz Final Data Sheet 7 Revision 1.1, 2012-10-15
Typical Characteristics at T A = 25 C, unless otherwise specified 40 ESD5V3L1B-02xx R DYN 20 30 15 R DYN = 0.23 Ω 20 10 I TLP [A] 10 0-10 5 0-5 Equivalent V IEC [kv] -20-10 R DYN = 0.36 Ω -30-15 -40-20 -25-20 -15-10 -5 0 5 10 15 20 25 V TLP [V] Figure 3-3 Clamping voltage (TLP): I TLP = f(v TLP ) according ANSI/ESD STM5.5.1 - Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z 0 = 50 Ω, t p = 100 ns, t r = 0.6 ns, I TLP and V TLP averaging window: t 1 = ns to t 2 = 60 ns, extraction of dynamic resistance using squares fit to TLP characteristics between I TLP1 = 10 A and I TLP2 = 40 ma. Please refer to Application Note AN210[1] Final Data Sheet 8 Revision 1.1, 2012-10-15
Typical Characteristics at T A = 25 C, unless otherwise specified 4 ESD5V3L1B-02xx R DYN 3 R DYN = 0.9 Ω 2 1 I PP [A] 0-1 -2 R DYN = 1.4 Ω -3-4 -15-10 -5 0 5 10 15 V CL [V] Figure 3-4 Pulse current (IEC61000-4-5) versus clamping voltage: I PP = f(v CL ) Final Data Sheet 9 Revision 1.1, 2012-10-15
Typical Characteristics at T A = 25 C, unless otherwise specified V CL [V] 70 60 50 40 30 20 10 0 V CL-max-peak = 45.0 [V] V CL-30ns-peak = 10.7 [V] -10-100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 3-5 IEC61000-4-2: V CL = f(t), 8 kv positive pulse from pin 1 to pin 2 10 0-10 V CL [V] -20-30 -40-50 -60 V CL-max-peak = -66.7 [V] V CL-30ns-peak = -9.7 [V] -70-100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 3-6 IEC61000-4-2: V CL = f(t), 8 kv negative pulse from pin 1 to pin 2 Final Data Sheet 10 Revision 1.1, 2012-10-15
Typical Characteristics at T A = 25 C, unless otherwise specified V CL [V] 110 100 90 80 70 60 50 40 30 20 10 0-10 -20 V CL-max-peak = 74.5 [V] V CL-30ns-peak = 12.0 [V] -100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 3-7 IEC61000-4-2: V CL = f(t), 15 kv positive pulse from pin 1 to pin 2 V CL [V] 20 10 0-10 -20-30 -40-50 -60-70 -80-90 -100-110 V CL-max-peak = -96.9 [V] V CL-30ns-peak = -15.6 [V] -100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 3-8 IEC61000-4-2: V CL = f(t), 15 kv negative pulse from pin 1 to pin 2 Final Data Sheet 11 Revision 1.1, 2012-10-15
Application Information 4 Application Information Connector Protected signal line 1 I/O ESD sensitive device 2 The protection diode should be placed very close to the location where the ESD or other transients can occur to keep loops and inductances as small as possible. Pin 2 (or pin 1) should be connected directly to a ground plane on the board. Figure 4-1 Single line, bi-directional ESD / Transient protection Application_ESD5V3S1B-02LS.vsd Final Data Sheet 12 Revision 1.1, 2012-10-15
Ordering Information Scheme (Examples) 5 Ordering Information Scheme (Examples) ESD 0P1 RF - XX YY Package XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP For Radio Frequency Applications Line Capacitance CL in pf: (i.e.: 0P1 = 0.1pF) ESD 5V3 U n U - XX YY Package or Application XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP S = SOT363 U = SC74 XX = Application family: LC = Low Clamp HDMI Uni- / Bi-directional or Rail to Rail protection Number of protected lines (i.e.: 1 = 1 line; 4 = 4 lines) Capacitance: Standard (>10pF), Low (<10pF), Ultra-low (<1pF) Figure 5-1 Maximum working voltage VRWM in V: (i.e.: 5V3 = 5.3V) Ordering information scheme Final Data Sheet 13 Revision 1.1, 2012-10-15
Package Information 6 Package Information 6.1 PG-TSLP-2-17 (mm) [2] Top view +0.01 0.39-0.03 Bottom view 0.05 MAX. 0.6 ±0.05 0.65 ±0.05 2 1 1±0.05 Cathode marking 1) 0.5 ±0.035 1) Dimension applies to plated terminal 1) 0.25 ±0.035 Figure 6-1 PG-TSLP-2-17: Package overview TSLP27PO V02 0.6 0.35 0.45 1 0.3 0.925 0.275 0.35 0.275 0.375 Copper Solder mask Stencil apertures TSLP-2-7-FP V01 Figure 6-2 PG-TSLP-2-17: Footprint 4 0.5 1.16 8 Orientation marking 0.76 TSLP-2-7-TP V03 Figure 6-3 PG-TSLP-2-17: Packing Type code 12 Cathode marking Figure 6-4 PG-TSLP-2-17: Marking (example) Final Data Sheet 14 Revision 1.1, 2012-10-15
Package Information 6.2 PG-TSSLP-2-1 (mm) [2] Top view +0.01 0.31-0.02 Bottom view 0.32±0.035 0.355±0.025 2 1 0.62 ±0.035 Cathode marking 1) 0.26±0.025 1) 0.2 ±0.025 Figure 6-5 1) Dimension applies to plated terminal PG-TSSLP-2-1: Package overview TSSLP-2-1,-2-PO V05 0.32 0.24 0.27 0.24 0.19 0.19 0.62 0.19 0.57 0.14 Copper Solder mask Stencil apertures Figure 6-6 Cathode marking Figure 6-7 PG-TSSLP-2-1: Footprint 4 0.35 Ey 8 Ex PG-TSSLP-2-1: Packing a g Tape type Punched Tape Embossed Tape TSSLP-2-1,-2-FP V02 Ex Ey 0.43 0.73 0.37 0.67 Deliveries can be both tape types (no selection possible). Specification allows identical processing (pick & place) by users. TSSLP-2-1,-2-TP V03 Figure 6-8 PG-TSSLP-2-1: Marking (example) Final Data Sheet 15 Revision 1.1, 2012-10-15
References References [1] Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP Characterization Methodology [2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages Final Data Sheet 16 Revision 1.1, 2012-10-15
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