PE93 Product Description The PE93 is a high-performance static UltraCMOS prescaler with a fixed divide ratio of. Its operating frequency range is DC to 500 MHz. The PE93 operates on a nominal 3V supply and draws only 6.5 ma. It is packaged in a small 8-lead CFP and is ideal for frequency scaling and clock generation solutions. The PE93 is manufactured on Peregrine s UltraCMOS process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. 500 MHz Low Power UltraCMOS Divide-by- Prescaler Radiation Tolerant for Space Applications Features DC to 500 MHz operation Fixed divide ratio of Low-power operation: 6.5 ma typical @ 3V Small package: 8-lead CFP Guaranteed 00 krad(si) total dose performance Superior single event upset immunity Figure. Functional Diagram Figure. Package Type 8-lead CFP D Q IN CLK QB Pre-Amp Output Buffer Table. Electrical Specifications (Z S = Z L = 50Ω) V DD = 3.0V, 40 C T A +85 C, unless otherwise specified Parameter Condition Min Typ Max Unit Supply voltage.85 3.0 3.5 V Supply current 6.5 ma Input frequency, F IN DC 500 MHz DC < F IN 000 MHz 8 +0 dbm Input power, P IN 000 < F IN 500 MHz 0 +0 dbm Output power, P DC < F IN 500 MHz 0 dbm Document No. DOC-494-4 www.ev-us.com 003 05 Peregrine Semiconductor Corp. All rights reserved. Page of 7
Figure 3. Pin Configuration Pin dot marking V DD IN NC 3 4 PE93 Table. Pin Descriptions Pin # Pin Name V DD Table 3. Absolute Maximum Ratings 8 7 6 5 NC Description Power supply pin. Bypassing is required (eg 000 pf & 00 pf). IN Input signal pin. Should be coupled with a capacitor (eg 000 pf). 3 NC No connection. This pin should be left open. 4 Ground pin. Ground pattern on the board should be as wide as possible to reduce ground impedance. 5 Ground pin. 6 NC No connection. This pin should be left open. 7 Divided frequency output pin. This pin should be coupled with a capacitor (eg 000 pf). 8 Ground Symbol Parameter/Condition Min Max Unit V DD Supply voltage 4.0 V P IN Input power 5 dbm V IN Voltage on input 0.3 V DD + 0.3 V T ST Storage temperature range 65 50 C T OP V ESD Operating temperature range ESD voltage (Human Body Model, MIL-STD 883) 40 85 C 000 V Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Latch-Up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Device Functional Considerations The PE93 divides an input signal, up to a frequency of 500 MHz, by a factor of two thereby producing an output frequency at half the input frequency. To work properly at higher frequency, the input and output signals (pins and 7) must be AC coupled via an external capacitor, as shown in the test circuit in Figure 7. The input may be DC coupled for low frequency operation with care taken to remain within the specified DC input range for the device. The ground pattern on the board should be made as wide as possible to minimize ground impedance. See Figure 8 for a layout example. ELDRS UltraCMOS devices do not include bipolar minority carrier elements, and therefore do no exhibit enhanced low dose rate sensitivity. Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating ranges maximum and absolute maximum for extended periods may reduce reliability. 003 05 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-494-4 UltraCMOS RFIC Solutions Page of 7
Typical Performance Data @ V DD = 3.0V Figure 4. Input Sensitivity Figure 5. Device Current Figure 6. Output Power Document No. DOC-494-4 www.ev-us.com 003 05 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 7
Figure 7. Test Circuit Block Diagram 3 V 00 pf 000 pf VDD 50 IN 50 N/C N/C Power Meter or Frequency Counter 003 05 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-494-4 UltraCMOS RFIC Solutions Page 4 of 7
Evaluation Kit Operation Figure 8. Evaluation Board Layout The ceramic CFP prescaler evaluation board was designed to help customers evaluate the PE93 divide-by- prescaler. On this board, the device input (pin ) is connected to the SMA connector J through a 50Ω transmission line. A series capacitor (C3) provides the necessary DC block for the device input. A value of 000 pf was used for the evaluation board; other applications may require a different value. It is also possible to place a 0Ω resistor in this location for very low frequency applications. The device output (pin 7) is connected to SMA connector J3 through a 50Ω transmission line. A series capacitor (C) provides the necessary DC block for the device output. This capacitor value must be chosen to have a low impedance at the desired output frequency of the device. A value of 000 pf was chosen for the evaluation board. The board is constructed of a two-layer FR4 material with a total thickness of 0.03. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide above ground plane model with trace width of 0.030, trace gaps of 0.006, dielectric thickness of 0.08, metal thickness of 0.004 and ε r of 4.6. Note that the predominate mode of these transmission lines is coplanar waveguide. J provides DC power to the device via pin. Two decoupling capacitors (C = 00 pf, C0 = 000 pf) are included on this trace. It is the responsibility of the customer to determine proper supply decoupling for their design application. J HEADER 7X X9 4 4 3 3 X93 6 6 5 5 X53 8 8 7 7 0 0 9 9 4 4 3 3 X54 PRT-705 Figure 9. Evaluation Board Schematic C0 C C5? 0pF U3 PE93//3 (CSOIC-8) J RF In VDD 8 J3 Out R C3 FIN 7 C R3 0 R 0 C8 DNI C4 DNI C6 DNI 3 NC 4 NC 6 5 J4 RF In J5 Out Document No. DOC-494-4 www.ev-us.com DOC-496 003 05 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 7
Figure 0. Package Drawing 8-lead CFP 5.59-6.35 4.57 MAX 4. 4.57 MAX.73 0.38±0.05 4.57 MAX 4..7 3.8 4.57 MAX 0.033±0.38 TOP VIEW BOTTOM VIEW 0.5 Min Lid 0.5 0.56 0.7.73.78 MAX 0.8 Min 0.5 0.5 0.7 0.3 MIN Side View 0.54±0.05.70 MIN DOC-50608 Figure. Top Marking Specifications 93-XX YYWW ZZZZZZZ nnnnnn PRT-5008 = Pin indicator 93-XX = Part number (XX will be specified by the PO and/or the assembly instructions) YYWW = Date code, last two digits of the year and work week ZZZZZZZ = Lot code (up to seven digits) nnnnnn = Serial number of the part (up to six digits) 003 05 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-494-4 UltraCMOS RFIC Solutions Page 6 of 7
Table 4. Ordering Information Order Code Description Package Shipping Method 93 0* PE93 08CFPG B Engineering samples 8-lead CFP 50 / Tray 93 PE93 08CFPG B Production units 8-lead CFP 50 / Tray 93 00 PE93 Evaluation kit Evaluation kit / Box Note: * The 93-0 devices are engineering sample (ES) prototype units intended for use as initial evaluation units for customers of the PE93- flight units. The PE93-0 device provides the same functionality and footprint as the PE93- space qualified device, and intended for engineering evaluation only. They are tested at +5 C only and processed to a non-compliant flow (e.g. no burn-in, non-hermetic, etc). These units are non-hermetic and are not suitable for qualification, production, radiation testing or flight use. Sales Contact and Information Contact Information: ev ~ http://www.ev-us.com ~ inquiries@ev-us.com Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. : The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com. Document No. DOC-494-4 www.ev-us.com 003 05 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 7