Physical Layer Modelling of Semiconductor Optical Amplifier Based Terabit/second Switch Fabrics K.A. Williams, E.T. Aw*, H. Wang*, R.V. Penty*, I.H. White* COBRA Research Institute Eindhoven University of Technology Eindhoven, The Netherlands * Department of Engineering, University of Cambridge, 9 JJ Thomson Avenue, Cambridge CB3 FA, UK
Outline Motivation for studying semiconductor optical amplifier switch fabrics Low latency reconfigurable interconnects in high performance computing Emerging scalable photonic integrated switch circuits Viability of multistage switch architectures for large scale interconnection Simulator architecture Multiwavelength emulator Power penalty estimation Performance mapping for multi-stage networks Switch fabric performance Calibration Scaling capacity - multi-wavelength operation Scaling connectivity - input power dynamic range Conclusions PAGE 2
Low latency reconfigurable interconnects Terabit/second SOA based 12x12 Data Vortex Shacham JLT, 23, (), 366-375, (Oct 25). High performance computing, future server networks, requiring Terabit/second low latency interconnection with several tens of high bandwidth ports Sophisticated testbeds devised and implemented increasing numbers of groups Colourless SOA switches promising for routing of high capacity WDM packets. Good crosstalk, ease of use and integration being key. HOWEVER: Concerns over accumulating noise and distortion PAGE 3
Emerging integrated switch technology Highly cascadability demonstrated for quantum dot based switches Liu, CLEO 26 Uncooled power efficient (7ºC) 2x2 QD switches demonstrated Aw, CLEO 28 Low power penalty routing demonstrated with 4 input 4 output multi-stage switch circuits Albores-Mejia, Photonics in Switching 28 8 6 4 2 Q factor Penalty 2 4 6 8 12 14 Number of loop circulations Discrete cascaded QD SOAs 8 6 4 2 Larger monolithic switch matrices now becoming tractable Integrated multistage circuits BUT little study into the scaling limits for broadband SOA based switches PAGE 4
Multi-stage switch fabrics: Clos networks n m blocks 1 2 r r blocks 1 m n blocks 1 2 n inputs 3 4 2 3 4 noutputs m outputs m inputs 5 6 3 5 6 7 r m 7 r 16x16 r inputs r outputs Generalised three stage Clos networks offer good compromise between number of stages (power consumption, power penalty) and connection scaling Scaling assessed by studying the data integrity at the physical layer for varied data capacity per port for three stage networks Large networks feasible by introducing increasing numbers of splitters at each stage PAGE 5
Wavelength multiplexed link simulation Pseudorandom sequence generation Time resolved Gb/s waveform generation Time decorrelated channel replication Wavelength multiplexing ΣE(f) Variable optical attenuation for penalty measure System under test Variable optical attenuation for dynamic range Demux PIN diode with thermal noise Bessel filter in frequency domain Eye diagram generation Q factor Mixed time and frequency domain units cascaded for power penalty evaluation from Q factor PAGE 6
Power penalty evaluation Amplitude 2 5 Bit period [ps] Bit error rate Deviation from -3 thermally limited error rate with SOA switches -6 introduced Back to -9 back -12 operation -24-22 -2-18 -16 Received optical power [dbm] Time resolved receiver output time-wrapped to generate eye diagram Centre of eye opening windowed by locating level transitions Probability density functions generated from ones (black) and zeros (red) Bit error rates correlate with Q factors for Gaussian PDFs Specify power penalty at BER= -9 E. Desurvire, Erbium doped fiber amplifiers, Wiley PAGE 7
Switch fabric definition Wavelength multiplexed input N x Gb/s Architecture (loss) variation Current (gain) variation Architecture (loss) variation Splitter losses Travelling wave and carrier rate equation model Splitter losses Optical field recirculated for, 1, 2 and 3 loops Splitter losses scanned to study range of connection configurations Currents scanned to identify local optima Input power scanned at system input Travelling wave algorithm as per Distributed Feedback Semiconductor Lasers Carroll, Whiteaway, Plumb, IEE, 1998 Data integrity assessment Q factor PAGE 8
Travelling wave model calibration On chip gain [db. Power penalty [db] 3 2-1.5 1..5 5 15 2 Current [ma]. -3-25 -2-15 - -5 Input power (on chip) [dbm] 4 3 2 15 5 OSNR [db/.1nm] Gain on 2x2 chip [db] Calibration of model for performance of uncooled 2x2 switch circuits Benchmarked as a function of input current and input power Logarithmic gain carrier relationship. No wavelength dependence implemented. Experimental data from Aw, CLEO 28 PAGE 9
Power penalty performance (i) Bias current [ma] 5 15 Power penalty [db] 2-3 -25-2 -15 - -5 Input power [dbm] (ii) Power penalty [db] Bias current [ma] 5 15 2 1xGb/s xgb/s -3-25 -2-15 - -5 Input power [dbm/channel] 4 db 2 db 4 db 2 db Data shown for three stage 16x16 switch implemented with 4x4 stages Extensive operating range for single wavelength operation Distortion evident at high input power and high current Distortion threshold further reduced through increased aggregate power Optimum current conditions selected for broader architecture comparisons PAGE
Multi-stage input power dynamic range Input power per channel [dbm] -5 - -15-2 -25-3 Total number of power splitters per stage 2 3 4 5 6 7 1dB power penalty 4 8 16 32 64 128 Number of input ports for 3 stage network Stage 1 Stage 2 Stage 3 2dB power penalty Stage 1 Stage 2 Stage 3 Multiple simulations for broader range of power maps enables comparison of connection levels Dynamic range reduced at each consecutive stage Distortion limited at high power Noise limited at low power The combined effect ultimately limits feasible power maps and connectivity 1dB power penalty for 32x32 2dB power penalty for 64x64 PAGE 11
Conclusions Three stage switch fabrics analysed for Clos switching networks with SOAs Low penalty multiwavelength routing of xgb/s payloads shown High data capacity feasible in large scale switch fabrics 32x32 switch fabric feasible with 1dB power penalty 64x64 switch fabric indicates 2dB power penalty Further scaling conceivable with further active element optimisation Competive system level figures of merit <1W per Gb/s path indicating <mw/gb/s driver power efficiency Extrapolated 6.4Tb/s aggregate capacity for 64 ports at xgb/s Encouraging for next generation integrated switch technologies Acknowledgements: EC FP7 Building the Optical Network in Europe (BONE) Network of Excellence & EC FP6 Marie Curie Chair award PAGE 12