Bary Arithmetic and Arithmetic Circuits-2 Lesson: Bary Arithmetic and Arithmetic Circuits-2 Lesson Developer: Dr. Divya Haridas College/ Department: Keshav Mahavidyalaya, University of Delhi 1 Institute of Lifelong Learng, University of Delhi
Table of Contents Bary Arithmetic and Arithmetic Circuits-2 Arithmetic Circuits-2 Chapter 2 Arithmetic Circuits 2.1 Chapters Objective 2.2 Introduction 2.3 Arithmetic Circuits 2.4 Adder 2.4.1 Half Adder 2.4.2 Full Adder 2.5 Subtractor 2.5.1 Half Subtractor 2.5.2 Full Subtractor 2.6 Adder/Subtractor 2.6.1 4 bit parallel Adder/Subtractor 2.7 Summary 2.8 Exercises 2.8.1 Subjective Questions 2.8.2 Fill the Blanks 2.8.3 Multiple Choice Questions 2.9 Glossary 2.10 References 2 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 2.1 Chapter Objectives Introduction to combational logic circuits. Design Half adder and understand it s workg. Design Full adder and to understand it s workg. To implement Bary addition usg Full adder Design Half Subtractor and understand it s workg. Design Full Subtractor and to understand it s workg. To implement Bary Subtraction usg Full Subtractor. Use full adders to implement four bit adder/subtractor 2.2 Introduction Logic circuits digital systems are broadly classified as A) Combational logic circuits B) Sequential logic circuits. A combational circuit is one whose output at any time is determed from the present combation of puts whereas the outputs of sequential circuits at any time depend not only on present value of puts but also on the past puts. Arithmetic circuits are the examples of combational circuits. I/P Combational O/P I/P Sequential Circuits O/P circuits Feedback 2.3 Arithmetic circuits Figure 1: Block diagram of combational and sequential circuits Arithmetic circuits are the circuits that perform arithmetic operations such as addition and subtraction, examples of arithmetic circuit are adders and subtractors. Adders are important digital systems which numerical data are processed. In this section adders, subtractor and adder/subtractor are troduced. 2.4 Adder 2.4.1 Half Adder The half adder accepts two bary digits on its put and provides two bary digits on its outputs, a sum bit and a carry bit. The logic symbol of half adder is given figure 2. Σ Input bits C A Σ Sum B out Carry Output bits Figure 2: Logic symbol of Half Adder 3 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 The truth table for half adder is given as Tip to memorize A B C out Σ 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 Σ Sum C out =Carry A & B are the put variables Whenever odd number of 1 is present truth table then sum will be high. When both puts are 1 then only carry will be high. From the above truth table the Boolean expression for sum and carry are S AB AB A B C AB A half adder can therefore be realized by usg one X-OR gate (for sum operation) and one AND gate (for carry operation). The logic circuit for half adder is shown figure 3 Figure 3: Circuit diagram of Half Adder The logic circuit for half adder can be implemented usg only NAND gates and is shown figure 4 4 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 Figure 4: Circuit diagram for half adder implemented usg NAND gates only The Boolean expression for sum and carry is given as: Sum AAB BAB A AB B AB A ( A B) B ( A B) AA AB BA BB AB AB Carry AB AB Try yourself Draw logic circuit for half adder usg only NOR gates only. Solution: 2.4.2 Full Adder A half adder has only two puts and there is no provision to add a carry comg from the lower bits even the case of 4 bit addition operation. For this another circuit is required which can add three bits simultaneously. A full adder is a combational logic circuit that performs the arithmetic addition of three put bits. The full adder accepts two put bits and put carry and generates a sum output and an output carry. So a full adder has three puts and two outputs. The logic symbol of full adder is given figure 5 Σ Input bits Input Carry A B Σ Sum Output bits C C out Carry 5 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 Figure 5: Logic symbol of full adder Two of the put variables denoted by A and B represent the two significant bits to be added. The third put C represents the carry from the previous lower significant position. Table 2 shows the truth table for a full adder. A B C C out Σ 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Σ Sum C =Input Carry C out =Output Carry A, B & C are the put variables Tip to memorize When the number of 1 s truth table is odd then the output for sum would be high. i.e it will follow a three put XOR gate function. Whenever the number of 1 s truth table appear more than once, then carry will be high. Karnaugh Map simplification for Full Adder Karnaugh Map for Sum C A B 0 C 1 AB 1 0 AB 0 1 A B 1 0 Boolean expression for sum = ABC ABC ABC ABC 6 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 Karnaugh Map for Carry C C A B 0 0 AB 0 1 AB 1 1 A B 0 1 Boolean expression for Carry = AB BC AC From the above Boolean expression we can design the logic circuit for full adder. Students are advised to first design the circuit on their own and then verify their results. Figure 6 shows the simplified circuit diagram of Full adder Figure 6: Logic circuit for Full adder Full adder can also be designed usg two half adders. Logic circuit of Full adder usg two half adders is given figure 7 7 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 Figure 7: Logic circuit of Full adder usg two half adders Complete logic circuit of figure 7 is given figure 8. Figure 8: Complete logic circuit of Full adder usg two half adders The sum output of the first half adder is the exclusive OR (X-OR) of two put variables A B. This output is fed as put for the second half adder. The second put variable for the second half adder is C (carry put). Therefore this put carry C must be exclusive ORed with A B, yieldg the equation for the sum Sum, A B C AB ABC AB A BA B C ABC ABC AB AB C ABC ABC ABC ABC AB C 8 Institute of Lifelong Learng, University of Delhi ABC ABC The output carry is a 1 when both puts to the first XOR gate are 1s or when both puts to the second XOR gate are 1s. The output carry of the full adder is therefore produced by the puts A ANDed with B and expression is given as A B ANDed with C. These two terms are ORed and the
Bary Arithmetic and Arithmetic Circuits-2 C Out AB AB AB ABC A B BC A B C AB AC A B C AB AC ABC AB A ABC AB A B C AB AB C ABC BC ABC ABC Try Yourself Design Full Adder usg universal NAND gate only. Design Full Adder usg universal NOR gate only. 9 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 Value Addition More complex adders Ripple-carry adder It is possible to create a logical circuit usg multiple full adders to add N-bit numbers. Each full adder puts a C, which is the C out of the previous adder. This kd of adder is called a ripple-carry adder, sce each carry bit "ripples" to the next full adder. The first (and only the first) full adder may be replaced by a half adder (under the assumption that C = 0). The layout of a ripple-carry adder is simple, which allows for fast design time; however, the ripple-carry adder is relatively slow, sce each full adder must wait for the carry bit to be calculated from the previous full adder. Carry-look ahead adder 4-bit adder with carry look ahead A carry-look ahead adder (CLA) is a type of adder used digital logic. A carry-look ahead adder improves speed by reducg the amount of time required to determe carry bits. It can be constructed with the simpler, but usually slower, ripple carry adder for which the carry bit is calculated alongside the sum bit, and each bit must wait until the previous carry has been calculated to beg calculatg its own result and carry bits. The carry-look ahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits. The Kogge-Stone adder and Brent-Kung adder are examples of this type of adder. Gerald Rosenberger of IBM filed for a patent on a modern bary carry-look ahead adder 1957. From Wikipedia, the free encyclopedia: http://en.wikipedia.org/wiki/adder_(electronics)#full_adder 10 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 2.5 Subtractor Trivia Half Subtractor: The circuit which will subtract two bits and produce a borrow and difference. Full Subtractor: The circuit which will subtract three bits and produce a borrow and difference. 2.5.1 Half Subtractor: The half subtractor needs two puts a muend and a subtrahend bit and output bits are borrow and difference. The logic symbol of the half subtractor is given figure 9. Input bits A B Borrow Difference Output bits The truth table of half subtractor is given as Figure 9: Logic symbol of Half subtractor A B Difference Borrow 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 A & B are the put variables The Boolean expression for difference and borrow can be written as Difference AB AB A B Borrow AB Students are advised to design logic circuits usg the above Boolean expression and verify their diagram (see figure 10) 11 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 Figure 10: Logic circuit for Half subtractor Half subtractor can be realized usg NAND gates only and is given figure 11 Figure 11: Logic circuit for Half subtractor usg NAND gates only Difference AAB BAB A AB B AB A A B BA B AB BA Borrow BAB BAB B A B AB 12 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 Try Yourself Design half subtractor usg NOR gates only and obta Boolean expression for difference & borrow Difference A A B B A B A A B B A B A A B BA B AB AB Borrow A A B A( A B) AB 2.5.2 Full Subtractor The half subtractor can be used only for LSB subtraction. If there is a borrow durg the subtraction of the LSBs, it affects the subtractions the next higher column; the subtrahend bit is subtracted from the muend bit, considerg the borrow from that column used for the subtraction the precedg column. Such a subtraction is performed by a full subtractor. It subtracts one bit (B) from another bit (A), when already there is a borrow B from the column for the subtraction the precedg column, and outputs the difference bit and the borrow bit required from the next column. The block diagram and the truth table of a full subtractor are shown below: A B B B out Difference 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 13 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 B =Input Borrow B out =Borrow A, B & B are the put variables Input bits Input Borrow A Difference B B B out Borrow Output bits Figure 12: Logic symbol of Full Subtractor The difference and borrow for full subtractor are evaluated as: Difference ABB B B ABB AB AB B AB AB A BB A B A B B ABB ABB Borrow ABB AB ABB A B B ABB ABB The logic diagram of a full subtractor, usg two half subtractor is shown figure 12 Figure 12: Block diagram of Full subtractor usg two half subtractors 14 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 The complete circuit diagram of Full subtractor is given figure 13. Figure 13: Complete circuit diagram of Full subtractor The full subtractor can also be realized Universal logic usg either only NAND gates and is shown figure 14. Figure 14: Complete circuit diagram of Full subtractor 2.6 Adder/Subtractor 2.6.1 4-bit Parallel Adder/subtractor The 4-bit parallel Adder/Subtractor can perform the operation of addition and subtraction. The logic circuit is given Figure 15 The circuit is used for addition or subtraction of 4 bit puts A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0. A B 8s 3 3 A B 2 2 4s A B 1 1 A B 0 0 2s 1s The circuit can either do addition or can do subtraction which is controlled by a control le, but both the operation can not be performed simultaneously. 15 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 Figure 15: 4-bit parallel Adder/Subtractor The truth table for the operation can be summarized as Control A B Y 0 0 0 0 0 1 1 1 1 0 1 1 1 0 When the control le is low i.e 0, then when a 0 is placed put A of the XOR gates, the bits pass through the XOR gate with no change. This can be verified from the truth table that when A is 0 the output is the same as that of the put present at the put B. With the control at 0, the puts available at the Full Adders (FA) are A 3 A 2 A 1 A 0, B 3 B 2 B 1 B 0 and C. The AND gate is disabled as one of the put is zero. Sce the output of the AND gate is zero 16 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 so there is no end carry C put for FA (1s). Thus with the control at 0 the units add the bary number A 3 A 2 A 1 A 0 to B 3 B 2 B 1 B 0. The result appears at the output dicators. When the control bit is 1 position this causes the XOR gate to act as an verter for the B puts to the full adders. From the truth table it can be verified that when control is 1 position. The output is complement of B put. The 1 at the control bit also activates the AND gate so that the formation from the 8s Full adder can take the end around carry le back to the 1s full adder. This subtractor, subtracts the bary put number B 3 B 2 B 1 B 0 from A 3 A 2 A 1 A 0. With 2 s complement method. Takg an example as Decimal Subtraction Bary Subtraction 10 1010-6 -0110 4 0100 With the control le at 1, the puts at FA as A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0. i.e. 1 s complement of put B 3 B 2 B 1 B 0 first take place. After 1 s complement of Muend and fally addg Muend and Subtrahend. 1010 1001 10011 End around carry + 1 0100 (difference) The difference appears bary form on the output dicators. 17 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 Addg mache An addg mache was a class of mechanical calculator, usually specialized for bookkeepg calculations. In the United States, the earliest addg maches were usually built to read dollars and cents. Addg maches were ubiquitous office equipment until they were phased out favor of calculators the 1970s and by personal computers begng about 1985. The older addg maches were rarely seen American office settgs by the year 2000. Blaise Pascal and Wilhelm Schickard were the two origal ventors of the mechanical calculator 1642; For Pascal this was an addg mache that could perform additions and subtractions directly and multiplication and divisions by repetitions, whilst Schickard's mache, vented several decades earlier was less functionally efficient but was supported by a mechanized form of multiplication tables. These two were followed by a strg of ventors and ventions leadg to those of Thomas de Colmar who launched the mechanical calculator dustry 1851 when he released his simplified arithmometer (it took him thirty years to refe his mache, patented 1820, to a simpler and more reliable form). However, they didn't ga widespread use until Dorr E. Felt started manufacturg his comptometer (1887) and Burroughs started the commercialization of differently conceived addg maches (1892) Addg mache for the Australian pound c.1910, note the complement numberg, and the columns set up for shillgs and pence An addg mache Older addg mache. Its mechanism is similar to a car odometer. https://en.wikipedia.org/wiki/addg_mache 18 Institute of Lifelong Learng, University of Delhi A manual addg mache manufactured the 1950s.
Bary Arithmetic and Arithmetic Circuits-2 2.7 Summary Summary A combational circuit is one whose output at any time is determed from the present combation of puts with no storage or memory capability. The truth table for half adder is summarized as A B C out Sum 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 The truth table for full adder is summarized as A B C C out Sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 The truth table for half subtractor is summarized as A B Difference Borrow 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 The truth table for full subtractor is summarized as A B B B out Difference 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 19 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 A 4-bit parallel Adder/Subtractor can be designed usg full adders only and can perform both addition and subtraction operation. 2.8 Exercises 2.8.1 Subjective Questions 1) Draw the circuit diagram of Half Adder usg NAND gate only. Describe the operation performed by Half adder. 2) Draw a block diagram of a full adder labelg all the puts and outputs. Write the truth table for full adder. 3) Draw the circuit diagram of Half Subtractor usg NAND gate only. Describe its operation. 4) Draw a block diagram of a full Subtractor labelg all the puts and outputs. Write the truth table for full Subtractor. 5) Draw the Half Adder circuit usg two put NOR gate. 6) Draw the Full Adder circuit usg two put NOR gate. 7) Draw the Half Subtractor circuit usg two put NOR gate. 8) Draw the Half Subtractor circuit usg two put NOR gate. 9) Draw a logic circuit that has three puts A, B and C and whose output will be high only when majority puts are high. 2.8.2 Fill the blank 1) A half adder circuit is used for addg only the. (1s, 2s, 4s, 8s) column of a bary addition problem. 2) Adder circuits are widely used. Section of microprocessor. 3) The output of full adder is Σ = 1, C out =1 when the puts are.. 4) The put of the full subtractor is A=B=B =1 then the output is given as.. Answers to the questions: 1) 1s 2) Arithmetic logic unit (ALU) 3) 1,1,1 4) Difference = 1 & Borrow = 1 2.8.3 Multiple Choice Questions 1) Full subtractor has. Inputs and. Outputs A) 2,3 B) 2, 2 20 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 C) 3, 2 D) 3, 3 2) An Adder/Subtractor can perform A) only addition B) both addition and subtraction C) only subtraction D) only multiplication 3) The sum of a Full adder can be represented by A) 2 put X-OR gate B) 2 put NAND gate C) 3 put NAND gate D) 3 put X-OR gate 4) The control le should be kept. For performg subtraction usg 4 bit adder/subtractor A) 0 B)1 C) 11 D) 10 Answers to multiple choice questions 1) 3,2 Justification: Full Subtractor has 3 puts A, B, B and 2 outputs namely difference and Borrow output 2) Both addition and subtraction Justification: An Adder/Subtractor is designed to add two numbers as well as subtract two numbers usg 2 s complement method. 3) 3 put X-OR gate Justification: Sum = ABC 4) 1 Justification: With Control le at 1, the Adder/subtractor subtracts two number usg 2 s complement method. 21 Institute of Lifelong Learng, University of Delhi
Bary Arithmetic and Arithmetic Circuits-2 2.9 Glossary Combational Logic Circuit A combational logic circuit is one whose output at any time is determed from the present combation of puts Half Adder A digital circuit that adds two bits and produces a sum and a carry. Full Adder A digital circuit which adds two bits and an put carry to produce a sum and an output carry Half Subtractor A digital circuit that subtracts two bits and produces difference and a borrow if any. Full Subtractor It subtracts one bit (B) from another bit (A), when already there is a borrow B from the column for the subtraction the precedg column, and outputs the difference bit and a borrow bit. 2.10 Reference Books: Digital Prciples & Applications, A.P.Malvo, D.P.Leach & Saha, 7th Ed., 2011, Tata McGraw Fundamentals of Digital Circuits, A. Anand Kumar, 2nd Edition, 2009, PHI Learng Pvt. Ltd. Digital Electronics, Prciples and applications, Roger L Tokheim, 2003, Tata McGraw Hill. Digital Systems: Prciples and Applications, R.J. Tocci, N.S.Widmer, 2001, PHI Learng. Digital Electronics, An troduction to theory and practice, W H Gothmann, 1982, PHI Learng. 22 Institute of Lifelong Learng, University of Delhi