Meghan van Wouw ( Christo Janse van Rensburg ( Blessing Buthelezi (

Similar documents
Final Examination Copyright reserved. Finale Eksamen Kopiereg voorbehou. Analoogelektronika ENE Junie 2008

Final Examination Copyright reserved. Finale Eksamen Kopiereg voorbehou. Analogue Electronics ENE June 2007

Homework Assignment 12

UNIVERSITEIT VAN PRETORIA / UNIVERSITY OF PRETORIA DEPT WISKUNDE EN TOEGEPASTE WISKUNDE DEPT OF MATHEMATICS AND APPLIED MATHEMATICS

Homework Assignment 07

Experiment 8 Frequency Response

Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B

Homework Assignment 11

EE 140 / EE 240A ANALOG INTEGRATED CIRCUITS FALL 2015 C. Nguyen PROBLEM SET #7

Homework Assignment 07

FAKULTEIT INGENIEURSWESE FACULTY OF ENGINEERING. Volpunte: Full marks: Instruksies / Instructions

Final Exam. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.1 μs. Estimate the 3 db bandwidth of the amplifier.

Analog Integrated Circuit Design Exercise 1

You will be asked to make the following statement and provide your signature on the top of your solutions.

Theory: The idea of this oscillator comes from the idea of positive feedback, which is described by Figure 6.1. Figure 6.1: Positive Feedback

Homework Assignment 10

BJT Amplifier. Superposition principle (linear amplifier)

UNIVERSITY OF PRETORIA Department of Mechanical and Aeronautical Engineering MACHINE DESIGN MOW323

55:041 Electronic Circuits The University of Iowa Fall Exam 3. Question 1 Unless stated otherwise, each question below is 1 point.

ECEN 5008: Analog IC Design. Final Exam

Lecture 34: Designing amplifiers, biasing, frequency response. Context

Field Effect Transistors

ECE-342 Test 1: Sep 27, :00-8:00, Closed Book. Name : SOLUTION

PHYSICS 330 LAB Operational Amplifier Frequency Response

Advanced Operational Amplifiers

MICROELECTRONIC CIRCUIT DESIGN Third Edition

Common-Source Amplifiers

PRIMARY SCHOOL GRADE 4 MATHEMATICS FORMAL ASSESSMENT TASK (FAT) 3. 3 JUNE 2016 EXAMINATIONS NAME & SURNAME GRADE 4 INSTRUCTIONS

Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs

Code: 9A Answer any FIVE questions All questions carry equal marks *****

Department of Mathematics and Applied Mathematics Departement Wiskunde en Toegepaste Wiskunde

Week 12: Output Stages, Frequency Response

You will be asked to make the following statement and provide your signature on the top of your solutions.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.

Filter Design, Active Filters & Review. EGR 220, Chapter 14.7, December 14, 2017

HOME ASSIGNMENT. Figure.Q3

Lecture 240 Cascode Op Amps (3/28/10) Page 240-1

Homework Assignment 10

MICROELECTRONIC CIRCUIT DESIGN Fifth Edition

Elektriese stroombane: Weerstand (Graad 11) *

Homework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26

ECEN 474/704 Lab 6: Differential Pairs

MOSFET Amplifier Design

Experiment 5 Single-Stage MOS Amplifiers

ELC224 Final Review (12/10/2009) Name:

UNIT 1 MULTI STAGE AMPLIFIES

Improving Amplifier Voltage Gain

Roll No. B.Tech. SEM I (CS-11, 12; ME-11, 12, 13, & 14) MID SEMESTER EXAMINATION, ELECTRONICS ENGINEERING (EEC-101)

Chapter 15 Goals. ac-coupled Amplifiers Example of a Three-Stage Amplifier

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers

COMPARISON OF THE MOSFET AND THE BJT:

University Of Pretoria

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1

ETIN25 Analogue IC Design. Laboratory Manual Lab 2

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

D n ox GS THN DS GS THN DS GS THN. D n ox GS THN DS GS THN DS GS THN

Common-source Amplifiers

EE 501 Lab 4 Design of two stage op amp with miller compensation

Chapter 12 Opertational Amplifier Circuits

EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design

CMOS Cascode Transconductance Amplifier

Dual, Current Feedback Low Power Op Amp AD812

PURPOSE: NOTE: Be sure to record ALL results in your laboratory notebook.

IOWA STATE UNIVERSITY. EE501 Project. Fully Differential Multi-Stage Op-Amp Design. Ryan Boesch 11/12/2008

LF155/LF156/LF355/LF356/LF357 JFET Input Operational Amplifiers

Design and Simulation of Low Voltage Operational Amplifier

GRADE 7 - FINAL ROUND QUESTIONS GRAAD 7 - FINALE RONDTE VRAE

Department of Mathematics and Applied Mathematics Departement Wiskunde en Toegepaste Wiskunde

ECE 363 FINAL (F16) 6 problems for 100 pts Problem #1: Fuel Pump Controller (18 pts)

LF353 Wide Bandwidth Dual JFET Input Operational Amplifier

PowerAmp Design. PowerAmp Design PAD117A RAIL TO RAIL OPERATIONAL AMPLIFIER

55:041 Electronic Circuits

Homework Assignment 13

Homework Assignment 13

EECE2412 Final Exam. with Solutions

Department of Mathematics and Applied Mathematics Departement Wiskunde en Toegepaste Wiskunde

ECE4902 C Lab 5 MOSFET Common Source Amplifier with Active Load Bandwidth of MOSFET Common Source Amplifier: Resistive Load / Active Load

Homework Assignment 06

PIN CONFIGURATIONS FEATURES APPLICATION ORDERING INFORMATION. FE, N Packages

ECE 3110: Engineering Electronics II Fall Final Exam. Dec. 16, 8:00-10:00am. Name: (78 points total)

Homework Assignment 06

OPERATIONAL AMPLIFIERS (OP-AMPS) II

Homework Assignment True or false. For both the inverting and noninverting op-amp configurations, V OS results in

Solid State Devices & Circuits. 18. Advanced Techniques

LF411 Low Offset, Low Drift JFET Input Operational Amplifier

Homework Assignment 03 Solution

Lab 2: Discrete BJT Op-Amps (Part I)

ENEE 307 Laboratory#2 (n-mosfet, p-mosfet, and a single n-mosfet amplifier in the common source configuration)

LM148/LM248/LM348 Quad 741 Op Amps

Experiment No. 9 DESIGN AND CHARACTERISTICS OF COMMON BASE AND COMMON COLLECTOR AMPLIFIERS

LINEAR IC APPLICATIONS

Single-Stage Integrated- Circuit Amplifiers

6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers

Lecture 040 CE and CS Output Stages (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

ECE 2C Final Exam. June 8, 2010

PowerAmp Design. PowerAmp Design PAD135 COMPACT HIGH VOLATGE OP AMP

ECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers

PowerAmp Design. PowerAmp Design PAD541 COMPACT POWER OP AMP

TL082 Wide Bandwidth Dual JFET Input Operational Amplifier

Op-Amp Simulation Part II

Transcription:

Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Finale Eksamen Kopiereg voorbehou Analoogelektronika ENE310 08 Junie 2010 Toetsinligting / Test information: Department of Electrical, Electronic and Computer Engineering Final Examination Copyright reserved Analogue Electronics ENE310 08 June 2010 Maksimum punte / Maximum marks: 100 Volpunte / Full marks: 100 Duur van vraestel: Duration of paper: 180 minute 180 minutes Eksamineringsbeplanning: n Addisionele 10 minute sal aan die begin van die eksaminering beskikbaar gestel word. Gedurende hierdie tydperk mag kandidate nie op die antwoordstelle skryf nie. Test planning: An additional 10 minutes will be availed at the start of the examination. During this period, candidates may not make any markings on the answer scripts. Oopboek / toeboek: Open / closed book: Oop (Enige materiaal) Open (Any material) Geen toestel met n kommunikasiepoort (van enige aard) word toegelaat nie. Any device with a communication port (of whatsoever kind) may not be used. BELANGRIK- IMPORTANT 1. Die eksamenregulasies van die Universiteit van Pretoria geld. The test & examination regulations of the University of Pretoria apply. 2. Vrae moet in onuitwisbare ink beantwoord word. Geen antwoorde wat in potlood geskryf is sal gemerk word nie. Questions must be answered in indelible ink. Answers in pencil will not be marked. 3. Beantwoord al die vrae en skryf u antwoorde in u Antwoordboek neer. Geen vrae mag op die vraestel beantwoord word nie. Answer all the questions and write the answers in the supplied Answer Book. No questions are to be answered on the Question Paper. 4. Toon alle berekeninge waar van toepassing. Geen punte sal toegeken word vir korrekte antwoorde sonder berekeninge om dit te staaf nie. Show all calculations where applicable. No marks will be given for correct answers without calculations/reasoning to support them. 5. Gebruik duidelik geregverdigde & kundige Ingenieursbenaderings (en/of aannames) waar/indien van toepassing. Use clearly justified & educated Engineering approximations (and/or stated assumptions) where/as appropriate. Dosent: Lecturer: Dr Saurabh Sinha ( ssinha@ieee.org) Eksterne Eksaminator: External examiner: Johan Schoeman ( johan.schoeman@eng.up.ac.za) Vertaler (Engels Afrikaans): Translator (English Afrikaans): Antonie Alberts ( ac.alberts@ieee.org) Beoordeelaar (Vraag 1) Evaluator (Question 1) Beoordeelaar (Vraag 2) Evaluator (Question 2) Beoordeelaar (Vraag 3) Evaluator (Question 3) Beoordeelaar (Vraag 4) Evaluator (Question 4) Beoordeelaar (Vraag 5) Evaluator (Question 5) Beoordeelaar (Vraag 6) Evaluator (Question 6) Meghan van Wouw ( meghanvanwouw@gmail.com) Christo Janse van Rensburg ( christojvr@ieee.org) Blessing Buthelezi ( blessing.buthelezi@gmail.com) Richard Balson ( richard.balson@gmail.com) Antonie Alberts ( ac.alberts@ieee.org) Johan Venter ( johan.venter@tuks.co.za) Groephoof: Ek bevestig dat die vraestel die uitkomstes toets soos gespesifiseer in die studiehandleiding. Group head: I confirm that the question paper evaluates the outcomes as specified in the study guide. Groephoof: Group Head (Acting): Dr Saurabh Sinha Handtekening: Signature: Totale aantal bladsye (hierdie blad ingesluit) / Total number of pages (including this page): 10

Study Theme Notional hours % (Exam) Question(s) 1: Introduction to amplifier circuits 18 11 1 2: Bipolar transistor amplifiers 26 15 5 3: Field effect transistor amplifiers 22 14 2 4: Differential and multistage amplifiers 10 6 3 5: Amplifier frequency response 34 21 2; 4 6: Feedback 30 19 5 7: Output stages and power amplifiers 22 14 6 162 100 % 100 marks AFRIKAANS AGTER OP 2

Question 1 [11] 1.1 Determine the output voltage, v O, of the 4 bit weighted resistor digital to analogue converter 1.1.1 [2] if the input signal is 0110, and 1.1.2 [2] if the input signal changes to 1001. For this problem, assume R F = 10 kω. v o 1.2 [4] The figure below shows a phototransistor that converts light intensity into an output current. The transistor must be biased as shown. The transistor output versus input characteristics are shown. Light intensity Design the current to voltage converter shown below (choose values for R F and V E ) to produce an output voltage between 0 and 8 V for an input light intensity between 0 and 20 mw/cm 2. Power supplies of ±10 V are available. v o V E AFRIKAANS AGTER OP 3

1.3.1 [2] The circuit shown below is an analogue voltmeter in which the meter reading is directly proportional to the input voltage, v I. Design the circuit (choose a value for R) such that a 1 ma fullscale reading corresponds to v I = 10 V. Resistance, R 2 corresponds to the meter resistance, and R 1 corresponds to the source resistance. v o 1.3.2 [1] Does the value of the source resistance, R 1, influence the design of the analogue voltmeter shown above? AFRIKAANS AGTER OP 4

Question 2 [25] Consider the amplifier shown below. V SS r in v o Power supplies: V DD = 3 V and V SS = 3 V V DD r out The PMOS transistor parameters: V TP = ½ V. K P = ½ μ p C ox (W/L) = 0.8 ma/v 2 and λ = 0.01 /V C gs = 2.5 pf C gd = 0.5 pf C ds = 0.1 pf The load resistor, R L = 2 kω. 2.1 [6] Design (choose values for R S and R D ) the circuit such that I D = ¼ ma and V SD = 1.5 V. Using appendix A, choose standard (5 %) resistors. 2.2 [3] Determine the small signal gain, A v = v o /v i. Express the gain in db. 2.3 Determine the values of the small signal resistances: 2.3.1 [1]r in 2.3.2 [2] r out 2.4 [1] Determine the total dc power delivered by the voltage sources, V SS and V DD. 2.5 [1] Determine the dc power dissipated by the transistor, P Q. 2.6 Assume C S = 47 µf and C C1 = C C2 = 10 µf 2.6.1 [3] Determine the high frequency cut off for the circuit, f H. 2.6.2 [4]Determine the low frequency cut off for the circuit, f L. 2.6.3 [4] Sketch the Bode magnitude and phase plot. AFRIKAANS AGTER OP 5

Question 3 [6] Consider the differential amplifier shown below. Transistor parameters are V TN = 0.8 V, K n = 0.4 ma/v 2, and λ = 0 Assume the transistors are matched. 3.1 [4] Design (choose R D ) the differential amplifier such that v O = v D1 v D2 = 1 V, when v 1 = 50 mv and v 2 = 50 mv. 3.2 [2] Determine the maximum common mode input voltage, v i,cm. AFRIKAANS AGTER OP 6

Question 4 [10] 4.1 [4] Design the active filter in the figure shown below such that the input resistance, r in is 20 kω, the low frequency gain is 15, and the 3 db frequency is 5 khz. Assume an ideal operational amplifier. r in v o 4.2 [6] Sketch the Bode magnitude and phase plot. AFRIKAANS AGTER OP 7

Question 5 [34] 5.1 Consider the series shunt feedback circuit below. r o,fb r i,fb v o Transistor parameters: h fe = 120, V BE(on) = 0.7 V and V A 5.1.1 [9] Determine the dc operating currents (I C ) for the three transistors Q 1, Q 2, and Q 3. 5.1.2 [6] Determine the ac small signal parameters (r π and g m ) for the three transistors Q 1, Q 2, and Q 3. 5.1.3 [4] Determine the open loop gain, A vo. 5.1.4 [3] Determine the feedback factor, β. 5.1.5 [1] Determine the amount of feedback, 1 + A vo β. 5.1.6 [2] Determine the closed loop small signal voltage gain, A vfb = v o /v i. 5.1.7 [2] Determine the input resistance of the closed loop feedback configuration, r i,fb. 5.1.8 [2] Determine the output resistance of the closed loop feedback configuration, r o,fb. 5.2 [5] A feedback amplifier has a low frequency open loop gain of 4000 and three poles, f P1 = 400 khz, f P2 = 4 MHz and f P3 = 40 MHz. A dominant pole is to be inserted such that the phase margin is 60. Assuming the original poles remain fixed, determine the dominant pole frequency. AFRIKAANS AGTER OP 8

Question 6 [14] 6.1 Consider the ideal class B output stage shown below. v o The output stage is to deliver 50 W of average power to a 24 Ω load for a symmetrical input sine wave. Assume the supply voltages for ±n volts, where n is an integer. 6.1.1 [3] The power supply voltages are to be at least 3 V greater than the maximum output voltage. Determine the power supply voltages. 6.1.2 [2] Determine the peak current in each device. 6.1.3 [2] Determine the efficiency of the amplifier. 6.2 A particular transistor is rated for a maximum power dissipation of 60 W if the case temperature is 25 C. Above 25 C, the allowed power dissipation is reduced by 0.5 W/ C. 6.2.1 [3] Sketch the power derating curve. 6.2.2 [2] Determine the maximum allowed junction temperature. 6.2.3 [2] Determine the thermal resistance, Θ dev air (in C/W). AFRIKAANS AGTER OP 9

Appendix A AFRIKAANS AGTER OP 10

Studentenommer / Student Number Volle Voorname / Full Name QUESTION/VRAAG 1 v o/u 1.1.1 [2] 1.1.2 [2] Beoordelaar 1 (Vraag 1) Evaluator 1 (Question 1) Meghan van Wouw ( meghanvanwouw@gmail.com)

1.2 v o V E [4] 1.3.1 [2] 1.3.2 [1] Beoordelaar 1 (Vraag 1) Evaluator 1 (Question 1) Meghan van Wouw ( meghanvanwouw@gmail.com) Total/Totaal: [11]

Studentenommer / Student Number Volle Voorname / Full Name QUESTION/VRAAG 2 r in r out 2.1 [6] Beoordelaar 2 (Vraag 2) Evaluator 2 (Question 2) Christo Janse van Rensburg ( christojvr@ieee.org)

2.2 [3] 2.3.1 [1] 2.3.2 [2] 2.4 [1] Beoordelaar 2 (Vraag 2) Evaluator 2 (Question 2) Christo Janse van Rensburg ( christojvr@ieee.org)

Studentenommer / Student Number Volle Voorname / Full Name 2.5 [1] 2.6.1 [3] 2.6.2 [4] Beoordelaar 2 (Vraag 2) Evaluator 2 (Question 2) Christo Janse van Rensburg ( christojvr@ieee.org)

2.6.3 Ajω ( ) db f L f H f [Hz] [2] A( jω) f L f H f [Hz] [2] Beoordelaar 2 (Vraag 2) Evaluator 2 (Question 2) Christo Janse van Rensburg ( christojvr@ieee.org) Total/Totaal: [25]

Studentenommer / Student Number Volle Voorname / Full Name QUESTION/VRAAG 3 3.1 [4] Beoordelaar 3 (Vraag 3) Evaluator 3 (Question 3) Blessing Buthelezi ( Blessing.Buthelezi@gmail.com)

3.2 [2] Beoordelaar 3 (Vraag 3) Evaluator 3 (Question 3) Blessing Buthelezi ( Blessing.Buthelezi@gmail.com) Total/Totaal: [6]

Studentenommer / Student Number Volle Voorname / Full Name QUESTION/VRAAG 4 r in v o 4.1 [4] Beoordelaar 4 (Vraag 4) Evaluator 4 (Question 4) Richard Balson ( Richard.Balson@gmail.com)

4.2 Ajω ( ) db f L f H f [Hz] [3] A( jω) f L f H f [Hz] [3] Beoordelaar 4 (Vraag 4) Evaluator 4 (Question 4) Richard Balson ( Richard.Balson@gmail.com) Total/Totaal: [10]

Studentenommer / Student Number Volle Voorname / Full Name QUESTION/VRAAG 5 r o,fb r i,fb v o 5.1.1 Beoordelaar 5 (Vraag 5) Evaluator 5 (Question 5) Antonie Alberts ( AC.Alberts@ieee.org)

[9] Beoordelaar 5 (Vraag 5) Evaluator 5 (Question 5) Antonie Alberts ( AC.Alberts@ieee.org)

Studentenommer / Student Number Volle Voorname / Full Name 5.1.2 [6] Beoordelaar 5 (Vraag 5) Evaluator 5 (Question 5) Antonie Alberts ( AC.Alberts@ieee.org)

5.1.3 [4] 5.1.4 [3] Beoordelaar 5 (Vraag 5) Evaluator 5 (Question 5) Antonie Alberts ( AC.Alberts@ieee.org)

Studentenommer / Student Number Volle Voorname / Full Name 5.1.5 [1] 5.1.6 [2] 5.1.7 [2] 5.1.8 [2] Beoordelaar 5 (Vraag 5) Evaluator 5 (Question 5) Antonie Alberts ( AC.Alberts@ieee.org)

5.2 [5] Beoordelaar 5 (Vraag 5) Evaluator 5 (Question 5) Antonie Alberts ( AC.Alberts@ieee.org) Total/Totaal: [34]

Studentenommer / Student Number Volle Voorname / Full Name QUESTION/VRAAG 6 v o/u 6.1.1 [3] Beoordelaar 6 (Vraag 6) Evaluator 6 (Question 6) Johan Venter ( johan.venter@tuks.co.za)

6.1.2 [2] 6.1.3 [2] Beoordelaar 6 (Vraag 6) Evaluator 6 (Question 6) Johan Venter ( johan.venter@tuks.co.za)

Studentenommer / Student Number Volle Voorname / Full Name 6.2.1 [3] 6.2.2 [2] Beoordelaar 6 (Vraag 6) Evaluator 6 (Question 6) Johan Venter ( johan.venter@tuks.co.za)

6.2.3 [2] Beoordelaar 6 (Vraag 6) Evaluator 6 (Question 6) Johan Venter ( johan.venter@tuks.co.za) Total/Totaal: [14]