CONTINUOUS-TIME (CT) ΔΣ modulators have gained

530 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 56, NO. 7, JULY 009 DT Modeling of Clock Phase-Noise Effects in LP CT ΔΣ ADCs With RZ Feedback Martin Anderson, Member, IEEE, and Lars Sundström, Member, IEEE Abstract The performance of continuous-time (CT) ΔΣ modulators is limited by their sensitivity to clock phase noise (PN). The clock PN-induced in-band noise (IBN) is dependent on the magnitude and frequency of both the desired in-band signals and the out-of-band signals, as well as the shape of the clock PN spectrum. This brief presents a discrete-time (DT) model of the dominant clock PN-induced errors. It enables fast and accurate simulations of the clock PN effects with arbitrary input signals, PN spectra, and noise-transfer functions. The model has been verified by CT simulations and measurements on a second-order low-pass CT ΔΣ modulator with return-to-zero feedback. The flexibility and usefulness of the DT model are demonstrated, and the two dominant clock PN effects are compared by means of simulations with orthogonal frequency-division multiplexing input signals and various PN specifications. Index Terms Analog-to-digital conversion (ADC), behavioral modeling, clock jitter, delta sigma modulation, phase noise (PN). I. INTRODUCTION CONTINUOUS-TIME (CT) ΔΣ modulators have gained popularity in battery-powered applications due to speed/ power advantages over their discrete-time (DT) counterparts and inherent antialias filtering [1]. However, different forms of clock jitter limit their performance [] [5]. As opposed to Nyquist-rate analog-to-digital converters (ADCs) and DT ΔΣ modulators, the time discretization in a CT modulator occurs at the quantizer input, which is the point of maximum error suppression. However, in the presence of phase noise (PN) on the digital-to-analog converter (DAC) clock, the timing of each rising and falling edge of the DAC output pulse deviates from the ideal timing. This induces a noise signal, which consists of a sequence of narrow pulses whose width is proportional to the timing error. This noise signal is multiplied in the time domain by the DAC input signal, which contains both the ADC input signal and the shaped quantization noise (QN). Since the error is induced in the feedback DAC, it can reach the ADC output without noise shaping and can therefore significantly degrade the SNR. Previous works show that the SNR degradation due to DAC clock PN is mainly Manuscript received March 5, 008; revised November 1, 008. First published May 7, 009; current version published July 17, 009. This work was supported by Vinnova and Ericsson AB. This paper was recommended by Associate Editor P. P. Sotiriadis. M. Anderson is with the Department of Electrical and Information Technology, Lund University, 1 00 Lund, Sweden (e-mail: martin.anderson@ ieee.org). L. Sundström is with Ericsson AB, 1 83 Lund, Sweden (e-mail: lars.s. sundstrom@ericsson.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.009.00950 Fig. 1. PW and PP errors caused by the sampling clock PN. caused by two mechanisms: 1) by modulation with the ADC input signal and ) by spreading the shaped QN into the signal band, both for nonreturn-to-zero (NRZ) [5] and return-to-zero (RZ) [], [4] feedback pulses. Unfortunately, the exact modeling of the PN-induced noise in the DAC is not amenable to a simple analytical treatment [5]. Instead, models where the pulsewidth (PW) and pulseposition (PP) variations, as shown in Fig. 1, caused by the clock PN are transferred to equivalent amplitude modulation of the feedback pulse have been suggested [], [4] [6]. When studying the effect of Gaussian PP and PW errors, it was found that the PW errors are dominating, because the PP errors are first-order noise shaped [7], [8]. However, when considering the close-in noise of a voltage-controlled oscillator (VCO), the result is that the modulation with strong sinusoidal in-band signals limits the achievable SNR [], [4]. The modulation with the in-band signals shows great similarities with a samplingtime noise of a traditional sample-and-hold circuit [4]. This brief presents a DT model, which extends previous work by deriving the PW and PP variations from an arbitrary clock PN and considering the modulation with arbitrary input signals and QN spectra. This is practically relevant since the PN of a phase-locked loop (PLL) is quite different from that of the VCO itself [9], and in many applications such as wireless receivers, the input signals are nonsinusoidal. Since the model only needs DT simulation, the simulation time is decreased by two to three orders of magnitude compared with simulations of CT modulator models in Spectre. In Section II, the DT modeling principles are described. Section III presents a simulation and measurement technique, where a systematic PN enables the study of the PN sensitivity for different PN frequencies separately. Using this technique, the DT model is verified against Spectre simulations on a CT modulator model and by measurements on an implemented 400 MHz second-order low-pass (LP) CT modulator with RZ 1549-7747/$5.00 009 IEEE

ANDERSON AND SUNDSTRÖM: DT MODELING OF CLOCK PN EFFECTS IN LP CT ΔΣ ADCs WITH RZ FEEDBACK 531 Fig.. DT PN model overview. Fig. 3. S pp/s t (4) and S pw/s t (6) versus f o for β α =0.5 and 0.75. feedback. The simulations on the DT model show excellent agreement with both Spectre simulations and measurements. Finally, in Section IV, the DT model is used to compare the in-band noise (IBN) power caused by PP and PW variations by simulation of a fifth-order modulator for different PN specifications and with orthogonal frequency-division multiplexing (OFDM)-modulated input signals. II. CLOCK PN MODEL This section presents the DT PN modeling principles. First, the PW and PP variations of the feedback pulses are derived from an arbitrary PN specification. Then, as shown in Fig., the time-domain feedback pulse errors are converted to DT amplitude errors that are referred to the input of the modulator. The IBN caused by each noise component can thus be separately studied, or the total IBN, including the QN, can be evaluated at the DT modulator output. Both the effects of the PP and PW variations are estimated from an arbitrary DAC input bit stream and an arbitrary PN spectrum. Thus, no time-consuming simulations of CT modulator models are necessary. A. Clock PN and Time Jitter Effects This section describes the relation between the clock PN and the PW and PP variations used in the DT model. The signal provided as the reference for the square-wave sampling clock may be expressed as a periodic sinusoidal signal with amplitude A clk (t) and instantaneous phase θ clk (t), i.e., s clk (t) =A clk (t)cos(θ clk (t)) (1) where θ clk (t) =ω s t + δ θ (t), w s =πf s is the ideal radian frequency, f s is the ideal sampling clock frequency, and δ θ (t) is a time-dependent phase deviation (i.e. PN). The phase deviation can also be expressed as a random time delay (denoted jitter) δ t (t) of the clock signal reference, i.e., s clk (t) =A clk (t)cos(ω s (t + δ t (t))) () since the phase deviations are related to the time jitter through δ θ (t) =ω s δ t (t). The PP variations δ pp [n] are defined as the deviation from the ideal center of gravity of the feedback pulses, i.e., δ pp [n] = δ t ((n + α)t s )+δ t ((n + β)t s ) (3) where 0 <α<β 1define the ideal timing of the rising and falling edges (see Fig. 1). Since the two time jitter noise terms are due to the same noise source, they are correlated. The transfer function resulting from this double sampling and summation can also be represented in the frequency domain [10], i.e., S pp (f o ) S t (f o ) = 1 ) (1+e jω o(β α)t s where f o is the offset frequency from the ideal sampling clock frequency f s, ω o =πf o, S pp is the power spectral density (PSD) of the PP variations, and S t is the PSD of the time jitter. The PW variations δ pw [n] are modeled by subtracting the instantaneous values of the time jitter existing at the falling and rising edges of the feedback pulse, i.e., t =(n + β)t s and t =(n + α)t s, respectively. Thus resulting in (4) δ pw [n] =δ t ((n + β)t s ) δ t ((n + α)t s ) (5) S pw (f o ) S t (f o ) = 1 e jω o (β α)t s. (6) The transfer functions from the PN spectral density to the PP and PW spectral densities, as given by (4) and (6), are plotted in Fig. 3 for β α of 0.5 and 0.75, respectively. There are three important implications of (5) and (6): First, the PN at f o = k f s /(β α) will be canceled (k is an integer) and will therefore create no PW variations. Second, (6) is peaking at f o =(0.5+k) f s /(β α), amplifying the PN there by 6 db. Third, sampling of the continuous noise causes aliasing of its spectrum, which concentrates all its power below f s /. B. PW Noise It is well known that it is the integral (area) of the feedback pulse over one sampling period that is most important in LP CT modulators [1], [4], [8]. The reason is that the output of the first integrator at the sampling instants is more significant than the exact integration over time in other integrators and that the signal is only dependent on the area of the feedback pulse. For a one-bit RZ feedback pulse, the integrated area error in the DAC can be expressed as δ A [n] =v d [n] Δ δ pw [n] (7) where Δ is the quantization step height and v d [n] is the modulator output signal. The equivalent input-referred DT amplitude error sequence PW noise (PWN)[n], which produces the

53 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 56, NO. 7, JULY 009 same error voltage at the integrator output at t = nt s, can be written as PWN[n] =v d [n] Δ δpw[n] T s al c L (8) where a L and c L, as shown in Fig. 1, are the feedback and input coefficients of the outermost feedback branch of the CT loop filter, respectively. Multiplication by v d [n] accounts for the modulation with actual DAC input signals. The PWN model is valid for arbitrary input signals, noise-transfer functions (NTFs), and PN specifications, since no assumptions were made with regard to the DAC input v d [n] or the time jitter δ t (t). Fig. 4. VCO PN spectrum used in the two-tone simulations shown in Fig. 5. C. PP Noise As shown in Fig. 3, the PN at small offset frequencies mainly causes PP variations. The PP variations described by (3) represent random delays of the feedback pulses. Since the PP error integrated over one clock period is equal to zero, the error is not stored in the outermost integrator Int L. However, within the clock period, the Int L output will deviate from its ideal shape, and this deviation will be integrated continuously by the subsequent integrators. This effect can be modeled as an area error of the input signal to Int L 1, which is equal to Fig. 5. 3 768-point fast Fourier transform (FFT; with a Hann window) from VCO PN simulations of the DT model in MATLAB and the corresponding CT model in Spectre. δ A,L 1 [n] = v d [n] Δ δ pp [n] (β α)t s a L f s. (9) Assuming that the errors in the loop filter back end can be neglected, a DT PP noise (PPN) sequence for the Int L 1 input can be calculated [7], in a similar way as that for the PW error, resulting in PPN L 1 [n] = v d [n] Δ δpp[n] a L (β α). (10) T s To refer this error to the input, it has to be high-pass filtered by the function (1 z 1 ), which results in PPN[n] = 1 (PPN L 1 [n] PPN L 1 [n 1]). (11) c L These results agree with the results of the theoretical investigation of the PP errors presented in [8]. III. DT MODEL VERIFICATION The presented DT model has been verified by simulations on a CT behavioral model in Spectre and by measurements on a second-order LP CT ΔΣ modulator circuit with one-bit RZ feedback (α = 0.5 and β = 1). The DT-to-CT transformation was performed using impulse-invariant transformation [1]. The clock frequency used in this section is 640 MHz, and the signal bandwidth is taken to be the wideband code-division multipleaccess baseband bandwidth of 1.9 MHz. A. VCO PN Simulation Both the CT and DT models of the second-order modulator were simulated using a clock derived from the single-sideband Fig. 6. Systematic PN simulation and measurement setup. (SSB) VCO PN spectrum shown in Fig. 4. The PSD starts at L{1 khz} 5 dbc/hz and has a 0 db/dec roll-off. The input signal was two 11 dbfs tones at 1. and 3.6 MHz. To perform DT simulations with an arbitrary PN spectrum specified in the frequency domain, the PN spectrum is first converted to a time jitter for every clock edge, i.e., δ t (n + α)t s and δ t (n + β)t s, using inverse fast Fourier transform (ifft in MATLAB). Thereafter, the clock edge time deviations are converted to PP and PW variations using (3) and (5). Finally, these are used in (9) (11) to generate the PPN and in (8) to generate the PWN for the DT model simulation. Fig. 5 shows the output spectra from the Spectre simulation of the CT model and the PPN and PWN sequences from the DT model simulation. The level of modulation with the input tones is in good agreement with the PPN, whereas the white noise level is accurately modeled by the PWN. B. Systematic PN Simulations By using a single tone as an artificial systematic PN, it is possible to separately study the effect of different PN frequencies. One way to generate a perturbed clock signal reference s clk (t), which can also be easily arranged in measurements, is to simply add a sinusoid s n (t) =A n cos(ω n t) to the sampling sinusoid s s (t) =A s cos(ω s t), as shown in Fig. 6, i.e., s clk (t) =s s (t)+s n (t). (1)

ANDERSON AND SUNDSTRÖM: DT MODELING OF CLOCK PN EFFECTS IN LP CT ΔΣ ADCs WITH RZ FEEDBACK 533 Fig. 8. Measured output spectrum for the modulator circuit with a clean clock. Fig. 7. Integrated IBN due to the (a) wide-band PN and (b) close-in PN from f n sweep simulations of the DT model compared with Spectre simulations on the corresponding CT model. A n/a s = 0 dbc. f s = 640 MHz. f c 1.4 MHz. The perturbation signal s n (t) will create both phase and amplitude modulations of the clock signal. It can be shown that the resulting phase perturbation, which is equivalent to the angle between the ideal clock signal s s (t) and the perturbed clock signal s clk (t), is ( ) sin(θ n θ s ) δ θ (t) = arctan A s (13) A n +cos(θ n θ s ) where θ n =πf n t, and θ s =πf s t.fora n A s, δ t can be approximated by δ t (t) T s A n sin(θ n θ s ). (14) π A s Thus, the time jitter from the described setup is approximately sinusoidal and varies with the offset frequency f o = f n f s. By using the phase perturbations from (13) and δ t (t) = δ θ (t)/ω s as input to the DT model, the IBN from both the PPN and the PWN can be accurately predicted. Fig. 7 shows the resulting IBN due to the PWN and the PPN when sweeping the perturbation tone frequency f n. The input signal v c was a 7 dbfs single tone at f c 1.4 MHz. For comparison, a CT behavioral model was simulated in Spectre with the same setup. The CT and DT simulations agree very well for both the wideband and the close-in PN. It is evident that the high-frequency PN is folded down and modulates with the QN to create the IBN. The simulations also confirm that no PWN is created by the PN at offset frequencies close to f o = k f s /(β α) (at even multiples of the clock frequency since β α =0.5 was used). The reason for the noise peaks for offset frequencies close to odd multiples of the clock frequency is that PW errors at these frequencies modulate with the strong input tone, i.e., v c. C. Systematic PN Measurements The single-tone PN method has also been verified by measurements. The CT ΔΣ modulator used in the measurement Fig. 9. Measured and simulated IBN from f n sweep for the modulator circuit. A n/a s = 0 dbc. was implemented in a 90-nm RF-CMOS process with a 1. V supply voltage. Its second-order loop filter contains two cascaded RC integrators, and the feedback DACs are of traditional SI type (RZ with α =0.5, β =1, and a L /c L =). The modulator was designed for a clock frequency of 400 MHz. Fig. 8 shows a typical output spectrum from a measurement with a dbfs input tone at 1.49 MHz, when a clean clock is used. The measured IBN due to circuit noise is 77 dbfs. The clock PN sensitivity was investigated by using the single-tone PN method, as previously described in this brief. The frequency of a clock PN tone at 0 dbc was swept, and the IBN was recorded. A DT model simulation was performed for comparison using the actual modulator output sequence from the measurement, i.e., v d [n], as input to (7). The measurement results, along with the DT model simulation results, are shown in Fig. 9. The simulation and measurements agree very well. At small offset frequencies, other noise sources are limiting the measured IBN. It should also be noted that due to the small input signal amplitude, the PWN is dominating the PN-induced noise in the presented measurement. IV. DT MODEL SIMULATIONS This section presents DT simulation examples that demonstrate the usefulness of the DT model and compare the IBN caused by the PPN and the PWN for different input signals and PN spectra. A fifth-order one-bit LP modulator clocked at 640 MHz is used. The target bandwidth is a 9 MHz baseband bandwidth, resulting in a low oversampling ratio (OSR) of 35. The PPN is mainly dependent on the clock PN at small f o, whereas the PWN is mainly caused by the wideband clock PN at f o close to odd multiples of f s. When clocking with a PLL, the dominating time-jitter effect is therefore determined by the level of the VCO PN, as well as the ratio of the closein and the wideband PN of the PLL [9]. Here, the simulations are performed using PN spectra 1 3, as shown in Fig. 10, to

534 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 56, NO. 7, JULY 009 lower for the wideband signals and the out-of-band sinusoidals than that for the in-band sinusoidals. In most of the simulations presented here, the PWN is dominating over the PPN. The main reason for this is that for a typical PLL, the VCO PN with a 0 db/dec roll-off levels out to a white noise floor, which increases the PWN power. Fig. 10. PN PSD specifications S t used in the DT simulation examples. Fig. 11. 3 768-point FFT (with a Hann window) from a DT simulation of a fifth-order ΔΣ modulator with a 17-dBFS OFDM input signal and a sampling clock derived from PN spectrum 1. TABLE I PN SIMULATIONS FOR A FIFTH-ORDER LP CT ΔΣ MODULATOR WITH OSR =35, f s = 640 MHz, AND BASEBAND BW =9MHz V. C ONCLUSION A DT model of the two dominant effects (PPN and PWN) of the clock PN, in LP CT ΔΣ modulators with RZ feedback, has been developed. It has been verified by means of CT Spectre simulations and measurements on a second-order LP CT modulator circuit. The DT simulations agree well with CT simulations and measurements. The relation between the PPN and the PWN is determined by the spectral shape of the clock PN, the input signal, and the NTF. The presented DT model simulates these effects in a fast and accurate manner. The PWN is caused by the wideband PN rather than the close-in noise that mainly caused the PPN. The PPN power is lower for wideband modulated input signals and narrow outof-band blockers, as compared with in-band sinusoidal signals. The PPN power is therefore reduced relative to the PWN power for such input signals. ACKNOWLEDGMENT The authors would like to thank Dr. P. Andreani for his perspicacious suggestions on how to improve this brief. compare the different levels for the wideband noise floor. The level of the VCO PN was L{1 MHz} 10 dbc/hz. The PLL bandwidth was assumed to be 100 khz, giving a close-in noise level of L{ 100 khz} = 100 dbc/hz. In addition, the PN spectrum of the PLL used to clock the high-performance CT modulator presented in [11] is included as an example of a practical situation. The spectral density and power of the input signal are important for the PPN. Here, sinusoidal and modulated (OFDM) input signals are simulated. We also simulate the effect of strong sinusoidal inputs slightly above the upper band edge (representing narrow-band blockers). The modulated input signals have a higher peak-to-average ratio than a sinusoidal input. Therefore, the power of these signals has to be lower than that for the sinusoidal signal to avoid overloading the modulator. Fig. 11 shows the output spectra from DT simulations of the fifth-order modulator, with the clock PN derived from PN spectrum 1, as shown in Fig. 10. The input signal is a 17 dbfs OFDM signal with a 9 MHz baseband bandwidth. The simulation results for all different input signals and PN spectra are summarized in Table I. It can be seen that the difference in the PWN power between the simulations is completely determined by the difference in the wideband noise floors. This is because the VCO PN is a lot smaller than the white noise floor for large offset frequencies. The PPN power is REFERENCES [1] J. A. Cherry and W. M. Snelgrove, Continuous-Time Delta Sigma Modulators for High-Speed A/D Conversion. Norwell, MA: Kluwer, 000. [] J. A. Cherry and W. M. Snelgrove, Clock jitter and quantizer metastability in continuous-time delta sigma modulators, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 6, pp. 661 676, Jun. 1999. [3] H. Tao, L. Tóth, and J. M. Khoury, Analysis of timing jitter in bandpass sigma delta modulators, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 8, pp. 991 1001, Aug. 1999. [4] M. Ortmanns, F. Gerfers, and Y. Manoli, Fundamental limits of clock jitter insensitivity in discrete and continuous-time sigma delta modulators, in Proc. IEEE ISCAS, Bangkok, Thailand, May 5 8, 003, pp. 1037 1040. [5] Y.-S. Chang, C.-L. Lin, W.-S. Wang, C.-C. Lee, and C.-Y. Shih, An analytical approach for quantifying clock jitter effects in continuoustime sigma delta modulators, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 9, pp. 1861 1868, Sep. 006. [6] L. Hernández, A. Wiesbauer, S. Patón, and A. D. Giandomenico, Modeling and optimization of low-pass continuous-time sigma delta modulators, in Proc. IEEE ISCAS, Vancouver, BC, Canada, May 3 6, 004, pp. 107 1075. [7] O. Oliaei, Clock jitter noise spectra in continuous-time delta sigma modulators, in Proc. IEEE ISCAS, Orlando, FL, May 30 Jun., 1999, pp. 19 195. [8] O. Oliaei, State-space analysis of clock jitter in continuous-time oversampling data converters, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 1, pp. 31 37, Jan. 003. [9] P. Heydari, Analysis of the PLL jitter due to power/ground and substrate noise, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 404 416, Dec. 004. [10] A. Hajimiri, S. Limotyrakis, and T. H. Lee, Jitter and phase noise in ring oscillators, IEEE J. Solid-State Circuits,vol.34,no.6,pp.790 804, Jun. 1999. [11] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, A 0-mW 640-MHz CMOS continuous-time ΣΔ ADC with 0-MHz signal bandwidth, 80-dB dynamic range and 1-bit ENOB, IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 641 649, Dec. 006.