Bias Power Supply for TV and Monitor TFT LCD Panels Description The offers a compact power supply solution to provide all four voltages required by thin-film transistor (TFT) LCD panel. With its high current capabilities, the device is ideal for large screen monitor panels and LCD TV applications. The consists of a boost converter to provide the source voltage V S and a step-down converter to provide the logic voltage for the system. A positive and a negative charge pump drivers provide adjustable regulated output voltages VGH and VGL to bias the TFT-LCD. Both step-up and step-down converters, as well as the charge-pump drivers, operate with a fixed switching frequency of 500 KHz or 750 KHz, selectable by the FREQ pin. The includes adjustable power-on sequencing. The includes safety features like over-voltage protection and short-circuit protection, as well as thermal shutdown. Additionally, the device incorporates a gate drive signal to control an isolation MOSFET switch in series with V S or VGH. The comes in a miniature 28-pin TSSOP package with exposed pad. Features 8V to 4V Input Voltage Range V S Output Voltage Range up to 9 V % Accurate Step-up Converter with 2.8A Switch Current.5% Accurate 2.3A Step-down Converter 500KHz/750KHz Fixed Switching Frequency Selection Negative Charge Pump Driver for VGL Positive Charge Pump Driver for VGH Adjustable Sequencing for VGL, VGH Gate Drive Signal to Drive External MOSFET Internal and Adjustable Soft Start Short Circuit Protection Over Voltage Protection Over Temperature Protection TSSOP-28 Exposed Pad Package Applications TFT LCD Displays for Monitor and LCD TV Pin Assignments TP Package (TSSOP-28<Exposed Pad>) Ordering Information TR: Tape / Reel Blank: Tube P: Pb Free with Commercial Standard (RoHS Compliant) G:Green Package Type TP: TSSOP-28(Exposed Pad) Figure. Pin Assignment of
Typical Application Circuit VGL -5V/50mA VIN 2V C2 0.47µF CIN 2*22µF CB µf D2 D3 R3 620KΩ R4 50KΩ CREF 220nF CSS 22nF CB3 µf C4 0.47µF 8 SUPP LX 4 2 FREQ LX 5 20 VIN2 FB 2 VIN2 OS 3 22 6 VIN EN GND 23 EXT 27 9 EN2 DRVP 0 DRVN FBP 4 3 FBN 24 REF 6 PGND 7 PGND 28 SS 25 DLY CD 0nF L 0µF BOOT 7 LX2 8 NC 9 FB2 5 COMP 2 DLY2 26 CD2 0nF D SL22 CF R 22PF 825KΩ C 3*22µF CB2 470nF C5 0.47µF CLOMP 22nF D4 D5 R2 56KΩ CBOOST 00nF D6 SL22 R5 560KΩ R6 22KΩ L2 5µF C3 0.47µF R7 2KΩ Vs 8V/.3A VGH 32V/50mA Vlogic 3.3V/2.3A C5 2*22µF R8.2KΩ Figure 2. Typical Application Circuit of 2
Functional Pin Description Pin Name Pin Function FB Feedback pin of the step-up converter generating V SOURCE (V S ) 2 COMP 3 OS The external compensation pin for the step-up converter. A small capacitor is connected to this pin. If required, a resistor is connected to this pin. Output sense pin. The pin is connected to the output of step-up converter and can not be connected to any other voltage rail. Connect a 470-nF capacitor from OS pin to GND to avoid noise coupling into this pin. 4, 5 LX Switching pin of the step-up converter generating V SOURCE (V S ) 6, 7 PGND Power ground 8 SUPP 9 EN2 The supply pin for positive charge pump driver. It can be connected to the input voltage V IN or the output of the step-up converter V S EN2 is the enable pin of the step-up converter and the positive charge pump. When EN2 is pulled high, the step-up converter and positive charge pump start up after the step down converter is within regulation and a delay time set by DLY2 has passed by. This pin must be terminated and not be left floating. A logic high enables the device and a logic low disables the device 0 DRVP Drive pin of the positive charge pump DRVN Drive pin of the negative charge pump 2 FREQ Frequency selection pin. A logic high set the oscillator frequency = 750KHz and a logic low set the oscillator frequency = 500KHz 3 FBN Feedback pin of the negative charge pump 4 FBP Feedback pin of the positive charge pump 5 FB2 Feedback pin of the step-down converter 6 EN 7 BOOT EN is the enable pin of the step-down converter and the negative charge pump. When EN is pulled high, the step down converter starts up, and after a delay time set by DLY, the negative charge pump comes up. This pin must be terminated and not be left floating. A logic high enables the device and a logic low disables the device Bootstrap pin. A capacitor is needed to drive the N-channel MOSFET s gate above the supply voltage. It is connected between LX2 and BOOT pin to form a floating supply across the N-channel MOSFET 8 LX2 Switching pin of the step-down converter 9 NC No connected 20, 2 VIN2 Power input voltage pin for the step-down converter 22 VIN Analog input voltage pin. This is the input for the analog circuits of the device and should be connected with a bypass capacitor for good filtering 23 GND Analog ground 24 REF Reference pin. Typically.23V. 25 DLY 26 DLY2 27 EXT Connect a capacitor between this pin and ground to set the delay time between step-down converter and negative charge pump during start-up Connect a capacitor between this pin and ground to set the delay time between step-down converter to step-up converter and positive charge pump during start-up The gate drive pin which can be used to control an external MOSFET switch to provide input to output isolation of V S or VGH. EXT is an open-drain output and is latched low when the output voltage of step-up converter is regulated (92% of FB). EXT is changed to high impedance when EN2 or input voltage (V IN ) is cycled low. 28 SS Connect a capacitor to this pin to set the step-up converter internal soft-start time. Typically 22nF 3
Block Diagram fitipower integrated technology lnc. VIN FREQ LX LX GND Bias =.23V Thermal Shutdown 500KHZ/ 750KHZ Oscillator BTSS Current Limit and Soft Start OS Q2 OS BTSS Slope Compensation Overvoltage Comparator SS Control Logic OS COMP FB GM Amplifier.54V Comparator PR2 PGND PGND VIN2 SUPP SUPP DRVN VIN Negative Charge Pump Soft Start Control Logic.23V PR2 Soft Start Control Logic DRVP FBP PR Regulator 5V BOOT FBN osc LX2 Control Logic NC DLY TDLY Slope Compensation Current Limit FB2 DLY2 TDLY2 Error Amplifer EXT Compensation and Soft Start 0.9V Clock/2 PR PR2 0.6V Clock/4 Logic Clock Power-on Sequencing Control TDLY TDLY2 Clock Clock Select During Short Circuit and Soft Start.23V Reference output REF EN EN2 Figure 3. Block Diagram of 4
Absolute Maximum Ratings V IN, V IN2, EN, EN2, FREQ to GND ------------------------------------------------------------- -0.3V to 6.5V FB, FB2, FBP, FBN, REF, SS, DLY, DLY2, COMP to GND ----------------------------- -0.3V to 6V LX to PGND ------------------------------------------------------------------------------------------ -0.3V to 25V LX2 to PGND ------------------------------------------------------------------------------------------ -0.3V to 20V BOOT to GND ----------------------------------------------------------------------------------------- V LX2 + 5V OS, EXT, SUPP to GND ---------------------------------------------------------------------------- -0.3V to 25V DRVN, DRVP to PGND ----------------------------------------------------------------------------- -0.3V to (SUPP+0.3V) PGND to GND ----------------------------------------------------------------------------------------- ± 0.3V Maximum Junction Temperature (T J ) ------------------------------------------------------------ + 50 Storage Temperature (T STG ) ------------------------------------------------------------------------ -65 to + 50 Power Dissipation @ T A =70, TSSOP-28 (P D ) ----------------------------------------------.38W Package Thermal Resistance, TSSOP-28 (θ JA ) ----------------------------------------------- 40 /W Lead Temperature (Soldering, 0sec.) ---------------------------------------------------------- + 260 ESD Susceptibility (HBM Mode)------------------------------------------------------------------- 2KV ESD Susceptibility (MM Mode)--------------------------------------------------------------------- 00V Note:Stresses beyond those listed under Absolute Maximum Ratings" may cause permanent damage to the device. Recommended Operating Conditions Supply Voltage (V IN ) --------------------------------------------------------------------------------- 8V to 4V Output Voltage of Main Boost Converter (V S ) -------------------------------------------------- 9V Output Voltage of Buck Converter (V LOGIC ) -----------------------------------------------------.8V to 5V Operation Temperature Range -------------------------------------------------------------------- - 40 C to + 85 C 5
Electrical Characteristics (VIN=2V, VSUPP= VIN, VEN= VEN2= VIN, VS=5V, VLOGIC=3.3V, T A = 25 ºC, unless otherwise specified) Parameter Symbol Conditions Min Typ. Max Unit Input Voltage Range V IN 8 4 V Under-Voltage Lockout Threshold V UVLO V IN falling 6 6.4 V Bias Current Bias Current into VIN I VIN 0.2 2 ma Bias Current into VIN2 I VIN2 0.2 0.5 ma Bias Current into SUPP I VIN2 0.2 2 ma Shut Down Current into VIN I SD,VIN EN=EN2=0V 0. 2 µa Shut Down Current into VIN2 I SD,VIN2 EN=EN2=0V 0. 2 µa Shut Down Current into SUPP I SD,VIN EN=EN2=0V 0. 4 µa Reference Reference Voltage V REF.20.23.225 V Enable EN, EN2 High Level Input Voltage V ENH 2 EN, EN2 Low Level Input Voltage V ENL 0.3 FREQ High Level Input Voltage V FREQH 2 V FREQ Low Level Input Voltage V FREQL 0.3 Input Leakage Current I I EN=EN2=FREQ=0V or V IN 0.0 0. µa Delay and Soft Start Setting Delay Charge Current I DLY 3.3 4.8 6.2 Delay 2 Charge Current I DLY2 3.3 4.8 6.2 V THRESHOLD =.23V Soft Start Charge Current I SS 5 9 2 µa Oscillator Oscillator Frequency f FREQ=High 600 750 900 FREQ=Low 400 500 600 KHz Step-up Converter Output Voltage Range V S 9 V Feedback Voltage V FB.35.46.57 V Feedback Input Leakage Current I FB 0 00 na NMOS On-Resistance I LX =500mA 00 mω PMOS On-Resistance R DS(ON) I LX =200mA 0 Ω Maximum PMOS Peak Switch Current A 6
Electrical Characteristics (Continued) Parameter Symbol Conditions Min Typ. Max Unit NMOS Current Limit I LIM 2.8 3.5 A LX Switch Leakage Current I LEAK V LX =5V 0 µa Over-Voltage Protection Threshold V OVP VOUT rising 9.5 20 2.5 V Line Regulation 0.6V < V IN <.6V at ma 0.0008 %/V Load Regulation 0.03 %/A Thermal Shutdown Temperature rising 55 ºC Thermal Shutdown Hysteresis 20 ºC Step-down Converter Output Voltage Range V LOGIC.8 5 V Feedback Voltage V FB2.95.23.23 V Feedback Input Leakage Current I FB2 0 00 na NMOS On-Resistance R DS(ON) I LX2 =500mA 75 mω NMOS Current Limit I LIM 2.5 3.2 A LX2 Switch Leakage Current I LEAK V LX2 =0V 0 µa Line Regulation 0.6V < V IN <.6V at ma 0.008 %/V Load Regulation 0.037 %/A Negative Charge Pump Output Voltage Range V GL -2 V Feedback Voltage V FBN -36 0 36 mv Feedback Input Leakage Current I FBN 0 00 na PMOS On-Resistance R DS(ON) I OUT = 20mA 4.4 Ω Current Sink Voltage Drop Positive Charge Pump V DROPN I DRVN = 50mA 30 mv I DRVN = 00mA 270 mv Feedback Voltage V FBP.87.23.238 V Feedback Input Leakage Current I FBP 0 00 na NMOS On-Resistance R DS(ON) I OUT = 20mA. Ω Current Source Voltage Drop Gate Drive (EXT) V DROPP I DRVP = 50mA 400 mv I DRVP = 00mA 850 mv Gate Drive Threshold V EXT V FB rising 88% V S 92% V S 96% V S V Gate Drive Output Low Voltage V EXTL Sink 500µA 0.3 V Gate Drive Output Leakage Current I EXTL V EXT = 20V 0.05 µa 7
Typical Performance Curves 00 00 90 90 80 80 Efficiency (%) 70 60 50 40 30 20 0 V IN /V O =2V/5V L=5uH FREQ=0V Efficiency (%) 70 60 50 40 30 20 0 V I =2V V O =3.3V L=5uH 0 0.0 0.5.0.5 2.0 Output Current (A) Figure 4. Boost Converter Efficiency vs. Output Current 0 0.0 0.5.0.5 2.0 Output Current (A) Figure 5. Step Down Converter Efficiency vs. Output Current Switching frequency (khz) 720 70 700 690 680 670 660 650 V IN =2V V S =5V/.2A C SS =22nF CH3: V S CH2: V LX CH4: I LX 640-40 -30-20 -0 0 0 20 30 40 50 60 70 80 90 Temperature (deg) Figure 6. Switching Frequency vs. Temperature Figure 7. Boost Converter Soft-Start V IN =2V V S =5V/0mA CH3: V S V IN =2V V S =5V/.5A CH3: V S CH2: V LX CH2: V LX CH4: I LX CH4: I LX Figure 8. PWM Operation Boost Converter Continuous Mode: Light Load Figure 9. PWM Operation Boost Converter Continuous Mode: Heavy Load 8
Typical Performance Curves (Continued) V IN =2V, V S =5V, C O =3x22uF C COMP =4.7nF, C F =22pF, L=6.8uH, FREQ=H I OUT =200mA to.4a CH3: V LOGIC V IN =2V V O =3.3V/.2A CH: V S CH2:V LX2 CH4: I OUT CH4: I LX2 Figure 0. Boost Converter Load Transient Response Figure. Step Down Converter Soft-Start CH3: V LOGIC CH: V LOGIC V IN =2V V O =3.3V/.5A CH4: I LX2 CH2:V LX2 V IN =2V V O =3.3V/45mA CH4: I LX2 CH2:V LX2 Figure 2. Step Down Converter PWM Operation Discontinuous Mode Figure3. Step Down Converter PWM Operation Continuous Mode CH: V LOGIC CH3: V LOGIC V IN =2V, V LOGIC =3.3V C O =22uFx2, FREQ=H I OUT =00mA to.3a CH2: V GL CH3: V S CH4: I OUT CH4: V GH Figure 4. Step Down Converter Load Transient Response Figure 5. Power-Up Sequence EN2 Connected To V IN 9
Typical Performance Curves (Continued) CH: V LOGIC CH2: EN2 CH3: V S CH4: V GH Figure 6. Power-Up Sequence EN2 Enabled Separately 0
Application Information Operation The is a multiple-output DC-DC converter IC which is designed primarily for use in thin-film transistor (TFT) liquid crystal display (LCD) applications. It features two PWM converters: one is step-up converter operating with a selectable switching frequency of 500KHz or 750KHz and uses internal N-MOS to provide maximum efficiency. The output voltage of the step-up converter can be set from V IN to 9V with external resistive divider. The other is step down converter using internal N-MOS to provide the logic voltage for system. A pair of charge-pump regulators independently regulates a positive output V GH and a negative output V GL for TFT gate-high and gate-low supplies. also consists of a precision.23v reference, logic shutdown, current-limited, soft-start, power-up sequencing and thermal shutdown. Step Up Converter The step up converter operates in fast transient response, current-mode PWM. Figure 3 shows block diagram of. On the rising edge of the internal clock, the control and driver logic block sets internal flip-flop when the output voltage is too low, which turns on the N-MOS. The external inductor current ramps up linearly, storing energy in a magnetic filed. Once peak current of inductor over trans-conductance output level, the N-MOS turns off, the flip-flop resets, and external schottky diode turns on. This forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and load. To add higher flexibility to the selection of external component values, the device uses external loop compensation Negative Charge-Pump Regulator (V GL ) Negative Charge-Pump Regulator inverts the supply voltage (VIN) and provides a regulated negative output voltage to power the row driver in the LCD panel. During the first half-cycle, the P-channel MOSFET turns on and flying capacitor C4 charges to VIN minus a diode drop. During the second half-cycle, the P-channel MOSFET turns off, and the current source turns on, level shifting C4. This connects C4 in parallel with the reservoir capacitor C2. If the voltage across C2 minus a diode drop is lower than the voltage across C4, charge flows from C4 to C2 until the diode turns off. The amount of charge transferred to the output is controlled by the variable N-channel on-resistance and a resistive voltage-divider from the VGL output to GND with the center tap connected to FBN. Positive Charge-Pump Regulator (V GH ) Positive Charge-Pump Regulator also inverts the supply voltage (V S ) and provides a regulated positive output voltage to power the row driver in the LCD panel. During the first half-cycle, the N-channel MOSFET turns on and flying capacitor C 5 charges to V S minus a diode drop. During the second half-cycle, the N-channel MOSFET turns off, and the current source turns on, level shifting C 4 by V SUPP volts. This connects C 5 in series with the reservoir capacitor C 3. If the voltage across C 3 plus a diode drop is lower than the level shifted flying capacitor voltage (V S +V SUPP ), charge flows from C 5 to C 3 until the diode turns off. The amount of charge transferred to the output is controlled by the variable N-channel on-resistance and a resistive voltage-divider from the V GH output to GND with the center tap connected to FBP. Power-Up Sequencing The step-down regulator starts up when the s input voltage (VIN) is above its under-voltage lockout (UVLO) threshold and EN is logic-high. Once the step-down regulator reaches regulation, the negative charge pump delay block are enabled. A 4.8μA current source at DLY charges C D linearly. The negative charge-pump regulator soft-starts when VDLY reaches VREF. The step-up regulator and positive charge-pump startup sequence begin when the step-down regulator reaches regulation and EN2 is logic-high. A 4.8μA current source at DLY2 charges C D2 linearly when VDLY2 reaches VREF. For non-delayed startups, capacitors can be omitted from DLY, DLY2. Delay Time Setting A capacitor from DLY, DLY2 pin to GND modulates delay time. Select C DLY,2 using the following equation: C DLY 4. 8uA, 2 = TDELAY. 23V where T DELAY is setting delay time
Application Information (Continued) Frequency Selection The s frequency can be user selected to operate at either 500kHz or 750KHz. Connect FREQ to GND for 500kHz operation. For a 750KHz switching frequency, connect FREQ to V IN. This allows the use of small, minimum-height external components while maintaining low output noise. Current Limit Protection The provides cycle-by-cycle over-current protection. Current limit is accomplished by sensing voltage drop across the drain to source of power switch. If the current sense amplifier output voltage is larger than current-limited threshold level (typ..0v), it will be immediately turned off power MOS. The current-limit feature protects over current fault at the output. Thermal Overload Protection Thermal-overload protection limits total power dissipation in the. When the junction temperature exceeds T j = +55 C, a thermal sensor activates the thermal protection, which shuts down the IC, allowing the IC to cool. Once the device cools down by 20, IC will automatically recover normal operation. For continuous operation, do not exceed the absolute maximum junction temperature rating of Tj=50. Short Circuit Protection (Step Down Converter) The protects output short circuit by switching frequency fold-back. The oscillator frequency of is reduced to about /2 and /4 of switching frequency when the feedback voltage is under 0.9V and 0.6V. This frequency fold-back allows the inductor current has more time to decay to prevent potential runaway condition to occur. The oscillator frequency will progressively increase to normal frequency as feedback voltage rises gradually from 0.6V back to regulated level. Under Voltage Lockout The under voltage lockout (UVLO) circuit provides the save operation to keeps the device from turning on when V IN is smaller than typically 6.0V. Soft-Start (Step Up Converter) Soft-start allows a gradual increase of the internal current-limit level for the step-up converter during power-up to reduce input surge currents. As the internal constant current source charges the external soft-start capacitor, the peak N-MOS current is limited by the voltage on the capacitor. Adjustable Step-up Converter Output Voltage The output voltage of ranges from V IN to 9.0V which is set by the external feedback resistor. It can be calculated as: R V S =. 46 ( + ) R2 Adjustable Gate-High Charge-pump Output Voltage The Gate-high charge pump output voltage can be set by the external feedback resistor from V ON to GND. A resistor network in the order of 22kΩ is recommended. It can be calculated as: R5 V GH =. 23 ( + ) R6 Adjustable Gate-Low Charge-pump Output Voltage The Gate-low charge pump output voltage can be set by the external feedback resistor from V OFF to GND. A resistor network in the order of 50kΩ is recommended. It can be calculated as: Over Voltage Protection (Step Up Converter) The over-voltage function monitors the output voltage by OS pin to protection the converter against the FB pin short to ground with a sense resistor. This will cause N-MOS to switch with a maximum duty cycle and come out output over-voltage. This may cause the LX pin voltage to exceed its maximum voltage rating to damage built-in N-MOS. In the state, the OVP protection circuitry stops the internal N-MOS and clamp output voltage at 20V (typ). When V OUT falls below 7V (typ), IC will automatically recover normal operation. V GL = V FBN R3 R3 ( + ) V R4 R4 REF where V FBN =0V, V REF =.23V as specified. 2
Application Information (Continued) Positive and Negative Charge Pump The contains two independent charge pump. The regulation of both the negative and positive charge pumps is generated by external diode-capacitor. The single stage of positive charge-pump is given by: V R I GH(MAX) DRVPP(ON) GH f 2 V C 3 SUPP ) + 2 V I DIODE GH I 2 (R GH f DRVPN(ON) C where R DRVPN(ON) and R DRVPP(ON) resistance values depend on the V SUPP voltage levels, V DIODE is the forward-voltage drop of the charge-pump diode. The single stage of negative charge-pump is given by: V GL(MAX) 2 V DIODE IGL 2 (R IGL f C DRVNN(ON) 4 I + R GL f DRVNP(ON) 5 2 + ) + V C where R DRVNN(ON) and R DRVNP(ON) resistance values depend on the V IN voltage levels, V DIODE is the forward-voltage drop of the charge-pump diode. Applications Information (Step Up Converter) External components of boost converter can be designed by performing simple calculations. It need to follow regulation by the output voltage and the maximum load current, as well as maximum and minimum input voltages. Begin by selecting an inductor value. Once L is know, choose the diode and capacitors. Inductor Selection A 4.7uH to 5uH is recommended for general used. The value of inductor depends on the operating frequency. Higher frequency allows smaller inductor and capacitor but increase internal switching loss. Two inductor parameters should be considered, current rating and DCR. The DCR of inductor affects the efficiency of the converter. The inductor with lowest DCR is chosen for highest efficiency. The inductor value can be calculated as: ΔIL ILpeak = ILAVG + 2 IMAIN ILAVG = D IN where: I L is the inductor peak-to-peak current ripple and is decided by: Vin D Δ I L = L f ΔI L V = in V L O D f D is the MOSFET turn on ratio and is decided by: VO V in D = VO f is the switching frequency. The inductor should be chosen to be able to handle this current and inductor saturation current rating should be greater than I PEAK. Inductor Selection (Step Down Converter) Inductor selection depends on input voltage, output voltage, maximum current, switching frequency and availability of inductor values. The following buck circuit equations are useful in choosing the inductor values based on the application. Choose an inductor that does not saturate under the maximum rating load conditions. The magnitude of inductance is selected to maintain a peak to peak ripple current of 30% of the maximum load current. The peak inductor current is given by: ΔI L I Lpeak = I LAVG + 2 I in I LAVG = D VO D = V in D is the MOSFET turn on ratio where: I L is the inductor peak-to-peak current ripple and is decided by: f is the switching frequency. (Vin V L = ΔI f L O ) D The inductor should be chosen to be able to handle this current and inductor saturation current rating should be greater than I PEAK. 3
Application Information (Continued) Capacitor Selection The is permissible in using ceramic capacitor for TFT LCD panel application. The value of capacitor depends on acceptable voltage ripple. The input capacitor can reduced peak current and noise at power source. It should have 22uF at least and can be increased for better input voltage filtering. Select the input capacitor to meet the input ripple current and voltage rating. When selecting an output capacitor, consider the output ripple voltage and the ripple current. The ESR of capacitor is a major factor to the output ripple. For best performance, a low ESR output capacitor is required. The ripple voltage is given by: Δ VO = ΔI L ( ESR + ) 8* f * Co The common aluminum-electrolytic capacitors have high ESR and should be avoided. Ceramic capacitors have the lowest ESR in general. It uses 22uF ceramic output capacitors for the. Diode Selection For diode selection, both forward voltage and diode capacitance need to be considered. The output diode should be rated to the output voltage and peak switch current. Schottky diodes, with their low forward voltage drop and fast reverse recovery, are the ideal choices for applications. Make sure the diode s peak current rating is at least IPK and its breakdown voltage exceeds V S. Compensation (Step Up Converter) The step-up loop can be compensated by a bypass capacitor across the upper resistor of FB pin. The feed-forward capacitor can provide a good load transient response and a stable converter loop. The feed-forward capacitor sets a zero with upper resistor of FB pin in the control loop. The zero frequency is given by: f Z = 2 π C F C F is the feed-forward capacitor. R Layout Consideration Careful printed circuit layout is extremely important to avoid causing parasitical capacitance and line inductance. The following layout guidelines are recommended to achieve optimum performance. Please the PWM converter diode and inductor close to the LX.2 pin and no via. Please ceramic bypass capacitors near the VIN,2, SUPP and REF pin. The ground connection of the V IN bypass capacitor should be connected directly to the GND pin with a wide trace. Place Cout, C5 next to schottky diode as possible. Use wide traces and trace length is short as possible to the LX,2 node. Using a bypass capacitor to GND to reduce noise coupling into OS pin. Keep the noise-sensitive feedback (FB, FB2, FBP, and FBN) away from the switching node. Place the flying capacitors as close as possible to the DRVP and DRVN pin. The power ground (PGND) and signal ground (GND) pins should be connected at only one point. The exposed pad, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers. if available, to maximize thermal dissipation away from the IC. 4
Outline Information TSSOP-28 Package (Unit: mm) SYMBOLS DIMENSION IN MILLIMETER UNIT MIN NOM MAX A --- ---.20 A 0.00 --- 0.5 A2 0.80.00.05 b 0.9 --- 0.30 D 9.60 9.70 9.80 E 4.30 4.40 4.50 E 6.40 BSC e 0.65 BSC L.00 REF L 0.45 0.60 0.75 S 0.20 --- --- E2 --- 3.0 REF --- D --- 5.33 REF --- θ 0º --- 8º Note :Followed from JEDEC MO-53-F. Life Support Policy Fitipower s products are not authorized for use as critical components in life support devices or other medical systems. 5