AS THE MOST fundamental analog building block, the

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011 445 Impedance Adapting Compensation for Low-Power Multistage Amplifiers Xiaohong Peng, Member, IEEE, Willy Sansen, Fellow, IEEE, Ligang Hou, Jinhui Wang, and Wuchen Wu Abstract A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation. A three-stage IAC amplifier was implemented and fabricated in a 0.35 m CMOS technology. Experiment results show that the implemented IAC amplifier, driving a 150 pf load capacitance, achieved a gain-bandwidth product (GBW) of 4.4 MHz while dissipating only 30 W power with a 1.5 V supply. Index Terms Multistage, amplifier, amplifiers, compensation, low power, low voltage, impedance adapting. I. INTRODUCTION AS THE MOST fundamental analog building block, the high-gain operational amplifier has always been the key element for achieving high performance in advanced analog circuits and systems. However, in CMOS technology, the trend of further scaling down the channel length and supply voltage leads to severely gain reduction and insufficient swing. In this situation, multistage amplifiers have become much more in demand. However, there are several problems and difficulties in implementing a multistage amplifier. As more poles and zeros show up, a multistage amplifier tends to be less stable in a feedback application, which results in disturbing oscillations. Hence, to ensure stability, frequency compensation is always required especially for multistage amplifiers. For this reason, several frequency compensation topologies such as NMC [6] (Nested Miller Compensation), MNMC [7] (Multi-path Nested Miller Compensation) and NGCC [8] (Nested Gm-C Compensation) were developed. Although these topologies can basically solve the problem and make multistage amplifiers practicable, they suffer from serious problems such as enormous power dissipation and bandwidth reduction. Subsequent researches are aimed at how to increase gain-bandwidth Manuscript received June 29, 2010; revised October 06, 2010; accepted October 18, 2010. Date of publication November 29, 2010; date of current version January 28, 2011. This paper was approved by Associate Editor Kunihiko Iizuka. This work was supported by the China National Science Fund under Grant 60976028. X. Peng, L. Hou, J. Wang, and W. Wu are with the VLSI and System Laboratories, Electronic Engineering Department, Beijing University of Technology, Beijing 100124, China (e-mail: pengxiaohong@bjut.edu.cn). W. Sansen is with the ESAT Laboratory, K. U. Leuven, Leuven 3001, Belgium. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2010.2090088 product and decrease power dissipation while applying various frequency compensation schemes. To further improve performance and enrich design methodologies for multistage amplifiers, this paper presents a new frequency compensation topology, Impedance Adapting Compensation (IAC), which effectively extends the gain-bandwidth product (GBW) while minimizing the power dissipation. II. REVIEW For better understanding and comparison, this section reviews some of the existing topologies. In a three-stage NMC amplifier, two Miller capacitors and are attached from the output to each preceding stage respectively, forming two negative feedback loops. They do ensure stability, but tremendously reduce the high-frequency gain. As shown in previous works [3], [4], this Nested Miller Compensation requires a large value of last-stage transconductance, given by (1) For a single-stage amplifier, for the same GBW and specification, a much smaller transconductance is required, given by Expressions (1) and (2) show that for a given GBW and a specific load capacitance, the last stage of a NMC amplifier needs at least 4 times more transconductance compared to a single-stage amplifier. For comparison, a new definition, namely the transconductance efficiency, can be employed, given by According to (3), an amplifier with a larger value of means that for a given capacitive load, the amplifier can achieve a larger GBW or require a smaller transconductance. Hence, it needs less current or power to achieve a given GBW. Applying the definition of transconductance efficiency, it is found that the transconductance efficiency of a single-stage amplifier is always unity, as given by For a NMC amplifier, the last-stage transconductance efficiency alone is not more than 0.25, as given by (2) (3) (4) (5) 0018-9200/$26.00 2010 IEEE

446 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011 TABLE I SUMMARY OF DIFFERENT TOPOLOGIES Fig. 1. Impedance Adapting Compensation. Based on the above discussions, it can be thus deduced that no matter what optimization is made and no matter what technology is used, the transconductance efficiency of a NMC amplifier is always limited to a small fraction of unity, and far smaller than that of a single-stage amplifier. Other topologies such as MNMC [7], NGCC [8] and NMCF [10] (Nested Miller Compensation with a Feed-forward stage), were reported with improved performance. However, since the shorting effect of the inner Miller capacitor still exists, the improvement ratios are not more than two. Further studies show that the transconductance efficiencies of these topologies are all insufficient. In Table I, the performance parameters such as achievable gain-bandwidth product and phase margin of different topologies are given. The transconductance efficiencies and their ratios to the Nested Miller Compensation are calculated and listed as well. For better gaging, a single-stage amplifier (Single) and a twostage amplifier with Single Miller Compensation (SMC) are also given in Table I. To substitute a single-stage amplifier for low-power application, a multistage amplifier should at least have its transconductance efficiency to be above unity. With this respect, the designs of low-power multistage amplifiers should better start with frequency compensation topologies that exhibit high transconductance efficiencies. Thus, it is very important to develop more efficient frequency compensation topologies so as to make multistage amplifiers more competitive. III. IMPEDANCE ADAPTING COMPENSATION A. Topology The newly proposed topology employs a serial RC impedance as a frequency compensation element, as shown in Fig. 1. It is named as Impedance Adapting Compensation (IAC). The single transconductance stages,, and make up the conventional three-stage amplifier. The output resistance and the lumped parasitic node capacitance of each single stage are noted by and, respectively. stands for the load capacitance. is a usual Miller capacitor forming a outer negative feedback loop, which is necessary for stabilization. The distinction from the NMC topology is that the inner Miller capacitor is no longer used; instead a serial RC impedance(formed by and ) is added. This serial RC impedance exerts no shorting effect on the last stage, but only acts as a load to the second stage, needing no extra power. In summary, the proposed IAC topology has, on one hand, a normal Miller capacitor which is still needed to provide a negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance such as stability, gain-bandwidth product and power dissipation. To improve as well large signal performance such as slew rate, a feedforward stage, can be optionally included, as shown by dotted lines in Fig. 1. It will be discussed later as well. B. Transfer Function Analytically, the small-signal transfer function of the openloop gain of a three-stage IAC amplifier can be described by a fourth-order expression, given by It is practical to presume that the low-frequency gain of each stage is sufficiently larger than unity, and the compensating capacitances are much larger than the corresponding parasitical capacitances and far smaller than the load capacitance, as given by (6) (7) (8) (9) Based on these assumptions, and by a circuit analyzing on the topology shown in Fig. 1, the frequency factors in (6) can be determined, as follows: (10) (11) (12) (13) (14) (15) Herein, the parameter can be approximated to unity when is much larger than unity, as given by (16)

PENG et al.: IMPEDANCE ADAPTING COMPENSATION FOR LOW-POWER MULTISTAGE AMPLIFIERS 447 Fig. 2. A pole-zero distribution of IAC topology. Therefore, in this case, the feedforward stage can be ignored for small-signal analysis. The other two parameters in (6) are the low-frequency gain and the dominant pole, given respectively by (17) (18) Finally, the multiplication of (17) by (18) yields the gainbandwidth product, as given by (19) C. Design Constraints and Stability The design focuses on the pole-zero distribution of the openloop gain transfer function. It is important to properly arrange poles and zeros so as to optimize performance such as gainbandwidth product and phase margin. As multiple poles may be present too closely spaced to each other, the desired single-pole property below unity-gain frequency cannot be obtained easily. Therefore, pole-splitting is usually applied. For NMC topology, to split poles, Miller capacitors are used to form multiple negative feedback loops. However these additional feedback loops overly reduce high-frequency gain, resulting in serious bandwidth reduction or requiring very large transconductance stages which consume much current or power. In contrast, for the IAC topology, a serial RC impedance is used as a simple load of the intermediate stage, carrying out the pole-splitting task without having to short amplification stages. Since capacitor is a lumped parasitic capacitance which is relatively small, frequency can be readily extended to a sufficiently large value by setting appropriately. Similarly, by increasing capacitance, frequency can be tuned to a relatively small value. Thus, separated poles can be obtained. The pole-splitting task is accomplished satisfactorily. The following inequalities can be thus established: (20) Based on (20), finding out all the roots that zeroing the denominator in (6), the non-dominant poles can then be determined: (21) (22) (23) For the numerator, also based on (20), the relations of frequencies can be derived as follows: (24) (25) Thus, by solving the roots that zeroing the numerator in (6), all zeros are obtained, as given by (26) (27) (28) Apparently, as long as conditions (24) and (25) are satisfied, both the left-half-plane (LHP) zero and the right-halfplane (RHP) can be kept at sufficiently higher frequencies, even far higher than the second non-dominant pole. Their influences are thus neglected. Only the LHP zero, located at a relatively low position, provides a visible affect. Based on the discussions above, a pole-zero distribution can be realized, as illustrated by Fig. 2. It is important to notice that the first non-dominant pole and the first LHP zero cancel each other. The other zeros,, and the third non-dominant pole are located at sufficiently high frequencies. Their effects can be neglected. Consequently, the second non-dominant pole is actually the sole element that determines phase margin PM and GBW. This can be thus established as a design constraint, as given by (29) It is known that to ensure stability for an unity-gain feedback application, the phase margin PM must be kept above zero. This can always be satisfied from (29). Nonetheless, to allow a singlepole property below the unity-gain frequency, cannot be lower than, as given by (30) which means that the PM should be larger than 45. Condition (30) reveals that the achievable GBW depends on for a specific last-stage transconductance to drive a specific load. As long as the value of is increased, the GBW can be extended accordingly. This is evidenced as well by checking its last-stage transconductance efficiency : (31)

448 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011 Fig. 3. Schematic. which can be made much larger than unity. Usually a PM about 60 is preferred. Hence, the non-dominant pole should be placed at about. Another design constraint that relates to and GBW is thus obtained: (32) Finally, the design constraint for the compensating capacitance can be derived, as given by (33) Fig. 4. Micrograph. D. Slew Rate The output-stage slew rate can be improved by means of bringing in a feedforward stage as shown by dotted lines in Fig. 1. Since is much smaller than and, and is set much larger than unity, the second-stage influence on slew rate can be ignored. Therefore, the first stage limits the overall slew rate SR [3], [4], as given by TABLE II MEASURED RESULTS AND CIRCUIT PARAMETERS (34) Equation (34) indicates that increasing GBW leads to an according improvement on slew rate. It shows also that for a given GBW, the overall slew rate depends on the first-stage operating point, which limits only the swing of the first stage. This enables additional ways of optimization such as seeking the optimum operating points of other stages to fine tune the overall performances and the output swing. E. Implementation A three-stage amplifier using IAC topology was implemented. The schematic is shown in Fig. 3. A folded cascoding OTA is used as the first stage. It consists of transistors M10 M18. Differential pair M11 and M12 determine first-stage transconductance. Transistor M21 M25 provides second-stage transconductance, which is realized through a current mirror. The last-stage transconductance is provided by a nmos transistor M3, while the pmos transistor M30 acts as the feedforward stage. is the Miller capacitor establishing the main internal negative feedback loop. is the load capacitance. and are connected in series as a load to the second stage. It has been found that the accuracy of resistance is not relevant. Simulations confirm that a 20% variation on only causes a phase-margin offset about 2. The amplifier was fabricated in a 0.35 m CMOS process. Its active area is less than 0.02 mm. A micrograph is shown in Fig. 4.

PENG et al.: IMPEDANCE ADAPTING COMPENSATION FOR LOW-POWER MULTISTAGE AMPLIFIERS 449 TABLE III LIST OF COMPARISON RESULTS OF DIFFERENT AMPLIFIERS Fig. 6. Measured transient response (Xdiv: 10 S, Ydiv: 0.5 V). Fig. 5. Measured open-loop gain frequency responses. on power and current respectively. The formulas for both smallsignal and large-signal evaluation are given by F. Measured Results The implemented three-stage IAC amplifier was measured for both dc and ac specifications. The measured results and circuit parameters are given in Table II. The frequency characteristic and the transient response are shown in Figs. 5 and 6, respectively. (35) (36) (37) (38) IV. PERFORMANCE COMPARISON Performance comparison is normally conducted by means of using formulas FOM and IFOM, which emphasize particularly Applying these formulas to different amplifiers, the comparison results are obtained and given in Table III. As can be seen, this work, the IAC amplifier, has achieved outstanding improvements.

450 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011 V. CONCLUSION A new power-efficient multistage amplifier frequency compensation method, Impedance Adapting Compensation, has been proven to be well suited for low-power low-voltage applications. By means of loading a serial RC impedance to the intermediate stage, performance can be boosted without extra power consumption. Remarkable achievements for both small- and large-signal performance have been reached with an optimized low-power low-voltage three-stage amplifier using this Impedance Adapting Compensation. Xiaohong Peng (S 02 M 04) received the M.S. degree in electronic engineering from the Beijing University of Aeronautics and Astronautics, Beijing, China, in 1985, and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, Belgium, in 2004. He was a Lecturer and an Associate Professor with the Electronic Center, Beijing University of Aeronautics and Astronautics, Beijing, China, from 1985 to 1998. During the period 1999 2004, he was an Assistant Researcher with the ESAT-MICAS Laboratories, Katholieke Universiteit Leuven, Belgium. Currently, he is an Associate Professor with the VLSI and System Laboratory, Electronic Engineering Department, Beijing University of Technology, Beijing, China. REFERENCES [1] W. Sansen, Analog Design Essentials. Dordrecht, The Netherlands: Springer, 2008. [2] X. Peng and W. Sansen, Nested feedforward gm-stage and nulling resistor plus nested-miller compensation for multistage amplifiers, in Proc. IEEE Custom Integrated Circuits Conf., Orlando, FL, May 2002, pp. 329 332. [3] X. Peng and W. Sansen, AC boosting compensation scheme for lowpower multistage amplifiers, IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2074 2079, Nov. 2004. [4] X. Peng and W. Sansen, Transconductance with capacitances feedback compensation for multistage amplifiers, IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1514 1520, Jun. 2005. [5] J. Ramos, X. Peng, M. Steyaert, and W. Sansen, Three stage amplifier frequency compensation, in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Lisbon, Portugal, Sep. 2003, pp. 365 368. [6] J. H. Huijsing and D. Linebarger, Low-voltage operational amplifier with rail-to-rail input and output stages, IEEE J. Solid-State Circuits, vol. 20, no. 12, pp. 1144 1150, Dec. 1985. [7] R. G. H. Eschauzier, L. P. T. Kerklaan, and J. H. Huijsing, A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure, IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1709 1717, Dec. 1992. [8] F. You, S. H. K. Embabi, and E. Sánchez-Sinencio, Multistage amplifier topologies with nested Gm-C compensation, IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2000 2011, Dec. 1997. [9] B. K. Thandri and J. Silva-Martínez, A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors, IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 237 243, Feb. 2003. [10] K. N. Leung and P. K. T. Mok, Analysis of multistage amplifier-frequency compensation, IEEE Trans. Circuits Syst. I, vol. 48, no. 9, pp. 1041 1056, Sep. 2001. [11] K. N. Leung and P. K. T. Mok, Nested Miller compensation in lowpower CMOS design, IEEE Trans. Circuits Syst. II, vol. 48, no. 4, pp. 388 394, Apr. 2001. [12] H. T. Ng, R. M. Ziazadeh, and D. J. Allstot, A multistage amplifier technique with embedded frequency compensation, IEEE J. Solid- State Circuits, vol. 34, no. 3, pp. 339 347, Mar. 1999. [13] K. N. Leung, P. K. T. Mok, W. H. Ki, and J. K. O. Sin, Three-stage large capacitive load amplifier with damping-factor-control frequency compensation, IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 221 230, Feb. 2000. [14] H. Lee and P. K. T. Mok, Active-feedback frequency-compensation technique for low-power multistage amplifiers, IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 511 520, Mar. 2003. [15] H. Lee, K. N. Leung, and P. K. T. Mok, A dual-path bandwidth extention amplifier topology with dual-loop parallel compensation, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1739 1744, Oct. 2003. [16] B. K. Ahuja, An improved frequency compensation technique for CMOS operational amplifiers, IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 629 633, Dec. 1983. [17] X. Fan, C. Mishra, and E. Sánchez-Sinencio, Single Miller capacitor compensation technique for low-power multistage amplifiers, IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 584 592, Mar. 2005. [18] R. Yousry and K. Sharaf, AC boosting compensation with zero cancellation for multistage amplifiers, in Proc. 19th Int. Conf. Microelectronics, Cairo, Egypt, Dec. 2007, pp. 161 164. Willy Sansen (M 72 SM 86 F 95 LF 09) received the M.Sc. degree in electrical engineering from the Katholieke Universiteit Leuven, Belgium, in 1967 and the Ph.D. degree in electronics from the University of California, Berkeley, in 1972. In 1972 he was appointed by the National Fund of Scientific Research (Belgium) at the ESAT Laboratory of the K.U. Leuven, where he has been a full Professor since 1980. During the period 1984 1990 he was the head of the Electrical Engineering Department. Between 1984 and 2008 he headed the ESAT- MICAS laboratory on analog design, which counts about 60 members and is mainly active in research projects with industry. He is a member of several boards of directors. In 1978 he was a Visiting Professor at Stanford University, Stanford, CA, in 1981 at the EPFL Lausanne, Switzerland, in 1985 at the University of Pennsylvania, Philadelphia, in 1994 at the T. H. Ulm and in 2004 at Infineon, Villach, Austria. Dr. Sansen is a member of several editorial and program committees of journals and conferences. He is cofounder and organizer of the workshops on Advances in Analog Circuit Design in Europe. He is a member of the executive and program committees of the IEEE ISSCC conference. He was the program chair of the ISSCC 2002 conference and president of the IEEE Solid-State Circuits Society in 2008 2009. He has been involved in design automation and in numerous analogue integrated circuit designs for telecommunications, consumer electronics, medical applications and sensors. He has been supervisor of over 60 Ph.D. dissertations in these fields. He has authored and coauthored more than 650 papers in international journals and conference proceedings, and 16 books, including the slide-based book Analog Design Essentials (Springer 2008). Ligang Hou received the B.S. degree in electronic engineering from the Shandong University, Jinan, China, in 2001 and the Ph.D. degree in microelectronics and solid-state electronics from Beijing University of Technology, Beijing, China, in 2007. Since 2007, he has been a Lecturer with the VLSI and System Laboratory, Electronic Engineering Department, Beijing University of Technology, Beijing, China. His research interests include VLSI EDA, physical design, and system integration. Jinhui Wang received the B.S. degree in electronic engineering from Hebei University, Hebei, China, in 2004, and the Ph.D. degree in microelectronics and solid-state electronics from Beijing University of Technology, Beijing, China, in 2010. From 2005 to 2009, he was a Research Assistant with the VLSI and System Lab, Beijing University of Technology, working on low-power and high-performance digital circuit design. From 2009 to 2010, he was a Visiting Scholar with the High-Performance VLSI/IC Design and Analysis Laboratory, University of Rochester, Rochester, NY, where he was responsible for the 3-D VLSI design and 3-D thermal simulation of vertical cavity surface emitting laser. He has been an Assistant Professor with the College of Electronic Information and

PENG et al.: IMPEDANCE ADAPTING COMPENSATION FOR LOW-POWER MULTISTAGE AMPLIFIERS 451 Control Engineering, Beijing University of Technology, Beijing, China, since July 2010. His research interests include the areas of low-power, high-performance and variation-tolerant integrated circuit design, multi-threshold voltage integrated circuit design, power gating techniques, estimation model for VLSI performance, and thermal issue in VLSI. He has more than 40 publications and six pending patents in the areas of high-performance integrated circuits and emerging semiconductor technologies. Wuchen Wu received the B.S. degree in electronic engineering from the Beijing University of Technology, Beijing, China, in 1981. He was invited to ETH Zürich Eidgenssische Technische Hochschule Zürich as a Visiting Professor from 1992 to 1995. He is currently a full Professor with the VLSI and System Laboratory, Electronic Engineering Department, Beijing University of Technology, Beijing, China. His research interests include IGBT reliability, IC design, and system integration.