GaAs, phemt, MMIC, Power Amplifier, 2 GHz to GHz FEATURES FUNCTIONAL BLOCK DIAGRAM Output power for 1 db compression (P1dB): 1. db typical Saturated output power (PSAT): dbm typical Gain: 11 db typical Output third-order intercept (IP3): 28 dbm typical Supply voltage: V at 6 ma Ω matched input/output Die size: 2.3 mm 1.4 mm. mm APPLICATIONS RFIN 1 V DD 2 3 RFOUT Test instrumentation Microwave radios and VSATs Military and space Telecommunications infrastructure Fiber optics Figure 1. 4 V GG 1 V GG 2 1383-1 GENERAL DESCRIPTION The is a gallium arsenide (GaAs), pseudomorphic high electron mobility transfer (phemt), monolithic microwave integrated circuit (MMIC), distributed power amplifier that operates from 2 GHz to GHz. The provides 11 db of gain, 28 dbm output IP3, and 1. dbm of output power at 1 db gain compression, while requiring 6 ma from a V supply. The amplifier inputs/outputs are internally matched to Ω facilitating integration into multichip modules (MCMs). All data is taken with the chip connected via two.2 mm (1 mil) wire bonds of minimal length.31 mm (12 mils). Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 916, Norwood, MA 262-916, U.S.A. Tel: 81.329.4 6 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
* PRODUCT PAGE QUICK LINKS Last Content Update: 11/29/ COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Application Notes Broadband Biasing of Amplifiers General Application Note MMIC Amplifier Biasing Procedure Application Note Thermal Management for Surface Mount Components General Application Note : GaAs, phemt, MMIC, Power Amplifier, 2 GHz to GHz TOOLS AND SIMULATIONS S-Parameter REFERENCE MATERIALS Press Distributed Power Amplifiers Cover 2- GHz to Simplify Instrumentation and Microwave Radio Applications Product Selection Guide RF, Microwave, and Millimeter Wave IC Selection Guide DESIGN RESOURCES Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
TABLE OF CONTENTS Features... 1 Applications... 1 Functional Block Diagram... 1 General Description... 1 Revision History... 2 Electrical Specifications... 3 2 GHz to 1 GHz Frequency Range... 3 1 GHz to 26 GHz Frequency Range... 3 26 GHz to 4 GHz Frequency Range... 4 4 GHz to GHz Frequency Range... 4 Absolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions...6 Interface Schematics... Typical Performance Characteristics...8 Applications Information... 13 Mounting and Bonding Techniques for Millimeterwave GaAs MMICs... 13 Application Circuit... 1 Assembly Diagram... 1 Outline Dimensions... 16 Ordering Guide... 16 REVISION HISTORY 2/16 Rev. A to Rev. B Change to Features Section... 1 Updated Outline Dimensions... 16 /1 Rev..1114 to Rev. A This Hittite Microwave Products data sheet has been reformatted to meet the styles and standards of Analog Devices, Inc. Updated Format... Universal Changes to Table... Added Applications Information Section and Figure 3... 13 Added Ordering Guide Section... 16 Rev. B Page 2 of 16
ELECTRICAL SPECIFICATIONS 2 GHz TO 1 GHz FREQUENCY RANGE TA = 2 C, VDD = V, VGG2 = 1.4 V, IDD = 6 ma, unless otherwise stated. Adjust VGG1 between 2 V to V to achieve IDD = 6 ma typical. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE 2 1 GHz GAIN 8 11 db Gain Variation Over Temperature.2 db/ C RETURN LOSS Input 12 db Output 14 db OUTPUT Output Power for 1 db Compression P1dB 14. 1. dbm Saturated Output Power PSAT dbm Output Third-Order Intercept IP3 Measurement taken at POUT/tone = 1 dbm 31 dbm NOISE FIGURE 4. TOTAL SUPPLY CURRENT IDD VDD = 4 V, VDD = V, VDD = 6 V, VDD = V, or VDD = 8 V 6 ma 1 GHz TO 26 GHz FREQUENCY RANGE TA = 2 C, VDD = V, VGG2 = 1.4 V, IDD = 6 ma, unless otherwise stated. Adjust VGG1 between 2 V to V to achieve IDD = 6 ma typical. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE 1 26 GHz GAIN 8 1. db Gain Variation Over Temperature. db/ C RETURN LOSS Input 14 db Output 2 db OUTPUT Output Power for 1 db Compression P1dB 14. 1. dbm Saturated Output Power PSAT dbm Output Third-Order Intercept IP3 Measurement taken at POUT/tone = 1 dbm 28 dbm NOISE FIGURE 4 TOTAL SUPPLY CURRENT IDD VDD = 4 V, VDD = V, VDD = 6 V, VDD = V, or VDD = 8 V 6 ma Rev. B Page 3 of 16
26 GHz TO 4 GHz FREQUENCY RANGE TA = 2 C, VDD = V, VGG2 = 1.4 V, IDD = 6 ma, unless otherwise stated. Adjust VGG1 between 2 V to V to achieve IDD = 6 ma typical. Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE 26 4 GHz GAIN 8 11 db Gain Variation Over Temperature. db/ C RETURN LOSS Input 2 db Output 8 db OUTPUT Output Power for 1 db Compression P1dB 13 16 dbm Saturated Output Power PSAT 2. dbm Output Third-Order Intercept IP3 Measurement taken at POUT/tone = 1 dbm 28 dbm NOISE FIGURE 4 TOTAL SUPPLY CURRENT IDD VDD = 4 V, VDD = V, VDD = 6 V, VDD = V, or VDD = 8 V 6 ma 4 GHz TO GHz FREQUENCY RANGE TA = 2 C, VDD = V, VGG2 = 1.4 V, IDD = 6 ma, unless otherwise stated. Adjust VGG1 between 2 V to V to achieve IDD = 6 ma typical. Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE 4 GHz GAIN 8 1. db Gain Variation Over Temperature.9 db/ C RETURN LOSS Input 12 db Output 12 db OUTPUT Output Power for 1 db Compression P1dB 1 13 dbm Saturated Output Power PSAT 18 dbm Output Third-Order Intercept IP3 Measurement taken at POUT/tone = 1 dbm 24 dbm NOISE FIGURE TOTAL SUPPLY CURRENT IDD VDD = 4 V, VDD = V, VDD = 6 V, VDD = V, or VDD = 8 V 6 ma Rev. B Page 4 of 16
ABSOLUTE MAXIMUM RATINGS Table. Parameter Drain Bias Voltage (VDD) Gate Bias Voltage VGG1 VGG2 Rating 8. V 3 V to V For VDD = 8 V 1 3.6 V For VDD = V 3. V For VDD = 6 V >2. V For VDD = 4 V to V >1.2 V RF Input Power (RFIN) 22 dbm Channel Temperature 1 C Continuous Power Dissipation, PDISS 1.91 W (TA = 8 C, Derate.3 mw/ C at 8 C) Thermal Resistance, RTH (Channel to 4 C/W 2 Bottom of Die) Storage Temperature 6 C to +1 C Operating Temperature C to +8 C ESD Sensitivity, Human Body Model (HBM) Class 1A, passed 2 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 1 IDD < 1 ma. 2 Based upon a thermal epoxy of 2 W/ C. Rev. B Page of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V DD 2 RFIN 1 TOP VIEW (Not to Scale) 3 RFOUT 4 V GG 1 V GG 2 1383-2 Figure 2. Pad Configuration Table 6. Pad Function Descriptions Pad No. Mnemonic Description 1 RFIN RF Input. This pin is ac-coupled and matched to Ω. 2 VDD Power Supply Voltage with Integrated RF Choke. Connect dc bias to this pin to provide drain current (IDD). 3 RFOUT RF Output. This pin is ac-coupled and matched to Ω. 4 VGG2 Gate Control 2 for Amplifier. Attach bypass capacitors as shown in Figure 38. For nominal operation, apply 1.4 V to VGG2. VGG1 Gate Control 1 for Amplifier. Attach bypass capacitors as shown in Figure 38. Adjust this pin to achieve IDD = 6 ma. Die Bottom GND Die bottom must be connected to RF/dc ground. Rev. B Page 6 of 16
INTERFACE SCHEMATICS RFIN 1383-29 Figure 3. RFIN Interface Schematic V GG 2 Figure 6. VGG2 Interface Schematic 1383-32 V DD 1383-3 V GG 1 1383-33 Figure 4. VDD Interface Schematic Figure. VGG1 Interface Schematic RFOUT Figure. RFOUT Interface Schematic 1383-31 GND 1383-34 Figure 8. GND Interface Schematic Rev. B Page of 16
TYPICAL PERFORMANCE CHARACTERISTICS 2 1 16 14 C +2 C +8 C RESPONSE (db) 1 2 GAIN (db) 12 1 8 3 S11 S S22 4 1 1 2 2 3 3 4 4 Figure 9. Response (Gain and Return Loss) vs. Frequency 1383-3 6 4 1 1 2 2 3 3 4 4 Figure 12. Gain vs. Frequency at Various Temperatures 1383-6 C +2 C +8 C C +2 C +8 C 1 1 RETURN LOSS (db) 2 RETURN LOSS (db) 2 3 3 4 1 1 2 2 3 3 4 4 Figure 1. Input Return Loss vs. Frequency at Various Temperatures 1383-4 4 1 1 2 2 3 3 4 4 Figure 13. Output Return Loss vs. Frequency at Various Temperatures 1383-18 16 4V V 6V V 8V 18 16 6mA 8mA 9mA 1mA 14 14 GAIN (db) 12 GAIN (db) 12 1 1 8 8 6 1 1 2 2 3 3 4 4 Figure 11. Gain vs. Frequency at Various Supply Voltages (VDD) (For VDD = 4 V, VGG2 = 1.4 V; for VDD = V, VGG2 = 1.4 V; for VDD = 6 V, VGG2 = 2 V; for VDD = V, VGG2 = 3 V; for VDD =8 V, VGG2 = 3.6 V) 1383-6 1 1 2 2 3 3 4 4 Figure 14. Gain vs. Frequency at Various Supply Currents (IDD) (For VDD = V, VGG2 = 1.4 V) 1383-8 Rev. B Page 8 of 16
2 C +2 C +8 C 2 4V V 6V V 8V P1dB (dbm) 1 1 13 P1dB (dbm) 1 1 13 11 11 9 9 2 6 1 14 18 22 26 3 34 38 42 46 Figure 1. P1dB vs. Frequency at Various Temperatures 1383-9 2 6 1 14 18 22 26 3 34 38 42 46 Figure 18. P1dB vs. Frequency at Various Supply Voltages (For VDD = 4 V, VGG2 = 1.4 V; for VDD = V, VGG2 = 1.4 V; for VDD = 6 V, VGG2 = 2 V; for VDD = V, VGG2 = 3 V; for VDD =8 V, VGG2 = 3.6 V) 1383-12 2 C +2 C +8 C 2 P SAT (dbm) 1 1 13 P SAT (dbm) 1 1 13 11 11 9 2 6 1 14 18 22 26 3 34 38 42 46 Figure 16. PSAT vs. Frequency at Various Temperatures 1383-1 9 4V V 6V V 8V 2 6 1 14 18 22 26 3 34 38 42 46 Figure. PSAT vs. Frequency at Various Supply Voltages (For VDD = 4 V, VGG2 = 1.4 V; for VDD = V, VGG2 = 1.4 V; for VDD = 6 V, VGG2 = 2 V; for VDD = V, VGG2 = 3 V; for VDD =8 V, VGG2 = 3.6 V) 1383-13 2 6mA 8mA 9mA 1mA 2 6mA 8mA 9mA 1mA P1dB (dbm) 1 1 13 P SAT (dbm) 1 1 13 11 11 9 9 2 6 1 14 18 22 26 3 34 38 42 46 Figure 1. P1dB vs. Frequency at Various Supply Currents (For VDD = V, VGG2 = 1.4 V) 1383-11 2 6 1 14 18 22 26 3 34 38 42 46 Figure 2. PSAT vs. Frequency at Various Supply Currents (For VDD = V, VGG2 = 1.4 V) 1383-14 Rev. B Page 9 of 16
3 33 31 C +2 C +8 C 3 33 31 4V V 6V V 8V 29 29 IP3 (dbm) 2 2 IP3 (dbm) 2 2 1 1 1 2 6 1 14 18 22 26 3 34 38 42 46 Figure. Output IP3 vs. Frequency for Various Temperatures, POUT = dbm/tone 1383-1 1 2 6 1 14 18 22 26 3 34 38 42 46 Figure 24. Output IP3 vs. Frequency for Various Supply Voltages, POUT = dbm/tone (For VDD = 4 V, VGG2 = 1.4 V; for VDD = V, VGG2 = 1.4 V; for VDD = 6 V, VGG2 = 2 V; for VDD = V, VGG2 = 3 V; for VDD =8 V, VGG2 = 3.6 V) 1383-18 3 33 31 29 6mA 8mA 9mA 1mA 8 6 2GHz 1GHz 2GHz 3GHz 4GHz GHz IP3 (dbm) 2 2 IM3 (dbc) 4 3 2 1 1 1 2 6 1 14 18 22 26 3 34 38 42 46 Figure 22. Output IP3 vs. Frequency for Various Supply Currents, POUT = dbm/tone (For VDD = V, VGG2 = 1.4 V) 1383-16 2 1 4 1 P OUT /TONE (dbm) Figure 2. Output IM3 vs. POUT/Tone at VDD = 4 V, VGG2 = 1.4 V 1383-8 6 2GHz 1GHz 2GHz 3GHz 4GHz GHz 8 6 2GHz 1GHz 2GHz 3GHz 4GHz GHz IM3 (dbc) 4 3 IM3 (dbc) 4 3 2 2 1 1 2 1 4 1 P OUT /TONE (dbm) Figure. Output Third-Order Intermodulation (IM3) vs. POUT/Tone at VDD = V, VGG2 = 1.4 V 1383-1 2 1 4 1 P OUT /TONE (dbm) Figure 26. Output IM3 vs. POUT/Tone at VDD = 6 V, VGG2 = 2 V 1383-2 Rev. B Page 1 of 16
8 6 2GHz 1GHz 2GHz 3GHz 4GHz GHz 8 6 2GHz 1GHz 2GHz 3GHz 4GHz GHz IM3 (dbc) 4 3 IM3 (dbc) 4 3 2 2 1 1 2 1 4 1 P OUT /TONE (dbm) 1383-2 1 4 1 P OUT /TONE (dbm) 1383-24 Figure 2. Output IM3 vs. POUT/Tone at VDD = V, VGG2 = 3 V Figure 3. Output IM3 vs. POUT/Tone at VDD = 8 V, VGG2 = 3.6 V 8 8 6 6 NOISE FIGURE (db) 4 3 NOISE FIGURE (db) 4 3 2 1 C +2 C +8 C 1 8 1 22 29 36 43 Figure 28. Noise Figure vs. Frequency at Various Temperatures 1383-22 2 4V V 1 6V V 8V 1 8 1 22 29 36 43 Figure 31. Noise Figure vs. Frequency at Various Supply Voltages (For VDD = 4 V, VGG2 = 1.4 V; for VDD = V, VGG2 = 1.4 V; for VDD = 6 V, VGG2 = 2 V; for VDD = V, VGG2 = 3 V; for VDD =8 V, VGG2 = 3.6 V) 1383-2 8 6mA 8mA 9mA 1mA 1 C +2 C +8 C 6 2 NOISE FIGURE (db) 4 3 2 ISOLATION (db) 3 4 1 6 1 8 1 22 29 36 43 Figure 29. Noise Figure vs. Frequency at Various Supply Currents (For VDD = V, VGG2 = 1.4 V) 1383-1 1 2 2 3 3 4 4 Figure 32. Reverse Isolation vs. Frequency for Various Temperatures (For VDD = V, VGG2 = 1.4 V) 1383-26 Rev. B Page 11 of 16
P OUT (dbm), GAIN (db), PAE (%) 2 2 1 1 P OUT GAIN PAE I DD 11 1 9 8 I DD (ma) POWER DISSIPATION (W).6...4.4.3.3 2GHz 1GHz 2GHz 3GHz 4GHz GHz.2 6 1 1 1 INPUT POWER (dbm) Figure 33. Power Compression at 24 GHz 1383-2.2 6 4 2 2 4 6 8 1 12 14 INPUT POWER (dbm) Figure 34. Power Dissipation at 8 C vs. Input Power at Various Frequencies 1383-28 Rev. B Page 12 of 16
APPLICATIONS INFORMATION The is a GaAs, phemt, MMIC, cascode distributed power amplifier. The cascode distributed amplifier uses a fundamental cell of two FETs in series, source to drain. This fundamental cell then duplicates a number of times. The major benefit of this is an increase in the operation bandwidth. The basic schematic for a fundamental cell is given in Figure 3. V DD.12mm (.4") THICK GaAs MMIC.6mm (.3") WIRE BOND RF GROUND PLANE V GG 2 RFIN V GG 1 RFOUT Figure 3. Fundamental Cell Schematic The recommended bias sequence during power up is the following: 1. Connect GND. 2. Set VGG1 to 2 V. 3. Set VDD to V. 4. Set VGG2 to 1.4 V.. Increase VGG1 to achieve a typical quiescent current (IDQ) = 6 ma. 6. Apply the RF signal. The recommended bias sequence during power down is the following: 1. Turn off the RF signal. 2. Decrease VGG1 to 2 V to achieve IDQ = ma. 3. Decrease VGG2 to V. 4. Decrease VDD to V.. Increase VGG1 to V. MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Attach the die directly to the ground plane eutectically or with conductive epoxy (see the Handling Precautions section, the Mounting section, and the Wire Bonding section). Microstrip, Ω, transmission lines on.12 mm ( mil) thick alumina, thin film substrates are recommended for bringing the radio frequency to and from the chip (see Figure 36). When using.24 mm (1 mil) thick alumina, thin film substrates, raise the die.1 mm (6 mils) to ensure that the surface of the die is coplanar with the surface of the substrate. One way to accomplish this is to attach the.12 mm (4 mil) thick die to a.1 mm (6 mil) thick, molybdenum (Mo) heat spreader (moly tab) which can then be attached to the ground plane (see Figure 36 and Figure 3). 1383-39.12mm (.") THICK ALUMINA THIN FILM SUBSTRATE Figure 36. Die Without the Moly Tab.12mm (.4") THICK GaAs MMIC.6mm (.3") WIRE BOND RF GROUND PLANE.1mm (.") THICK MOLY TAB.24mm (.1") THICK ALUMINA THIN FILM SUBSTRATE Figure 3. Die With the Moly Tab Place microstrip substrates as close to the die as possible to minimize bond wire length. Typical die to substrate spacing is.6 mm to.12 mm (3 mil to 6 mil). Handling Precautions To avoid permanent damage, follow these storage, cleanliness, static sensitivity, transient, and general handling precautions: Place all bare die in either waffle or gel-based ESD protective containers and then seal the die in an ESD protective bag for shipment. Once the sealed ESD protective bag is opened, store all die in a dry nitrogen environment. Handle the chips in a clean environment. Do not attempt to clean the chip using liquid cleaning systems. Follow ESD precautions to protect against ESD strikes. While bias is applied, suppress instrument and bias supply transients. Use shielded signal and bias cables to minimize inductive pick up. Handle the chip along the edges with a vacuum collet or with a sharp pair of bent tweezers. The surface of the chip may have fragile air bridges and must not be touched with vacuum collet, tweezers, or fingers. 1383-3 1383-38 Rev. B Page 13 of 16
Mounting The chip is back metallized and can be die mounted with AuSn eutectic preforms or with electrically conductive epoxy. Ensure that the mounting surface is clean and flat. When eutectic die attached, an 8/2 gold tin preform is recommended with a work surface temperature of 2 C and a tool temperature of 26 C. When hot 9/1 nitrogen/hydrogen gas is applied, ensure that tool tip temperature is 29 C. Do not expose the chip to a temperature greater than 32 C for more than 2 seconds. For attachment, no more than 3 seconds of scrubbing is required. When epoxy die attached, apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip once it is placed into position. Cure epoxy per the schedule of the manufacturer. Wire Bonding RF bonds made with two 1 mil wires are recommended. Ensure that these bonds are thermosonically bonded with a force of 4 grams to 6 grams. DC bonds of an.1 (.2 mm) diameter, thermosonically bonded, are recommended. Make ball bonds with a force of 4 grams to grams and wedge bonds with a force of 18 grams to 22 grams. Make all bonds with a nominal stage temperature of 1 C. Apply a minimum amount of ultrasonic energy to achieve reliable bonds. Make all bonds as short as possible, less than 12 mils (.31 mm). Rev. B Page 14 of 16
APPLICATION CIRCUIT V DD.1µF 1pF 2 RFIN 1 4 3 RFOUT V GG 1.1µF 1pF 1pF.1µF V GG 2 1383-36 Figure 38. Application Circuit ASSEMBLY DIAGRAM TO V DD SUPPLY.1µF ALL BOND WIRES ARE 1MIL DIAMETER 1pF 3MIL NOMINAL GAP Ω TRANSMISSION LINE 1pF 1pF.1µF.1µF TO V GG 1 SUPPLY Figure 39. Assembly Diagram TO V GG 2 SUPPLY 1383-3 Rev. B Page 1 of 16
OUTLINE DIMENSIONS.629.1 2.299.1.1. 2.1.2 3.1.2 1.449.2.2 1.6.28 4 TOP VIEW (CIRCUIT SIDE).9 1.39.1.1.1 Figure 4. -Pad Bare Die [CHIP] (C--4) Dimensions shown in millimeters.9 SIDE VIEW ORDERING GUIDE Model 1 Temperature Range Package Description Package Option C to +8 C -Pad Bare Die [CHIP] C--4 1 The is RoHS Compliant. 1--6-B 6 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D1383--2/16(B) Rev. B Page 16 of 16