Naghmeh Karimi Assistant Professor Department of Computer Science and Electrical Engineering University of Maryland, Baltimore County (UMBC) Address: 1000 Hilltop Circle, ITE 314 Baltimore, Maryland 21250 Email: naghmeh.karimi@umbc.edu Phone: 410-455-3965 Fax: 410-465-3969 Web: http://www.csee.umbc.edu/~nkarimi/ Research Interests: Hardware Security and Design-for-Trust Fault Tolerance and Design-for-Reliability VLSI Testing and Design-for-Testability VLSI and Electronic Circuits Hardware Design and Synthesis Internet of Things Computer Architecture Computer Aided Design Education: Ph.D. in Electrical Engineering, 2010 Thesis: Concurrent Self-Testing of SoCs at Component Level Advisor: Zainalabedin Navabi, Co-advisors: Yiorgos Makris & Mehdi Sedighi M.Sc. in Hardware Computer Engineering, 2002 Thesis: Automatic Testability Enhancement in RTL Domain Advisor: Zainalabedin Navabi, Co-advisor: Mehrdad Nourani B.Sc. in Hardware Computer Engineering, 1997 Advisor: Zainalabedin Navabi Professional Positions: University of Maryland, Baltimore County (UMBC) Assistant Professor, CSEE Department, Jan 2017-present Assistant Teaching Professor, ECE Department, Sep. 2015-Dec 2016 Visiting Assistant Professor, ECE Department, Sep. 2014-Sep. 2015 New York University Visiting Assistant Professor, ECE Department, Sep. 2012-Sep. 2014 New York University Postdoctoral Researcher, ECE Department, Feb. 2012-Sep. 2012 Duke University Postdoctoral Researcher, ECE Department, Feb. 2011-Feb.2012 1/5
Yale University Visiting Researcher, EE Department, July 2007-July 2009 Teaching Assistant, Spring 2009 University Of Kashan Lecturer, Sep. 2010- Sep. 2011 University Of Tehran Lecturer, Sep. 2003-Dec. 2006 Research Assistant, Sep. 1999- Sep. 2003 Teaching Assistant, Fall 2002 Selected Publications: Book Chapters: [1] N. Karimi and Z. Navabi, VHDL-AMS Hardware Description Language, In The VLSI Handbook, 2nd Edition, Chapter 91, Section XIII, CRC Press, USA, 2006. [2] N. Karimi and Z. Navabi, ASIC and Custom IC Cell Information Representation, In The VLSI Handbook, 2nd Edition, Chapter 93, Section XIII, CRC Press, USA, 2006. [3] N. Karimi and Z. Navabi, Timing Description Languages, In The VLSI Handbook, 2nd Edition, Chapter 95, Section XIII, CRC Press, USA. Journal Papers: [1] N. Karimi, A. Kanuparthi, X. Wang, O. Sinanoglu, and R. Karri, MAGIC: Malicious Aging in Circuits/Cores, ACM Trans. on Architecture and Code Optimization (TACO), vol. 12, no. 1, pp. 5.1-5.25, 2015. [2] S. Kannan, N. Karimi, O. Sinanoglu, and R. Karri, Security Vulnerability of Emerging Non-Volatile Main Memories and Countermeasures, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 1, pp. 2-15, 2015. [3] S. Kannan, N. Karimi, R. Karri, and O. Sinanoglu, Modeling, Detection, and Diagnosis of Faults in Multi- Level Memristor Memories, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.34, no.5, pp. 822-834, 2015. [4] A. DeTrano, N. Karimi, R. Karri, X. Guo, C. Carlet, S. Guilley, Exploiting Small Leakages in Masks to Turn a Second-Order Attack into a First-Order Attack and Improved Rotating Substitution Box Masking with Linear Code Cosets, The Scientific World Journal, vol. 2015, pp. 1-10, 2015. [5] N. Karimi and K. Chakrabarty, Detection, Diagnosis and Recovery from Clock-Domain Crossing Failures in Multi-Clock SoCs, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 9, pp. 1395-1408, 2013. [6] N. Karimi, M. Maniatakos, C. Tirumurti, and Y. Makris, On the Impact of Performance Faults in Modern Microprocessors, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 29, no. 3, pp. 351-366, 2013. [7] N. Karimi, M. Maniatakos, A. Jas, C. Tirumurti, and Y. Makris, Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor, IEEE Trans. on Computers (TCOMP), vol. 60, no. 9, pp. 1274-1287, 2011. [8] M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, and Y. Makris, Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller, IEEE Trans. on Computers (TCOMP), vol. 60, no. 9, pp. 1260-1273, 2011. [9] N. Karimi, A. Alaghi, M. Sedghi, and Z. Navabi, Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults, Journal of Universal Computer Science (JUCS), vol. 14, no. 22, pp. 3716-3736, 2008. 2/5
Conf. Papers: [1] N. Karimi, J. Danger, F. Lozac'h, and S. Guilley, Predictive Aging of Reliability of two Delay PUFs, Proc. Int l Conf. on Security, Privacy and Applied Cryptographic Engineering (SPACE), accepted for publication, 2016. [2] N. Karimi and K. Huang, Prognosis of NBTI Aging Using a Machine Learning Scheme, Proc. Int l Symp. on Defect and Fault Tolerance of VLSI Systems (DFTS), 2016, pp. 7-10. [3] X. Guo, N. Karimi, F. Regazzoni, C.Jin, and R. Karri Simulation and Analysis of Negative-Bias Temperature Instability Aging on Power Analysis Attacks, Proc. Hardware-Oriented Security and Trust Symp. (HOST), 2015, pp. 124-129. [4] A. DeTrano, S. Guilley, X. Guo, N. Karimi, R. Karri, Exploiting Small Leakages in Masks to Turn a Second-Order Attack into a First-Order Attack, Proc. Hardware and Architectural Support for Security and Privacy (HASP), 2015, pp. 7:1-7:5. [5] S. Kannan, N. Karimi, and O. Sinanoglu, Secure Memristor-Based Main Memory, Proc. Design Automation Conf. (DAC), 2014, pp.1-6. [6] S. Kannan, N. Karimi, R. Karri, and O. Sinanoglu, Detection, Diagnosis, and Repair of Faults in Memristor-Based Memories, Proc. VLSI Test Symp. (VTS), 2014, pp.1-6. [7] O. Sinanoglu, N. Karimi, J. Rajendran, R. Karri, Y. Jin, K. Huang, and Y. Makris, Reconciling the IC Test and Security Dichotomy, Proc. European Test Symp. (ETS), 2013, pp. 1-6. [8] N. Karimi, K. Chakrabarty, P. Gupta, and S. Patil, Test Generation for Clock Domain Crossing Faults in Integrated Circuits, Proc. Design Automation & Test in Europe Conf. (DATE), 2012, pp. 406-411. [9] N. Karimi, Z. Kong, K. Chakrabarty, P. Gupta, and S. Patil, Testing of Clock-Domain Crossing Faults in Multi-Core System-on-Chip, Proc. Asian Test Symp. (ATS), 2011, pp. 7-14. [10] N. Karimi, S. Sadeghi, and Z. Navabi, Network-on-Chip Concurrent Error Recovery Using Functional Switch Faults, Proc. Workshop on RTL and High Level Testing (WRTLT), 2010. [11] N. Karimi, M. Maniatakos, C. Tirumurti, A. Jas, and Y. Makris, Impact Analysis of Performance Faults in Modern Microprocessors, Proc. Int l. Conf. on Computer Design (ICCD), 2009, pp. 91-96. [12] M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, and Y. Makris, Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller, Proc. VLSI Test Symp. (VTS), 2009, pp. 9-14. [13] N. Karimi, M. Maniatakos, Y. Makris, and A. Jas, On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors, Proc. Int l. Test Conf. (ITC), 2008, pp. 24.1.1-24.1.10. [14] A. Alaghi, M. Sedghi, N. Karimi, and Z. Navabi, NoC Reconfiguration for Utilizing the Largest Fault- Free Connected Sub-Structure, Proc. Int l. Test Conf. (ITC), 2008, pp.1-1. [15] M. Maniatakos, N. Karimi, Y. Makris, A. Jas, and C. Tirumurti, Design and Evaluation of a Timestamp- Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller, Proc. Int l Symp. on Defect and Fault Tolerance of VLSI Systems (DFTS), 2008, pp. 454-462. [16] A. Alaghi, M. Sedghi, N. Karimi, M. Fathy, and Z. Navabi, Reliable NoC Architecture Utilizing a Robust Rerouting Algorithm, Proc. Int l East-West Design and Test Symp. (EWDTS), 2008, pp. 200-203. [17] N. Karimi, S. Aminzadeh, S. Safari, and Z. Navabi, A Novel GA-Based High-Level Synthesis Technique to Enhance RT-level Concurrent Testing, Proc. Int l. Online Test Symp. (IOLTS), 2008, pp. 173-174. [18] A. Alaghi, N. Karimi, M. Sedghi, and Z. Navabi, Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model, Proc. Int l. Symp. on Defect and Fault Tolerance of VLSI Systems (DFTS), 2007, pp. 21-30. [19] N. Karimi, S. Mirkhani, Z. Navabi, and F. Lombardi, RT Level Reliability Enhancement by Constructing Dynamic TMRs, Proc. ACM Great Lakes Symp. on VLSI (GlSVLSI), 2007, pp. 172-175. [20] N. Karimi, and Z. Navabi, A Dynamic Reconfiguration Method for Error Recovery of RT Level Designs, Proc. Int l. East-West Design and Test Symp. (EWDTS), 2007, pp. 249-254. [21] N. Karimi, S. Mirkhani, and Z. Navabi, ESTA: An Efficient Method for Reliability Enhancement of RT- Level Designs, Proc. Asian Test Symp. (ATS), 2006, pp. 195-202. 3/5
[22] N. Karimi, P. Riahi, and Z. Navabi, A Survey of Testability Measurements at Various Abstraction Levels, Proc. North Atlantic Test Workshop (NATW), 2003, pp. 26-33. [23] P. Riahi, Z. Navabi, N. Karimi, and F. Lombardi, A VPI-Based IP Core Serial Fault Simulation and Test Generation Methodology, Proc. North Atlantic Test Workshop (NATW), 2003, pp. 96-103. Teaching Experience: Graduate Course: 16:332:576 - Testing of VLSI Circuits (Spring 15-16) Undergraduate Course: 14:332:436 - VLSI Testing (Spring 15-16) Undergraduate Course: 14:332:331 - Computer Architecture & Assembly Language (Spring 15-16, Fall16) Graduate Course: 16:332:563 - Computer Architecture I (Fall 14-16) Graduate Course: 16:332:574 - CAD Digital VLSI Design (Fall 14-15) Undergraduate Course: 14:332:479 - VLSI Design (Fall 14-15) New York University (NYU-Poly) Graduate Course: EL6493 - VLSI System Testing (Fall 12-13) Graduate Course: EL5473 - Introduction to VLSI design (Spring 13) Graduate Course: EE9953 - Advanced project I (Spring 14) Undergraduate Course: EE3193 - Introduction to Very Large Scale Integrated Circuits (Spring 13-14) University of Tehran Undergraduate Course: Graph Theory (Fall 03 Spring 04) Undergraduate Course: Discrete Mathematics (Fall 04 06) University of Kashan Graduate Course: Advanced Computer Architecture (Spring 10 Fall 10) Undergraduate Course: Digital Logic Design (Spring 10 Fall 10) Honors and Awards: 1st place of innovation award, Capstone Project, ECE,, 2016 (Undergrad students) 2-year visiting faculty fellowship, School of Engineering, New York University, 2012-2014. 1-year postdoctoral scholarship, VLSI Testing Lab, Duke University, 2011-2012. Travel grant, Young Faculty Workshop in Design Automation Conf. (DAC), USA, 2012 Travel grant, Workshop on Diversity on Design Automation and Test (WD2AT), USA, 2011 Ph.D. Thesis Award, Iran Nanotechnology initiative council, 2010 2-year visiting assistant in research scholarship, TRELA Lab, Yale University, 2007-2009. Travel grant, Ph.D. Forum Design and Automation in Europe Conf. (DATE), Germany, 2006 Ph.D. Research Award, ECE Department, University of Tehran, 2006 1 st in Ph.D. Entrance Exam, Computer Engineering, University of Tehran, 2002 Ranked under 100 in Computer Olympiad among all high school students, Iran, 1992 1 st in Provincial Scientific Competitions, Iran, 1990, 1992 Professional Service: Program Committee IEEE Int l Test Conf. (ITC 2015, 2016) IEEE Int l Conf. on VLSI Design (VLSID 2016, 2017) IEEE Asian Test Symp. (ATS 2016) IEEE Great Lakes Symp. on VLSI (GLSVLSI 2017) IEEE North Atlantic Test Workshop (NATW 2016) 4/5
IEEE Int l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Sys. (DFTS 2014, 2015, 2016) IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2014, 2015, 2016) Organizing Committee IEEE VLSI Test Symp. (VTS 2017) Technical Referee IEEE Transactions on Computers (TCOMP) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) IEEE Transactions on Very Large Scale Integration Systems (TVLSI) ACM Journal of Emerging Technologies in Computing (JETC) ACM Transactions on Design Automation of Electronic Systems (TODAES) Elsevier Journal of Microprocessors and Microsystems - Embedded Hardware Design (MICPRO) Journal of Electronic Testing: Theory and Applications (JETTA) IEEE Design & Test of Computers IEEE Int l Test Conf. (ITC) IEEE VLSI Test Symp. (VTS) IEEE Design and Automation Conf. (DAC) IEEE Design Automation and Test in Europe (DATE) IEEE Int l Symp. on Hardware-Oriented Security and Trust (HOST) IEEE Int l Conf. of Computer-Aided Design (ICCD) IEEE European Test Symp. (ETS) IEEE Asian Test Symp. (ATS) IEEE On-line Testing Symp. (IOLTS) IEEE Int l Conf. on Electronics, Circuits, and Systems (ICECS) Session Chair IEEE Int l Test Conf. (ITC 2015) IEEE VLSI Test Symp. (VTS 2014, 2016) IEEE Int l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS 2013, 2016) IEEE/ACM Int l Symp. on NanoScale Architectures (NANOARCH 2013) Workshop on Trustworthy Hardware (2013) Judge for Best paper Award IEEE/ACM Int l Symp. on NanoScale Architectures (NANOARCH 2013) IEEE Int l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS 2016) Invited Talk: Stevens Institute of Technology, 2014 Title: Improving Reliability of Modern Microprocessors IEEE VLSI Test Symp. (VTS), Elevator Talk, 2014 Title: Malicious Aging Acceleration in Processors IEEE VLSI Test Symp. (VTS), Elevator Talk, 2013 Title: Accelerating NBTI Aging to Wear out Digital Circuits 5/5