Power MOSFET PRODUCT SUMMRY V DS (V) 600 R DS(on) ( ) V GS = 0 V 0.75 Q g (Max.) (nc) 49 Q gs (nc) 3 Q gd (nc) 20 Configuration Single G D 2 PK (TO-263) D S Note a. See device orientation. G N-Channel MOSFET Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Starting T J = 25 C, L = 6.8 mh, R g = 25, I S = 9.2 (see fig. 2). c. I SD 9.2, di/dt 50 /μs, V DD V DS, T J 50 C. d..6 mm from case. D S FETURES Halogen-free ccording to IEC 6249-2-2 Definition Low Gate Charge Q g results in Simple Drive Requirement Improved Gate, valanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and valanche Voltage and Current Compliant to RoHS Directive 2002/95/EC PPLICTIONS Switch Mode Power Supply (SMPS) Uninterruptible Power Supply High Speed Power Switching PPLICBLE OFF LINE SMPS TOPOLOGIES ctive Clamped Forward Main Switch ORDERING INFORMTION Package D 2 PK (TO-263) D 2 PK (TO-263) D 2 PK (TO-263) Lead (Pb)-free and Halogen-free SiHFS9N60-GE3 SiHFS9N60TRR-GE3 a SiHFS9N60TRL-GE3 a Lead (Pb)-free IRFS9N60PbF IRFS9N60TRRPbF a IRFS9N60TRLPbF a SiHFS9N60-E3 SiHFS9N60TR-E3 a SiHFS9N60TL-E3 a BSOLUTE MXIMUM RTINGS (T C = 25 C, unless otherwise noted) PRMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 600 V Gate-Source Voltage V GS ± 30 Continuous Drain Current V GS at 0 V T C = 25 C 9.2 I D T C = 00 C 5.8 Pulsed Drain Current a I DM 37 Linear Derating Factor.3 W/ C Single Pulse valanche Energy b E S 290 mj Repetitive valanche Current a I R 9.2 Repetitive valanche Energy a E R 7 mj Maximum Power Dissipation T C = 25 C P D 70 W Peak Diode Recovery dv/dt c dv/dt 5.0 V/ns Operating Junction and Storage Temperature Range T J, T stg - 55 to 50 Soldering Recommendations (Peak Temperature) for 0 s 300 d C * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 9287 www.vishay.com S-054-Rev. C, 30-May- THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?9000
THERML RESISTNCE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junction-to-mbient R thj - 40 C/W Maximum Junction-to-Case (Drain) R thjc - 0.75 SPECIFICTIONS (T J = 25 C, unless otherwise noted) PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static Drain-Source Breakdown Voltage V DS V GS = 0, I D = 250 μ 600 - - V V DS Temperature Coefficient V DS /T J Reference to 25 C, I D = m - 0.66 - V/ C Gate-Source Threshold Voltage V GS(th) V DS = V GS, I D = 250 μ 2.0-4.0 V Gate-Source Leakage I GSS V GS = ± 30 V - - ± 00 n V DS = 600 V, V GS = 0 V - - 25 Zero Gate Voltage Drain Current I DSS V DS = 480 V, V GS = 0 V, T J = 25 C - - 250 μ Drain-Source On-State Resistance R DS(on) V GS = 0 V I D = 5.5 b - - 0.75 Forward Transconductance g fs V DS = 25 V, I D = 3. 5.5 - - S Dynamic Input Capacitance C iss V GS = 0 V, - 400 - Output Capacitance C oss V DS = 25 V, - 80 - f =.0 MHz, see fig. 5 Reverse Transfer Capacitance C rss - 7. - pf V DS =.0 V, f =.0 MHz - 957 - Output Capacitance C oss V GS = 0 V V DS = 480 V, f =.0 MHz - 49 - Effective Output Capacitance C oss eff. V DS = 0 V to 480 V c - 96 - Total Gate Charge Q g - - 49 Gate-Source Charge Q gs I V GS = 0 V D = 9.2, V DS = 400 V see fig. 6 and 3 b - - 3 nc Gate-Drain Charge Q gd - - 20 Turn-On Delay Time t d(on) - 3 - Rise Time t r V DD = 300 V, I D = 9.2-25 - R g = 9., R D = 35.5 Turn-Off Delay Time t d(off) see fig. 0 b - 30 - ns Fall Time t f - 22 - Drain-Source Body Diode Characteristics MOSFET symbol Continuous Source-Drain Diode Current I S showing the - - 9.2 D integral reverse G Pulsed Diode Forward Current a I SM p - n junction diode - - 37 Body Diode Voltage V SD T J = 25 C, I S = 9.2, V GS = 0 V b - -.5 V Body Diode Reverse t rr - 530 800 ns Recovery Time T J = 25 C, I F = 9.2, di/dt = 00 /μs b Body Diode Reverse Recovery Charge Q rr - 3.0 4.4 μc Forward Turn-On Time t on Intrinsic turn-on time is negligible (turn-on is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Pulse width 300 μs; duty cycle 2 %. c. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80 % V DS. S www.vishay.com Document Number: 9287 2 S-054-Rev. C, 30-May- THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?9000
TYPICL CHRCTERISTICS (25 C, unless otherwise noted) I D, Drain-to-Source Current () 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.7V 4.7V I D, Drain-to-Source Current () 00 0 T J = 50 C T J = 25 C 20µs PULSE WIDTH 0. T J = 25 C 0. 0 00 V DS, Drain-to-Source Voltage (V) Fig. - Typical Output Characteristics V DS= 50V 20µs PULSE WIDTH 0. 4.0 5.0 6.0 7.0 8.0 9.0 0.0 V GS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics I D, Drain-to-Source Current () 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.7V 4.7V 20µs PULSE WIDTH T J = 50 C 0 00 V DS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics r DS(on), Drain-to-Source On Resistance (Normalized) 3.0 2.5 2.0.5.0 0.5 I D = 9.2 V GS = 0V 0.0-60 -40-20 0 20 40 60 80 00 20 40 60 T J, Junction Temperature ( C) Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 9287 www.vishay.com S-054-Rev. C, 30-May- 3 THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?9000
C, Capacitance (pf) 2400 2000 600 200 800 400 iss oss rss V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd C oss = C ds Cgd I SD, Reverse Drain Current () 00 0 T J = 50 C T J = 25 C 0 0 00 000 V DS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage V GS = 0 V 0. 0.2 0.5 0.7.0.2 V SD,Source-to-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage V GS, Gate-to-Source Voltage (V) 20 6 2 8 4 I = D 9.2 V DS = 480V V DS = 300V V DS = 20V FOR TEST CIRCUIT SEE FIGURE 3 0 0 0 20 30 40 50 Q G, Total Gate Charge (nc) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage I D, Drain Current () 000 00 0 OPERTION IN THIS RE LIMITED BY R DS(on) 0us 00us ms 0ms TC = 25 C TJ = 50 C Single Pulse 0. 0 00 000 0000 V DS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating rea www.vishay.com Document Number: 9287 4 S-054-Rev. C, 30-May- THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?9000
0.0 V DS R D I D, Drain Current () 8.0 6.0 4.0 2.0 R g V GS 0 V Pulse width µs Duty factor 0. % D.U.T. - V DD Fig. 0a - Switching Time Test Circuit V DS 90 % 0.0 25 50 75 00 25 50 T C, Case Temperature ( C) Fig. 9 - Maximum Drain Current vs. Case Temperature 0 % V GS t d(on) t r t d(off) t f Fig. 0b - Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0.0 0.05 t 0.02 SINGLE PULSE t2 0.0 (THERML RESPONSE) Notes:. Duty factor D = t / t 2 0.0 2. Peak T J = P DM x Z thjc TC 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM Fig. - Maximum Effective Transient Thermal Impedance, Junction-to-Case 5 V V DS t p V DS L Driver R g 20 V t p D.U.T I S 0.0 Ω - V DD I S Fig. 2a - Unclamped Inductive Test Circuit Fig. 2b - Unclamped Inductive Waveforms Document Number: 9287 www.vishay.com S-054-Rev. C, 30-May- 5 THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?9000
E S, Single Pulse valanche Energy (mj) 600 500 400 300 200 00 TOP BOTTOM I D 4. 5.8 9.2 0 25 50 75 00 25 50 Starting T, Junction Temperature ( J C) Fig. 2c - Maximum valanche Energy vs. Drain Current Current regulator Same type as D.U.T. 0 V Q G 2 V 0.2 µf 50 kω 0.3 µf Q GS Q GD D.U.T. V - DS V G V GS Charge Fig. 3a - Basic Gate Charge Waveform 3 m Fig. 3b - Gate Charge Test Circuit I G I D Current sampling resistors www.vishay.com Document Number: 9287 6 S-054-Rev. C, 30-May- THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?9000
Peak Diode Recovery dv/dt Test Circuit D.U.T. - Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer - - R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. - device under test - V DD Driver gate drive P.W. Period D = P.W. Period V GS = 0 V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. V DS waveform Diode recovery dv/dt V DD Re-applied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 4 - For N-Channel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?9287. Document Number: 9287 www.vishay.com S-054-Rev. C, 30-May- 7 THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?9000
Package Information TO-263B (HIGH VOLTGE) (Datum ) 3 4 E 4 L 4 D H 2 C 3 C L2 B B 5 Detail c2 B Gauge plane 0 to 8 L3 L L4 Detail Rotated 90 CW scale 8: H B Seating plane 2 x b2 2 x e 2 x b 0.00 M M B Plating 5 b, b3 c ± 0.004 M B Base metal E D 4 (c) c 5 Lead tip (b, b2) Section B - B and C - C Scale: none E View - 4 MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX. 4.06 4.83 0.60 0.90 D 6.86-0.270-0.00 0.25 0.000 0.00 E 9.65 0.67 0.380 0.420 b 0.5 0.99 0.020 0.039 E 6.22-0.245 - b 0.5 0.89 0.020 0.035 e 2.54 BSC 0.00 BSC b2.4.78 0.045 0.070 H 4.6 5.88 0.575 0.625 b3.4.73 0.045 0.068 L.78 2.79 0.070 0.0 c 0.38 0.74 0.05 0.029 L -.65-0.066 c 0.38 0.58 0.05 0.023 L2 -.78-0.070 c2.4.65 0.045 0.065 L3 0.25 BSC 0.00 BSC D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.88 0.208 ECN: S-820-Rev., 5-Sep-08 DWG: 5970 Notes. Dimensioning and tolerancing per SME Y4.5M-994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.27 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum. 4. Thermal PD contour optional within dimension E, L, D and E. 5. Dimension b and c apply to base metal only. 6. Datum and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263B. Document Number: 9364 www.vishay.com Revision: 5-Sep-08
N826 RECOMMENDED MINIMUM PDS FOR D 2 PK: 3-Lead 0.420 (0.668) 0.635 (6.29) 0.355 (9.07) 0.45 (3.683) 0.35 (3.429) 0.200 (5.080) 0.050 (.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 -pr-05 www.vishay.com
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