INTEGRATED CIRCUITS 8-bit bidirectional binary counter 1996 Jan 5 IC15 Data Handbook
FEATURES Synchronous counting and loading Built-in look-ahead carry capability Count frequency 115MHz typ Supply current 95mA typ PIN CONFIGURATION 1 Q 2 Q1 3 Q2 4 24 23 P 22 P1 21 P2 DESCRIPTION The is a fully synchronous 8-stage Up/Down Counter featuring a preset capability for programmable operation, carry look-ahead for easy cascading and a input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock. Q3 Q4 GND Q5 Q6 Q7 5 6 7 8 9 1 2 19 18 17 16 15 P3 V CC P4 P5 P6 P7 TY TYPICAL f MAX SUPPLY CURRENT TYPICAL (TOTAL) 115MHz 95mA 11 12 14 13 SF834 ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE V CC = 5V ±1%, T amb = C to +7 C PKG DWG # 24-Pin Plastic Slim DIP (3mil) NN SOT222-1 24-Pin Plastic SOL ND SOT137-1 24-Pin Plastic SSOP type II NDB SOT34-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW P - P7 Parallel Data inputs 1./1. 2µA/.6mA Parallel Enable input (active Low) 1./1. 2µA/.6mA Up/Down count control input 1./1. 2µA/.6mA Count Enable Parallel input (active Low) 1./1. 2µA/.6mA Count Enable Trickle input (active Low) 1./1. 2µA/.6mA Clock input 1./1. 2µA/.6mA Terminal Count output (active Low) 5/33 1.mA/2mA Q - Q7 Flip-flop outputs 5/33 1.mA/2mA NOTE: One (1.) FAST Unit Load is defined as: 2µA in the High state and.6ma in the Low state. 1996 Jan 5 2 853 56 16186
LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 24 1 CTR DIV 256 M1[LOAD] M2[COUNT] M3[UP] 23 22 21 2 18 17 16 15 12 13 M4[DOWN] & G5 24 P P1 P2 P3 P4 P5 P6 P7 11 EN6 2, 3, 5, 6 +/C7 2, 4, 5, 6 1 12 13 11 Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 3 4 5 6 8 9 1 14 23 22 21 2 18 17 16 15 1, 7D [1] [2] [4] [8] [16] [32] [64] [128] 2 3 4 5 6 8 9 1 V CC =Pin 19 GND=Pin 7 SF835 3, 5, 6 CT=256 4, 5, 8 CT= 14 SF836 APPLICATION P P1 P2 P3 P4 P5 P6 P7 Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 P P1 P2 P3 P4 P5 P6 P7 Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 P P1 P2 P3 P4 P5 P6 P7 Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 P P1 P2 P3 P4 P5 P6 P7 Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 Least significant 8-bit counter Figure 1. Synchronous Multistage Counting Scheme Most significant 8-bit counter SF851 MODE SELECT FUNCTION TABLE INPUTS OUTPUTS P n Q n ORATING MODE X X X l l L (a) X X X l h H (a) Parallel load h l l h X Count Up (a) Count Up l l l h X Count Down (a) Count Down X h l h X q n (a) X X h h X q n H Hold (do nothing) H = High voltage level h = High voltage level one setup prior to the Low-to-High clock traition L = Low voltage level l = Low voltage level one setup time prior to the Low-to-High clock traition q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock traition X = Don t care = Low-to-High clock traition (a) = is Low when is Low and the counter is at Terminal Count. Terminal Count Up is with all Q n outputs High and Terminal Count Down is with all Qn outputs Low. 1996 Jan 5 3
LOGIC DIAGRAM P 23 2 Q P1 22 3 Q1 P2 21 4 Q2 P3 2 5 Q3 P4 18 6 Q4 P5 17 8 Q5 P6 16 9 Q6 P7 15 1 Q7 24 11 1 12 13 TOGGLE 14 Pn D Q Q V CC =Pin 19 GND=Pin 7 SF837 1996 Jan 5 4
ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage.5 to +7. V V IN Input voltage.5 to +7. V I IN Input current 3 to +5 ma V OUT Voltage applied to output in High output state.5 to V CC V I OUT Current applied to output in Low output state 4 ma T amb Operating free-air temperature range to +7 C T stg Storage temperature 65 to +15 C RECOMMENDED ORATING CONDITIONS SYMBOL PARAMETER LIMITS MIN NOM MAX V CC Supply voltage 4.5 5. 5.5 V V IH High-level input voltage 2. V V IL Low-level input voltage.8 V I IK Input clamp current 18 ma I OH High-level output current 1 ma I OL Low-level output current 2 ma T amb Operating free-air temperature range 7 C UNIT DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS NO TAG MIN LIMITS TYP NO TAG MAX UNIT V OH V OL High-level output voltage Low-level output voltage V CC = MIN, V IL = MAX ±1%V CC 2.5 V IH = MIN, I OH = MAX ±5%V CC 2.7 3.4 V CC = MIN, V IL = MAX ±1%V CC.3.5 V IH = MIN, I OL = MAX ±5%V CC.3.5 V IK Input clamp voltage V CC = MIN, I I = I IK.73 1.2 V I I Input current at maximum input voltage V CC = MAX, V I = 7.V 1 µa I IH High-level input current V CC = MAX, V I = 2.7V 2 µa I IL Low-level input current V CC = MAX, V I =.5V.6 ma I OS Short-circuit output current NO TAG V CC = MAX 6 15 ma I CC Supply current (total) I CCH V CC = MAX I CCL ====GND, Pn=4.5V, = ====GND, Pn=GND, = V V 93 12 ma 98 125 ma NOTES: 1. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type. 2. All typical values are at V CC = 5V, T amb = 25 C. 3. Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I OS tests should be performed last. 1996 Jan 5 5
AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS T amb = +25 C V CC = +5V C L = 5pF, R L = 5Ω LIMITS T amb = C to +7 C V CC = +5V ± 1% C L = 5pF, R L = 5Ω MIN TYP MAX MIN MAX f MAX Maximum clock frequency Waveform 1 1 115 85 MHz t pphl Propagation delay to Q n (Load, = Low) Propagation delay to Q n (Count, = High) Propagation delay to Propagation delay to Propagation delay to Waveform 1 3. 4. Waveform 1 3. 4.5 Waveform 1 Waveform 2 Waveform 3 4.5 5. 3.5 3. 4.5 4.5 6. 6. 7. 6. 7. 7. 8.5 8.5 9. 1. 9.5 9.5 9. 9. 9. 9.5 3. 4. 3. 4. 4. 5. 3. 3. 4. 4. 9. 9. 1. 1.5 1.5 1. 1. 1. 1. 1. UNIT AC SETUP REQUIREMENTS SYMBOL PARAMETER TEST CONDITIONS t s (H) t s (L) t h (H) t h (L) t s (H) t s (L) t h (H) t h (L) t s (H) t s (L) t h (H) t h (L) t s (H) t s (L) t h (H) t h (L) t w (H) t w (L) Setup time, High or Low P n to Hold time, High or Low P n to Setup time, High or Low to Hold time, High or Low to Setup time, High or Low or to Hold time, High or Low or to Setup time, High or Low to Hold time, High or Low to Pulse width High or Low Waveform 4 Waveform 4 Waveform 4 Waveform 4 Waveform 5 Waveform 5 Waveform 6 Waveform 6 Waveform 1 T amb = +25 C V CC = +5V C L = 5pF, R L = 5Ω LIMITS T amb = C to +7 C V CC = +5V ± 1% C L = 5pF, R L = 5Ω MIN TYP MIN MAX 3.5 3.5 1. 1. 5.5 6. 8. 8. 4. 4.5 2.5 2.5 1. 5.5 5. 4. 5. UNIT 1996 Jan 5 6
TIMING DIAGRAM P P1 P2 P3 P4 P5 P6 P7 AND Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 253 254 255 1 2 2 1 255 254 253 SEQUENCE LOAD COUNT UP INHIBIT COUNT DOWN SF838B 1996 Jan 5 7
AC WAVEFORMS For all waveforms, = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/f MAX t W (H) t W (L) Q n VM SF792 Waveform 2. Propagation Delay, Input to Terminal Count Output SF791A Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency Pn t s t h SF793 t s (L) t h = t s (H) t h = Waveform 3. Propagation Delay, Up/Down Count Control Input to Terminal Count Output SF844 Waveform 4. Parallel Data and Parallel Enable Setup and Hold Times t s (L) t h (L) t s (H) t h (H) t s (L) t h t s (H) th Q n COUNT NO CHANGE Q n COUNT DOWN COUNT UP Waveform 5. Count Enables Setup and Hold Times SF842 SF839 Waveform 6. Up/Down Count Control Setup and Hold Times 1996 Jan 5 8
TEST CIRCUIT AND WAVEFORMS PULSE GENERATOR V IN V CC D.U.T. V OUT NEGATIVE PULSE 9% 1% t THL ( t f ) t w t TLH ( t r ) 1% 9% AMP (V) V R T C L R L Test Circuit for Totem-Pole Outputs POSITIVE PULSE 1% 9% t TLH ( t r ) t w t THL ( t f ) 9% 1% AMP (V) V DEFINITIONS: R L = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family 74F Input Pulse Definition INPUT PULSE REQUIREMENTS amplitude rep. rate t w t TLH t THL 3.V 1.5V 1MHz 5 2.5 2.5 SF6 1996 Jan 5 9
DIP24: plastic dual in-line package; 24 leads (3 mil) SOT222-1 1996 Jan 5 1
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 1996 Jan 5 11
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT34-1 1996 Jan 5 12
NOTES 1996 Jan 5 13
8-bit bidirectional binary counter DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contai the design target or goal specificatio for product development. Specificatio may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contai Final Specificatio. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 349 Sunnyvale, California 9488 349 Telephone 8-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Date of release: July 1994 Document order number: 9397-75-5112