HCPL, HCPL, HCPL, HCPL, HCPL, HCPL High Speed- MBit/s Logic Gate Optocouplers Single Channel: HCPL, HCPL, HCPL Dual Channel: HCPL, HCPL, HCPL Features Compact SO8 package Very high speed- MBit/s Superior CMR Fan-out of 8 over - C to +85 C Logic gate output Strobable output (single channel devices) Wired OR-open collector U.L. recognized (File # E97) VDE approval pending Applications Ground loop elimination LSTTL to TTL, LSTTL or 5-volt CMOS Line receiver, data transmission Data multiplexing Package Dimensions SEATING PLANE Pin. (.). (.). (5.).8 (.). (.). (.).8 (.). (.5). (.8). (.8).5 (.7) TYP Lead Coplanarity :. (.) MAX NOTE All dimensions are in inches (millimeters).9 (.8). (.9). (5.9). (.5). (.) Switching power supplies Pulse transformer replacement Computer-peripheral interface Description August 5 The HCPLXX optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output (single channel devices). The devices are housed in a compact small-outline package. This output features an open collector, thereby permitting wired OR outputs. The HCPL, HCPL and HCPL output consists of bipolar transistors on a bipolar process while the HCPL, HCPL, and HCPL output consists of bipolar transistors on a CMOS process for reduced power consumption. The coupled parameters are guaranteed over the temperature range of - C to +85 C. A maximum input signal of 5 ma will provide a minimum output sink current of ma (fan out of 8). An internal noise shield provides superior common mode rejection. 5 Fairchild Semiconductor Corporation www.fairchildsemi.com
N/C + V F _ 8 V CC 7 V E V O N/C 5 GND Single-channel circuit drawing (HCPL, HCPL and HCPL) TRUTH TABLE (Positive Logic) Dual-channel circuit drawing (HCPL, HCPL and HCPL) Input Enable Output H H L L H H H L H L L H H* NC* L* L* NC* H* *Dual channel devices or single channel devices with pin 7 not connected. A. µf bypass capacitor must be connected between pins 8 and 5. (See note ) + V F V F 8 V CC 7 V V + 5 GND www.fairchildsemi.com
Absolute Maximum Ratings (No derating required up to 85 C) Recommended Operating Conditions Parameter Symbol Value Units Storage Temperature T STG - to +5 C Operating Temperature T OPR - to +85 C EMITTER Single Channel I F 5 ma DC/Average Forward Input Current (each channel) Dual Channel Enable Input Voltage Single Channel V E 5.5 V Not to exceed VCC by more than 5 mv Reverse Input Voltage (each channel) V R 5. V Power Dissipation Single Channel P I 5 mw Dual Channel DETECTOR Supply Voltage V CC 7. V ( minute max) Output Current (each channel) I O 5 ma Output Voltage (each channel) V O 7. V Collector Output Power Dissipation Single Channel P O 85 mw Dual Channel Parameter Symbol Min Max Units Input Current, Low Level I FL 5 µa Input Current, High Level I FH *. 5 ma Supply Voltage, Output V CC.5 5.5 V Enable Voltage, Low Level V EL.8 V Enable Voltage, High Level V EH. V CC V Operating Temperature T A - +85 C Fan Out (TTL load) N 8 TTL Loads Output Pull-up R L K Ω *. ma is a guard banded value which allows for at least % CTR degradation. Initial input current threshold value is 5. ma or less www.fairchildsemi.com
Electrical Characteristics (T A = - C to +85 C Unless otherwise specified.) Individual Component Characteristics Parameter Test Conditions Symbol Min Typ** Max Unit EMITTER (I F = ma) V F.8 V Input Forward Voltage T A =5 C.75 Input Reverse Breakdown Voltage (I R = µa) B VR 5. V Input Capacitance (V F =, f = MHz) C IN pf Input Diode Temperature Coefficient (I F = ma) VF/ TA mv/ C DETECTOR (V E =.5 V) Single Channel I CCH ma High Level Supply Current (I F = ma, V CC = 5.5 V) Dual Channel 5 Low Level Supply Current (V E =.5 V) Single Channel I CCL ma (I F = ma, V CC = 5.5V) Dual Channel Low Level Enable Current (V CC = 5.5 V, V E =.5 V) Single Channel I EL -. ma High Level Enable Current (V CC = 5.5 V, V E =. V) Single Channel I EH -. ma High Level Enable Voltage (V CC = 5.5 V, I F = ma) Single Channel V EH. V Low Level Enable Voltage (V CC = 5.5 V, I F = ma)(note ) Single Channel V EL.8 V Switching Characteristics (T A = - C to +85 C, V CC = 5 V, I F = 7.5 ma Unless otherwise specified.) AC Characteristics Test Conditions Device Symbol Min Typ Max Unit Propagation Delay Time to Output High Level (Note ) (T A =5 C) All T PLH 75 ns (R L = 5Ω, C L = 5 pf) (Fig. ) Propagation Delay Time (Note ) (T A =5 C) All T PHL 5 75 ns to Output Low Level (R L = 5Ω, C L = 5 pf) (Fig. ) Pulse Width Distortion (R L = 5Ω, C L = 5 pf) (Fig. ) All T PHL -T PLH 5 ns Output Rise Time (-9%) (R L = 5Ω, C L = 5 pf)(note 5) (Fig. ) All t r 5 ns Output Fall Time (9-%) (R L = 5Ω, C L = 5 pf)(note ) (Fig. ) All t f ns Enable Propagation Delay Time to Output High Level Enable Propagation Delay Time to Output Low Level Common Mode Transient Immunity (at Output High Level) Common Mode Transient Immunity (at Output Low Level) (I F = 7.5 ma, V EH =.5 V) (R L = 5Ω, C L = 5 pf) (Note 7) (Fig. ) (I F = 7.5 ma, V EH =.5 V) (R L = 5Ω, C L = 5 pf) (Note 8) (Fig. ) (R L = 5Ω) (T A =5 C) (I F = ma, V OH (Min.) =. V)(Note 9)(Fig., ) (R L = 5Ω) (T A =5 C) (I F = 7.5 ma, V OL (Max.) =.8 V)(Note )(Fig., ) HCPL HCPL HCPL HCPL HCPL HCPL V CM = V HCPL HCPL CM H V CM = 5 V HCPL 5 HCPL V CM =, V HCPL, HCPL 5, V CM = V HCPL HCPL CM H V CM = 5 V HCPL 5 HCPL V CM =, V HCPL, HCPL 5, t ELH ns t EHL ns V/µs V/µs www.fairchildsemi.com
Transfer Characteristics (T A = - C to +85 C Unless otherwise specified.) DC Characteristics Test Conditions Symbol Min Typ** Max Unit High Level Output Current (V CC = 5.5 V, V O = 5.5 V) (I F = 5 µa, V E =. V) (Note ) Low Level Output Voltage (V CC = 5.5 V, I F = 5 ma) (V E =. V, I OL = ma) (Note ) Input Threshold Current (V CC = 5.5 V, V O =. V, V E =. V, I OL = ma) Isolation Characteristics (T A = - C to +85 C Unless otherwise specified.) ** All typical values are at V CC = 5 V, T A = 5 C I OH µa V OL. V I FT 5 ma Characteristics Test Conditions Symbol Min Typ** Max Unit Input-Output Insulation Leakage Current Withstand Insulation Test Voltage (Relative humidity = 5%) (T A = 5 C, t = 5 s) (V I-O = VDC) (Note ) (R H < 5%, T A = 5 C) (Note ) ( t = min.) I I-O.* µa V ISO 75 V RMS Resistance (Input to Output) (V I-O = 5 V) (Note ) R I-O Ω Capacitance (Input to Output) (f = MHz) (Note ) C I-O. pf NOTES. The V CC supply to each optoisolator must be bypassed by a.µf capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V CC and GND pins of each device.. Enable Input - No pull up resistor required as the device has an internal pull up resistor.. t PLH - Propagation delay is measured from the.75 ma level on the HIGH to LOW transition of the input current pulse to the.5v level on the LOW to HIGH transition of the output voltage pulse.. t PHL - Propagation delay is measured from the.75 ma level on the LOW to HIGH transition of the input current pulse to the.5v level on the HIGH to LOW transition of the output voltage pulse. 5. t r - Rise time is measured from the 9% to the % levels on the LOW to HIGH transition of the output pulse.. t f - Fall time is measured from the % to the 9% levels on the HIGH to LOW transition of the output pulse. 7. t ELH - Enable input propagation delay is measured from the.5v level on the HIGH to LOW transition of the input voltage pulse to the.5v level on the LOW to HIGH transition of the output voltage pulse. 8. t EHL - Enable input propagation delay is measured from the.5v level on the LOW to HIGH transition of the input voltage pulse to the.5v level on the HIGH to LOW transition of the output voltage pulse. 9. CM H - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., V OUT >. V). Measured in volts per microsecond (V/µs).. CM L - The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state (i.e., V OUT <.8 V). Measured in volts per microsecond (V/µs).. Device considered a two-terminal device: Pins,, and shorted together, and Pins 5,,7 and 8 shorted together. 5 www.fairchildsemi.com
Typical Performance Curves (HCPL, HCPL and HCPL only) IF - FORWARD CURRENT (ma) ITH - INPUT THRESHOLD CURRENT (ma) Fig. Forward Current vs. Input Forward Voltage....9......5..7 5 T A = 7 C T A = 5 C T A = 85 C V F - FORWARD VOLTAGE (V) Fig. Input Threshold Current vs. Temperature V CC = 5V V O =.V R L = 5Ω R L = KΩ T A - TEMPERATURE ( C) T A = - C T A = C Vo - OUTPUT VOLTAGE (V) IOH - HIGH LEVEL OUTPUT CURRENT (µa) 5 Fig. Output Voltage vs. Forward Current R L = kω R L = 5Ω 5 I F - FORWARD INPUT CURRENT (ma) Fig. High Level Output Current vs. Temperature 8 T A - TEMPERATURE ( C) T A = 5 C V CC = 5V V O = V CC = 5.5V V E = V I F = 5 µa www.fairchildsemi.com
Typical Performance Curves (HCPL, and HCPL and HCPL only) VOL - LOW LEVEL OUTPUT VOLTAGE (V) TP - PROPAGATION DELAY (ns).8.7..5.... Fig. 5 Low Level Output Voltage vs. Temperature. 9 8 7 5 V = 5.5V CC V E = V I F = 5mA I O = ma I O =.ma I O =.8mA I O = 9.mA T A - TEMPERATURE ( C) Fig. 7 Propagation Delay vs. Temperature I F = 7.5mA t PLH R L = kω t PLH R L = 5Ω t PHL RL = 5Ω & kω T A - TEMPERATURE ( C) IOL - LOW LEVEL OUTPUT CURRENT (ma) TP - PROPAGATION DELAY (ns) Fig. Low Level Output Current vs. Temperature 55 5 5 5 5 V E = V V OL =.V I F = -5mA I F = 5mA T A - TEMPERATURE ( C) Fig. 8 Propagation Delay vs. Pulse Input Current 9 8 7 5 T A = 5 C t PLH R L = kω t PLH R L = 5Ω t PHL RL = 5Ω & kω 5 7 9 5 I F - PULSE INPUT CURRENT (ma) 7 www.fairchildsemi.com
Typical Performance Curves (HCPL, HCPL and HCPL only) Fig. 9 Typical Enable Propagation Delay vs. Temparature PWD - PULSE WIDTH DISTORTION (ns) te - ENABLE PROPAGATION DELAY (ns) 9 8 7 5 V EH = V V EL = V I F = 7.5mA t ELH R L = kω t ELH R L = 5Ω t EHL RL = 5Ω & kω T A - TEMPERATURE ( C) T A - TEMPERATURE ( C) Fig. Typical Pulse Width Distortion vs. Temperature 5 5 5 5 I F = 7.5mA R L = kω tf - FALL TIME (ns) R L = 5Ω T A - TEMPERATURE ( C) Fig. Typical Rise and Fall Time vs. Temperature 8 I F = 7.5mA t r R L = kω t r R L = 5Ω t f R L = 5Ω & kω 8 www.fairchildsemi.com
Typical Performance Curves (HCPL, HCPL and HCPL only) IF - FORWARD CURRENT (ma) IOH - HIGH LEVEL OUTPUT CURRENT (na) VOL - LOW LEVEL OUTPUT VOLTAGE (V) Fig. Input Forward Current vs. Forward Voltage....8 8 T A = 85 C T A = C T A = - C T A = C T A = 5 C.9......5..7 V F - FORWARD VOLTAGE (V) Fig. High Level Output Current vs. Ambient Temperature..5.... V O = V CC = 5.5V V E = V (Single Channel Only) I F = 5 µa T A - AMBIENT TEMPERATURE ( C) Fig. Low Level Output Voltage vs. Ambient Temperature V = 5.5V CC V E = V (Single Channel Only) I F = 5mA I O =.ma I O =.8mA I O = 9.mA I O = ma. T A - AMBIENT TEMPERATURE ( C) ITH - INPUT THRESHOLD CURRENT (ma) IOL - LOW LEVEL OUTPUT CURRENT (ma) Fig. Input Threshold Current vs. Ambient Temperature PWD - PULSE WIDTH DISTORTION (ns).5..5..5 V CC = 5.5V V O =.V R L = kω R L = 5Ω R L = kω. 5 5 5 T A - AMBIENT TEMPERATURE ( C) Fig. 5 Low Level Output Current vs. Ambient Temperature V = 5.5V CC V E = V (Single Channel Only) V OL =.V I F = 5-5mA 7 5 T A - AMBIENT TEMPERATURE ( C) Fig. 7 Pulse Width Distortion vs. Ambient Temperature I F = 7.5mA RL = kω RL = kω RL = 5Ω T A - AMBIENT TEMPERATURE ( C) 9 www.fairchildsemi.com
Typical Performance Curves (HCPL, HCPL and HCPL only) TP - PROPAGATION DELAY (ns) 8 I F = 7.5mA Fig. 8 Propagation Delay vs. Ambient Temperature t PLH RL = kω t PHL RL = 5Ω, kω, kω t PLH RL = kω t PLH RL = 5Ω T A - AMBIENT TEMPERATURE ( C) tr - RISE TIME (ns) 5 5 5 5 I F = 7.5mA Fig. 9 Rise and Fall Times vs. Ambient Temperature t r - RL = kω t f - RL = 5Ω, kω, kω t r - RL = kω t r - RL = 5Ω T A - AMBIENT TEMPERATURE ( C) 7 5 tf - FALL TIME (ns) www.fairchildsemi.com
Pulse Gen. t f = t r = 5 ns Z O = 5 Ω Input Monitor (I F) 7Ω +5V Pulse Gen. Z O = 5 Ω t f = t r = 5 ns Dual Channel I F V CC 8 V CC 8 Input.µf 7 R L Monitoring Bypass Node 7 Output (V O) C L R M GND 5 5 GND Test Circuit for HCPL, HCPL and HCPL Pulse Generator tr = 5ns Z O= 5Ω 7.5 ma V CC GND 8 7 5 Input Monitor (V E).µf bypass Test Circuit for HCPL, HCPL and HCPL R L C L +5V Output (V O) Input (V ) E tehl Output (V O) Input (I F) t PHL Output (V O) Output (V ) O Fig. Test Circuit and Waveforms for t PLH, t PHL, t r and t f. +5 V Fig. Test Circuit t EHL and t ELH. R L.µF Bypass Output V O Monitoring Node C L* telh tf. V.5 V.5 V 9% % t PLH tr I F = 7.5 ma I =.75 ma F.5 V www.fairchildsemi.com
VCM V 5V VO VO.5 V V FF A B I F Peak V CC GND V CM Pulse Gen Switching Pos. (A), I = F V O (Min) V O (Max) 8 7 5.µf bypass Test Circuit for HCPL, HCPL, and HCPL Switching Pos. (B), I = 7.5 ma F 5Ω +5V Output (V O) Fig. Test Circuit Common Mode Transient Immunity (HCPL, HCPL and HCPL) CM H CM L www.fairchildsemi.com
VCM V Peak.V VO VO.5 V I F V FF B A Switching Pos. (A), I = F V O (Min) Dual Channel V CC 8 V O (Max) Switching Pos. (B), I = 7.5 ma F Fig. Test Circuit Common Mode Transient Immunity (HCPL, HCPL and HCPL) 7 GND 5 V CM + Pulse Generator Z O = 5 Ω R L.µF Bypass Test Circuit for HCPL, HCPL and HCPL +.V Output V O Monitoring Node CM H CM L www.fairchildsemi.com
8-Pin Small Outline. (.). (.5).75 (.99).55 (.9).5 (.7) www.fairchildsemi.com
Ordering Information Option Order Entry Identifier Description No Suffix HCPL Shipped in tubes (5 units per tube) V HCPLV VDE88 (pending approval) R HCPLR Tape and Reel (5 units per reel) RV HCPLRV VDE88 (pending approval), Tape and Reel (5 units per reel) R HCPLR Tape and Reel (5 units per reel) RV HCPLRV VDE88 (pending approval), Tape and Reel (5 units per reel) Marking Information V 5 Definitions Fairchild logo Device number VDE mark (Note: Only appears on parts ordered with VDE option See order entry table) One digit year code, e.g., 5 Two digit work week ranging from to 5 Assembly package code X YY S 5 www.fairchildsemi.com
Carrier Tape Specifications Reflow Profile 8 8 C 8.5 ±. 8. ±.. MAX User Direction of Feed. ±.. MAX. ±. 8. ±.. ±.5.8 C/Sec Ramp up rate Sec Time (s) C Time above 8 C = 9 Sec 8 7 Ø.5 MIN.75 ±. 5.5 ±.5. ±. 5. ±. Ø.5 ±./- >5 C = Sec www.fairchildsemi.com
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