Freescale Semiconductor User Guide Document Number: TWRS8GWUG TWR-S8GW User Guide Overview The M9S8GW Tower MU Module (TWR-S8GW) is a low-cost evaluation, demonstration and development board. The TWR-S8GW can operate stand-alone or as the main control board in a Tower System with peripheral modules. The following list summarizes the features of the TWR-S8GW: Tower compatible microcontroller module M9S8GW in an 8 LQFP package M9S8JM based Open Source Debug (OSDM) circuit user controlled LEDs push buttons and two unpopulated headers for user input pin header for PNT based sensors Potentiometer ontents Overview..................................... Reference Documents........................... Hardware Features.............................. locking................................... System Power.............................. Debug Interface............................. RS Interface............................ Elevator onnections........................ Mechanical Form Factor..................... Jumper Settings................................ Input/Output Pin Usage Table..................... Appendix ASilk Screen.............................. 8 Appendix Schematic Drawings....................... 8 Freescale Semiconductor, Inc.,. All rights reserved.
Reference Documents M9S8QE8 based sine wave generator for AD test and energy meter simulation 9 pin V LD Glass GD97P Optical IR communication RS transceiver and x pin header Push button and jumper selection for tamper inputs Optional battery for powering up the board Expansion via Primary Elevator connector A block diagram for the TWR-S8GW is shown in the figure below. Tower Elevator Expansion onnectors.v SPI, I, AD, Timers, PWM, UARTs, IRQ, LD etc.v pin DM Header US Mini- A OSDM Debug,Power,SI.V.V DM UART S8GW Micro controller GPIO RESET L E D L E D L E D pin Header RS XVR U A R T A D A D LD pin PNT Header PNT IR footprint IR Interface QE8 based AD test circuit Freescale Device External onnectors Interf ace ircuits Power Reference Documents Figure. TWR-S8GW lock Diagram The documents listed below can be referenced for more information on the Freescale Tower system and the TWR-S8GW. Refer to http://www.freesale.com/tower for the latest revision of all Tower documentation. TWR-S8GW Schematics TWR-S8GW Quick Start Guide TWR-S8GW User Guide, Rev. Freescale Semiconductor
Hardware Features TWR-S8GW-KIT Lab Tutorial M9S8GW Reference Manual M9S8GW Data Sheet Hardware Features This section provides more details about the features and functionality of the TWR-S8GW.. locking Internal lock can be configured using the IS block for the microcontroller to run at up to MHz bus clock. Also there is a provision of.78 khz external crystal.. System Power The TWR-S8GW can be powered by the OSDM circuit via the Mini- US connector, J8, or from a source in an assembled Tower System. A standard US A male to Mini- male cable (provided) can be used to supply power from a US Host or powered US Hub. Optionally, an A to D adapter with a US A female receptacle (not provided) can be used as the power source. Power will automatically be sourced from the Elevator connector if power is available on both the Elevator and the OSDM. A jumper, J7, can be used to isolate the.v supply from the microcontroller. This connection can be used to measure the power usage of the M9S8GW microcontroller. Alternatively the board can be powered up from battery. The jumper J selects the source between V battery and US or elevator power.. Debug Interface An on-board, M9S8JM based Open Source DM (OSDM) circuit provides a debug interface to the M9S8GW and M9S8QE8. The OSDM circuit provides a US-to-debug interface that allows run-control and debugging of the M9S8GW target device. The US drivers required to communicate with the OSDM are provided in development tools such as Freescale odewarrior. This single US connection can also be used to power the TWR-S8GW stand-alone or in a fully assembled Tower System. A standard US A male to Mini- male cable (provided) can be used for debugging via the US connector, J8. Alternatively the header J can be used to program via P&E US multilink debugger. The jumpers J and J select between the devices M9S8GW and M9S8QE8 while programming using both OSDM and P&E US multilink.. RS Interface An RS transceiver on the TWR-S8GW connects to a standard x pin header (refer to Figure ). TWR-S8GW User Guide, Rev. Freescale Semiconductor
Jumper Settings Selection jumper pins on J allow UART signals to be routed to either the RS transceiver or the OSDM circuit. Refer to Table for more details. Table. RS X Pin Header onnections M9S8GW Signal PIN M9S8GW Signal No onnect No onnect TXD TS RXD RTS No onnect 7 8 No onnect GND 9.V. Elevator onnections The TWR-S8GW features two expansion card-edge connectors that interface to Elevator boards in a Tower system: the Primary and Secondary Elevator connectors. The Primary Elevator connector, comprised of sides A and, is utilized by the TWR-S8GW, while the Secondary Elevator connector makes connections to LD signals from TWR-S8GW and ground (GND).. Mechanical Form Factor The TWR-S8GW is designed for the Freescale Tower System and complies with the electrical and mechanical specification as described in Freescale Tower Electromechanical Specification. Jumper Settings There are several jumpers provided for isolation, configuration, and feature selection. Refer to the following table for details. The default installed jumper settings are shown in bold. Table. TWR-S8GW Jumper onnections Jumper Option Setting Description J Reset selection - onnect M9S8QE8 Reset to Debugger J pin DM header for M9S8QE8 and M9S8GW - onnect M9S8GW Reset to Debugger J KGD selection for Debugger - onnect M9S8QE8 KGD to Debugger J IRQ () header for JM - onnect M9S8GW KGD to Debugger TWR-S8GW User Guide, Rev. Freescale Semiconductor
Input/Output Pin Usage Table J pin DM header for JM J Supply Selection - attery power Input/Output Pin Usage Table - Regulated Output Voltage J7 MU power ON Supply.V to MU J9 KI7 switch header () OFF J Tamper Selection - Tamper J J J KI switch header () PNT Sensor Header() UART header pin - Tamper Isolate MU from Power (connect an ammeter to measure current) J - & - onnect TXD and RXD to OSDM debugger circuit - & - onnect TXD and RXD to RS J AD Input - Simulated sine wave from QE8 - GND J AD Input - Simulated sine wave from QE8 J7 J8 Primary Elevator Secondary Elevator Table. TWR-S8GW Jumper onnections Jumper Option Setting Description - GND Pin No M9S8GW Pins Application PTE/LD LD Glass pin PTE7/LD LD Glass pin PTF/LD LD Glass pin 7 PTF/LD7 LD Glass pin 8 PTF/LD8 LD Glass pin 9 PTF/LD9 LD Glass pin 7 PTF/LD LD Glass pin 8 PTF/LD LD Glass pin 9 PTF/MTIMLK/AD/LD LD Glass pin PTF7/FTMLK/AD/LD LD Glass pin TWR-S8GW User Guide, Rev. Freescale Semiconductor
Input/Output Pin Usage Table Pin No M9S8GW Pins Application PTG/MOSI/AD/LD LD Glass pin PTG/MISO/AD7/LD LD Glass pin PTG/SLK/AD8/LD LD Glass pin 7 PTG/SS/AD9/LD7 LD Glass pin 8 PTG/MPOUT/RXD/AD/LD8 LD Glass pin 9 PTG/MPOUT/TXD/AD/LD9 IR communication 7 PTG/PNT/MPP/AD/LD PNT Sensor Input/sine wave Input from QE8 8 PTG7/PNT/MPP/AD/LD PNT Sensor Input 9 PTH/PNT/MPP/AD/LD PNT Sensor Input/sine wave Input from QE8 PTH/RTLKOUT/AD/LD AD Potentiometer VDDA Analog Power VREFH Analog Reference Voltage High VSSA Analog Ground VREFL Analog Reference Voltage Low DADP sine wave Input from QE8 DADM sine wave Input from QE8 7 VREFO Reference Output Voltage from MU 8 DADP sine wave Input from QE8 9 DADM sine wave Input from QE8 VAT V battery for RT EXTAL RT EXTAL of.78 khz XTAL RT XTAL of.78 khz TAMPER Tamper from SW using J TAMPER Tamper from SW using J PTA/MOSI/PNTH/SL/AD PTA/MISO/PNTH/SDA/AD 7 PTA/SLK/FTMH/PNT/MPP User LED 8 PTA/SS/FTMH/PNT/MPP User LED 9 PTA/MTIMLK/RXD/PNT/MPP User LED PTA/FTMLK/TXD/EXTRIG/IRQ User Push utton PTA/MPOUT/LKOUT/KGD/MS KGD VDD Digital Power VSS Digital Ground PT/KIP/TXD/EXTAL MU EXTAL of.78 khz PT/KIP/RXD/MPP/XTAL MU XTAL of.78 khz RESET MU Reset TWR-S8GW User Guide, Rev. Freescale Semiconductor
Input/Output Pin Usage Table Pin No M9S8GW Pins Application 7 PT/KIP/MOSI/MISO/RXD UART Receiver 8 PT/KIP/MISO/MOSI/TXD UART Transmitter 9 PT/KIP/SLK/SL PT/KIP/SS/SDA PT/KIP/RXD/LD IR communication Receiver PT7/KIP7/TXD/LD IR communication Transmitter PT/MOSI/LD LD Glass pin PT/MISO/LD LD Glass pin PT/SLK/LD LD Glass pin PT/SS/LD LD Glass pin 7 PT/FTMH/RXD/LD LD Glass pin 8 PT/FTMH/TXD/LD7 LD Glass pin 9 PT/PNTH/RXD/LD8 LD Glass pin 7 PT7/PNTH/TXD/LD9 LD Glass pin 8 PTD/KIP/MOSI/LD PTD/KIP/MISO/LD PTD/KIP/SLK/LD PTD/KIP/SS/LD PTD/KIP/LD User Push utton PTD/KIP/LKOUT/LD User Push utton 7 PTD/KIP/LD User pin Header 8 PTD7/KIP7/LD7 User pin Header 9 PTE/LD8 LD Glass pin 9 7 PTE/LD9 LD Glass pin 7 PTE/LD LD Glass pin 7 PTE/LD LD Glass pin 7 PTE/LD LD Glass pin 7 PTE/LD LD Glass pin 7 VSS Digital GND 7 VLL LD voltage 77 VLL LD voltage 78 VLL LD voltage 79 VAP harge Pump capacitor 8 VAP harge Pump capacitor TWR-S8GW User Guide, Rev. Freescale Semiconductor 7
Silk Screen Appendix A Silk Screen Appendix Schematic Drawings TWR-S8GW User Guide, Rev. 8 Freescale Semiconductor
Table of ontents over Page M9S8GW MU OSDM & POWER PERIPHERALS ELEVATOR ONNETIONS Rev Description A Revisions Date Approved X Original Release Nov, 9 Sunaina Srivastava Release to Production Dec, 9 Sunaina Srivastava swapped PTG with PTG Sep, Sunaina Srivastava D D NOTES. Unless Otherwise Specified: All resistors are in ohms, %, /8 Watt All capacitors are in uf, %, V All voltages are D All polarized capacitors are aluminum electrolytic. Interrupted lines coded with the same letter or letter combinations are electrically connected.. Device type number is for reference only. The number varies with the manufacturer.. Special signal usage: _ Denotes - Active-Low Signal <> or [] Denotes - Vectored Signals. Interpret diagram in accordance with American National Standards Institute specifications, current revision, with the exception of logic block symbology. Elevator Primary & Secondary UART, SPI, I, LD, AD KI, IRQ etc VDD & GND M9S8GW KGD RESET VDD & GND GPIOs, AD, KI, LD, UART, PNT OSDM & POWER PERIPHERALS Microcontroller Solutions Group A A William annon Drive West Austin, TX 787-898 This document contains information proprietary to Freescale Semiconductor and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Freescale Semiconductor. IAP lassification: FP: FIUO: X PUI: Designer: Drawing Title: Sunaina Srivastava TWR-S8GW Drawn by: Page Title: Sunaina Srivastava over Page Approved: Size Document Number Rev Sunaina Srivastava SH- PDF: SPF- Thursday, September, Date: Sheet of
.UF D D (pg,) PTG/MOSI/AD/LD PTG/MOSI/AD/LD PT/KIP/SS/SDA PT/KIP/SS/SDA (pg) 9 PT/KIP/SLK/SL PT/KIP/SLK/SL (pg) PU_VDD PU_VDDA A_GND A A VREFO_J (pg) (pg,) PTE/LD (pg,) PTE/LD (pg,) PTE/LD (pg,) PTE/LD (pg,) PTE/LD9 (pg,) PTE/LD8 (pg,) PTD7/KIP7/LD7 (pg,) PTD/KIP/LD (pg,) PTD/KIP/LKOUT/LD (pg,) PTD/KIP/LD (pg,) PTD/KIP/SS/LD (pg) PTD/KIP/SLK/LD (pg) PTD/KIP/MISO/LD (pg) PTD/KIP/MOSI/LD (pg).uf.uf.uf U (pg,) PTE/LD (pg,) PTE7/LD (pg,) PTF/LD (pg,) PTF/LD7 (pg,) PTF/LD8 (pg,) PTF/LD9 (pg,) PTF/LD (pg,) PTF/LD XTAL (pg,) PTF/MTIMLK/AD/LD PTF/MTIMLK/AD/LD PT7/KIP7/TXD/LD PT7/KIP7/TXD/LD (pg) EXTAL (pg,) PTG/MISO/AD7/LD PTG/MISO/AD7/LD (pg,) PTG/SLK/AD8/LD 8 PTG/SLK/AD8/LD PT/KIP/MISO/MOSI/TXD PT/KIP/MISO/MOSI/TXD (pg,) 7 PT/KIP/RXD/MPP/XTAL (pg) (pg,) (pg) (pg,) (pg,) (pg,) PTG/MPOUT/TXD/AD/LD9 PTG/PNT/MPP/AD/LD PTG7/PNT/MPP/AD/LD PTH/PNT/MPP/AD/LD PTH/RTLKOUT/AD/LD PT/KIP/RXD/MPP/XTAL (pg) PT/KIP/TXD/EXTAL (pg) PTA/MPOUT/LKOUT/KGD/MS (pg,) Y.78KHz PT/KIP/TXD/EXTAL (pg) (pg,) (pg,) (pg,) (pg) DADP (pg) DADM (pg) DADP (pg) DADM EXTAL XTAL (pg) TAMPER (pg) TAMPER (pg) PTA/MOSI/PNTH/SL/AD (pg) PTA/MISO/PNTH/SDA/AD PTA/SLK/FTMH/PNT/MPP PTA/SS/FTMH/PNT/MPP PTA/MTIMLK/RXD/PNT/MPP PTA/FTMLK/TXD/EXTRIG/IRQ PTE/LD PTE7/LD PTF/LD PTF/LD7 PTF/LD8 PTF/LD9 PTF/LD PTF/LD PT7/PNTH/TXD/LD9 PT7/PNTH/TXD/LD9 (pg,) 9 PT/PNTH/RXD/LD8 PT/PNTH/RXD/LD8 (pg,) 8 PT/FTMH/TXD/LD7 PT/FTMH/TXD/LD7 (pg,) 7 PT/FTMH/RXD/LD PT/FTMH/RXD/LD (pg,) PT/SS/LD PT/SS/LD (pg,) PT/SLK/LD PT/SLK/LD (pg,) PT/MISO/LD PT/MISO/LD (pg,) PT/MOSI/LD PT/MOSI/LD (pg,) M9S8GW 8 9 PTG7/PNT/MPP/AD/LD PTH/PNT/MPP/AD/LD PTH/RTLKOUT/AD/LD PT/KIP/RXD/MPP/XTAL PT/KIP/TXD/EXTAL VSS VDD PTA/MPOUT/LKOUT/KGD/MS 9 PF M9S8GW.UF.UF X IAP lassification: FP: FIUO: PUI: Drawing Title: TWR-S8GW Page Title: M9S8GW MU Document Number Size Rev SH- PDF: SPF- Thursday, September, Date: Sheet of 7 8 9 7 8 9 7 8 9 VDDA VREFH VSSA VREFL DADP DADM VREFO DADP DADM VAT EXTAL XTAL TAMPER TAMPER PTA/MOSI/PNTH/SL/AD PTA/MISO/PNTH/SDA/AD PTA/SLK/FTMH/PNT/MPP PTA/SS/FTMH/PNT/MPP PTA/MTIMLK/RXD/PNT/MPP PTA/FTMLK/TXD/EXTRIG/IRQ VAP VAP VLL VLL VLL VSS PTE/LD PTE/LD PTE/LD PTE/LD PTE/LD9 PTE/LD8 PTD7/KIP7/LD7 PTD/KIP/LD PTD/KIP/LKOUT/LD PTD/KIP/LD PTD/KIP/SS/LD PTD/KIP/SLK/LD PTD/KIP/MISO/LD PTD/KIP/MOSI/LD 8 79 78 77 7 7 7 7 7 7 7 9 8 7 R PF Y R.78KHz M (pg,) PTF7/FTMLK/AD/LD PTF7/FTMLK/AD/LD PT/KIP/RXD/LD PT/KIP/RXD/LD (pg) PF (pg,) PTG/SS/AD9/LD7 7 R PTG/SS/AD9/LD7 PT/KIP/MOSI/MISO/RXD PT/KIP/MOSI/MISO/RXD (pg,) (pg,) PTG/MPOUT/RXD/AD/LD8 PTG/MPOUT/RXD/AD/LD8 RESET RESET (pg,) PF 7 PTG/MPOUT/TXD/AD/LD9 PTG/PNT/MPP/AD/LD 8.UF R M SH 8A T
VVSW R K VVU.UF U +VTRG_EN U VVSW VVTRG VVELE DDTAZA TRESET_IN +VTRG_Fault +V_Fault R.K U TRANSISTOR\JT +V_EN D ENA FLGA MSSPL ELE_PS_SENSE (pg) ELE_PS_SENSE EN FLG D D VV U IN OUTA 8 RNA RN RN RND k k k k GND OUT MI-YM + UF R7 R8 TRESET_OUT TRANSISTOR\JT UF 7. U RESET (pg,) VV VVU VVU U7 VVU R9 K PTS D D +V_EN T_TXD +VTRG_EN PT/MISO/ADP PTE/TxD T_TXD (pg) T_RXD PT/MOSI/ADP PTE/RxD T_RXD (pg) GRN TGND_EN VVSW 9 PT/SPSK/ADP PTE/TPMH U8 J.UF R 8 PT/SS/ADP PTE/TPMH 7 TGND_IN VV VV K.UF PT/KIP/ADP PTE/MISO DIR VA 8 PT/KIP/ADP PTE/MOSI V R PTE/SPSK TGND_OUT R R R PTE7/SS A K PT/SL.7K GND HDR X K PT/SDA PT PTF/TPMH SN7LVT TGND_IN.UF VVU PT/TxD PTF/TPMH TRESET_OUT TGND_OUT PT PTF/TPMH TGND_EN PT/RxD PTF/TPMH R 9 +V_Fault PTA/MPOUT/LKOUT/KGD/MS (pg,) R PTD/ADP8/AMP+ PTG/KIP +VTRG_Fault K TRESET_IN PTD/ADP9/AMP- PTG/KIP PTD/KIP/AMPO PTG/KIP (pg) QE_KGD PTG/KIP7 7 PTG/XTAL 8 IRQ/TPMLK PTG/EXTAL RESET KGD/MS R7 VV VV J VUS TLD HDR X TH VVU USDN 8 J VV USDP 9 HDR TH X M VV.UF UF R9 R R8 X K K K M9S8JMLD VVU RESET (pg,) PTA/MPOUT/LKOUT/KGD/MS (pg,) R R MHz K K 8PF 8PF OS_DM VVU (pg) QE_KGD (pg) QE_RESET (pg) QE_RESET PU_VDDA A_GND A A X IAP lassification: FP: FIUO: PUI: Drawing Title: TWR-S8GW Page Title: OSDM & POWER Document Number Size Rev SH- PDF: SPF- Thursday, September, Date: Sheet of E TRANSISTOR\JT R R STATUS LED LED-G LED-Y TPWR LED E R R.UF J SW HDR TH X OSDM Power Supply 7 + E R R D 7.UF + + E R R UF 8 9 7 7 9 VSSAD/VREFL VSS VSSOS VDDAD/VREFH VDD 7 J HDR X 8 PF NUP R-F T J VV R Vbat R VVTRG L U9 PU_VDD Mhz, ohms J7 HDR TH X IN VOUT OUT + 9 R VVU + 7 7UF HDR X TH.UF 8 OHM.UF UF PF OHM + L ADJ/GND L UF Mhz, ohms L Mhz, ohms LD7-. D S S + V OHM.UF UF V GRN S S Mhz, ohms OHM J8 MINI PWR_OR_DM US_MINI_ VUS D- D+ ID G
VV VV VV VV R R8 K R7 K K PTA/FTMLK/TXD/EXTRIG/IRQ PTD/KIP/LD PTD7/KIP7/LD7 (pg,) R9 R R D D (pg,) PT/MOSI/LD PTG/MPOUT/RXD/AD/LD8 (pg,) (pg,) PT/MISO/LD PTG/SS/AD9/LD7 (pg,) SH SH SH DS (pg,) PT/SLK/LD PTG/SLK/AD8/LD (pg,) VV VV VV (pg,) TAMPER (pg) (pg,) (pg,) PT/SS/LD PT/FTMH/RXD/LD PT/FTMH/TXD/LD7 PTG/MISO/AD7/LD (pg,) PTG/MOSI/AD/LD (pg,) PTF7/FTMLK/AD/LD (pg,) PTF/MTIMLK/AD/LD (pg,) PTF/LD (pg,) PTF/LD (pg,) PTF/LD9 (pg,) PTF/LD8 (pg,) PTF/LD7 (pg,) PTF/LD (pg,) PTE7/LD (pg,) R J AD_J PTG/PNT/MPP/AD/LD (pg) VV HDR TH X VV (pg) TPMH PTA/KIP/TPMH/ADP/AMP+ A A TPMH 9 PTA/KIP/TPMH/ADP/AMP- PT/KIP/RxD/ADP ADP ADP 8 R.K PTA/KIP/SDA/ADP PT/KIP/TxD/ADP ADP 7 PTA/KIP/SL/ADP PT/KIP/SPSK/ADP TPMH DADM (pg) (pg) QE_KGD PTA/AMPO/KGD/MS PT/KIP7/MOSI/ADP7 (pg) QE_RESET PTA/IRQ/TLK/RESET PT/TPMH/MISO 8 TPMH TPMH PT/TPMH PT/TPMH/SS 7 TPMH TPMH R.K J PT/TPMH PT/SDA/XTAL PT PT7/SL/EXTAL TPMH HDR TH X IAP lassification: FP: FIUO: X PUI: PT Drawing Title: - V- HDR X PNT.UF + (pg) T_RXD V+ - GND + V PTH/RTLKOUT/AD/LD (pg,) R.K 9 VV.UF 7 8 TPMH DADP (pg).uf.uf VV VV R7 VV R9.K.UF R8 R R TPMH DADM (pg) K K K VV VV PT/KIP/MISO/MOSI/TXD (pg,) PTH/PNT/MPP/AD/LD (pg,) PTG7/PNT/MPP/AD/LD (pg,) PTG/PNT/MPP/AD/LD (pg) PT/KIP/MOSI/MISO/RXD (pg,) PTA/SS/FTMH/PNT/MPP (pg,) PTA/SLK/FTMH/PNT/MPP (pg,) PTA/MTIMLK/RXD/PNT/MPP (pg,) IRQ, Tamper and KI (pg,) PT/PNTH/RXD/LD8 (pg,) PT7/PNTH/TXD/LD9 (pg,) PTE/LD8 (pg,) PTE/LD9 (pg,) PTE/LD (pg,) PTE/LD (pg,) PTE/LD (pg,) PTE/LD (pg,) PTE/LD 9 9 8 8 7 7 9 9 8 8 7 7 GD-97P GPIO/Timer LEDs LD and LD Enable AD channels ADP ADP ADP.UF R TPMH (pg) (pg) PT/KIP/RXD/LD PTG/PNT/MPP/AD/LD (pg) PT7/KIP7/TXD/LD Optical Interface.UF PTG/MPOUT/TXD/AD/LD9 (pg,) (pg) T_TXD RS TPMH QE based AD test circuit DADP (pg) PTH/PNT/MPP/AD/LD (pg,) Page Title: TWR-S8GW PERIPHERALS Size Document Number Rev SH- PDF: SPF- Thursday, September, Date: Sheet of 7 8 9 7 8 9 SW SW J9 D D7 D8 GRN GRN OR/RED (pg,) (pg,) HDR X TH PTS PTS SW PTS R K TAMPER (pg) R K J R K SW J HDR TH X PTS PTD/KIP/LD (pg,) PTD/KIP/LKOUT/LD HDR X TH (pg,) R R7 AD_J PTH/PNT/MPP/AD/LD (pg,) K (pg) SH U M9S8QE8 9 VSS VDD R8 K R9.UF R.K R R J J 7 8 9 HDR X.UF J HDR TH X.UF QTLPPD Q R R.UF.UF D9 QTLPIR R.K 9.UF.UF SH.UF 7 R K ROUT ROUT TIN TIN U IL RIN 8 RIN TOUT TOUT.UF 8.UF 9 7
VVELE J8 VVELE VV A VVELE J7 VVELE VV V_ V_ A VV GND_ GND_ A A VV V_ V_ VV.V_.V_7 A (pg) ELE_PS_SENSE A GND_ GND_ ELE_PS_SENSE.V_ A A.V_.V_7 GND_ GND_ (pg) ELE_PS_SENSE A R A ELE_PS_SENSE.V_ R7 GND_ GND_ A K 7 A7 GND_ GND_ K SPI_LK SL A 8 A8 GND_ GND_ SPI_S SDA D (pg) PTD/KIP/SLK/LD 7 A7 PT/KIP/SLK/SL (pg) 9 SPI_LK SL SPI_S GPIO9/OPEN A9 D 8 A8 PT/KIP/SS/SDA (pg) SPI_S SDA SPI_MOSI GPIO8/OPEN A (pg) PTD/KIP/SS/LD 9 SPI_S GPIO9/OPEN A9 SPI_MISO GPIO7/OPEN A (pg) PTD/KIP/MOSI/LD SPI_MOSI GPIO8/OPEN A (pg) PTD/KIP/MISO/LD SPI_MISO GPIO7/OPEN A ETH_OL ETH_RS A PTA/SLK/FTMH/PNT/MPP (pg,) ETH_RXER ETH_MD A ETH_OL ETH_RS A ETH_TXLK/ETH_REF_LK ETH_MDIO A ETH_RXER ETH_MD A ETH_TXEN ETH_RXLK A (pg) PTD/KIP/MISO/LD ETH_TXLK/ETH_REF_LK ETH_MDIO A ETH_TXER ETH_RXDV/ETH_RS_DV A (pg) PTD/KIP/MOSI/LD 7 A7 ETH_TXEN ETH_RXLK A ETH_TXD ETH_RXD PTD/KIP/SS/LD (pg) (pg) PTD/KIP/SLK/LD 8 A8 ETH_TXER ETH_RXDV/ETH_RS_DV A ETH_TXD ETH_RXD PTA/SS/FTMH/PNT/MPP (pg,) 7 A7 9 A9 ETH_TXD ETH_RXD ETH_TXD ETH_RXD 8 A8 A ETH_TXD ETH_RXD ETH_TXD ETH_RXD 9 A9 ETH_TXD ETH_RXD GPIO/OPEN SSI_MLK A A ETH_TXD ETH_RXD GPIO/OPEN SSI_LK A (pg,) PTA/MPOUT/LKOUT/KGD/MS GPIO/OPEN SSI_MLK A GPIO/OPEN SSI_FS A (pg,) PTA/FTMLK/TXD/EXTRIG/IRQ GPIO/OPEN SSI_LK A LKIN SSI_RXD A (pg,) PTA/SLK/FTMH/PNT/MPP GPIO/OPEN SSI_FS A LKOUT SSI_TXD A (pg,) PTA/SS/FTMH/PNT/MPP A LKIN SSI_RXD A GND_ GND_ (pg,) PTH/RTLKOUT/AD/LD 7 A7 SH8 LKOUT SSI_TXD A AN7 AN A (pg,) PTH/PNT/MPP/AD/LD 8 A8 SH7 GND_ GND_ AN AN 7 A7 PTH/RTLKOUT/AD/LD (pg,) 9 A9 AN7 AN AN AN 8 A8 AD_J (pg) A AN AN AN AN 9 A9 AD_J (pg) A AN AN GND_ GND_ A (pg,) PTG7/PNT/MPP/AD/LD A AN AN DA DA A A GND_ GND_ TMR TMR A VREFO_J (pg) A DA DA VV TMR TMR A VV TMR TMR GPIO/OPEN GPIO/OPEN A A A VV TMR TMR VV.V_.V_ 7 A7 GPIO/OPEN GPIO/OPEN A PWM7 PWM A 8 A8.V_.V_ PWM PWM 7 A7 9 A9 PWM7 PWM PWM PWM 8 A8 A PWM PWM PWM PWM 9 A9 A PWM PWM ANRX RXD A A PWM PWM ANTX TXD A PT/KIP/MOSI/MISO/RXD (pg,) A ANRX RXD AN RXD A PT/KIP/MISO/MOSI/TXD (pg,) (pg,) PTG/MPOUT/TXD/AD/LD9 A ANTX TXD SPI_MISO TXD A AN RXD R8 SPI_MOSI KGD A (pg) PTA/MISO/PNTH/SDA/AD A PT/KIP/RXD/MPP/XTAL (pg) (pg,) PTG/MPOUT/RXD/AD/LD8 A SPI_MISO TXD SPI_S ALLPST (pg) PTA/MOSI/PNTH/SL/AD (pg,) PTG/SS/AD9/LD7 7 SPI_MOSI KGD A SPI_S JTAG_EN A7 (pg,) PTA/SS/FTMH/PNT/MPP A R9 PT/KIP/TXD/EXTAL (pg) (pg,) PTG/SLK/AD8/LD 8 SPI_S ALLPST SPI_LK TRST_/DSLK A8 7 RESET (pg,) 9 A9 SPI_S JTAG_EN A7 GND_ GND_ (pg,) PTA/SLK/FTMH/PNT/MPP 8 PTA/MTIMLK/RXD/PNT/MPP (pg,) SPI_LK TRST_/DSLK A8 SL TLK/PSTLK A PTG/MISO/AD7/LD (pg,) 9 A9 A GND_ GND_ SDA TDI/DSI PTG/MOSI/AD/LD (pg,) (pg,) PTF7/FTMLK/AD/LD SL TLK/PSTLK A GPIO/OPEN TDO/DSO A PTF/MTIMLK/AD/LD (pg,) A (pg,) PTF/LD SDA TDI/DSI US_DP_PDOWN TMS/KPT_ A PTF/LD (pg,) (pg,) PTF/LD9 GPIO/OPEN TDO/DSO A US_DM_PDOWN US_DM A PTF/LD8 (pg,) US_DP_PDOWN TMS/KPT_ A IRQ_H US_DP A PTF/LD7 (pg,) US_DM_PDOWN US_DM A IRQ_G US_ID A PTF/LD (pg,) (pg,) PTD7/KIP7/LD7 7 IRQ_H US_DP A IRQ_F US_VUS A7 PTE7/LD (pg,) (pg,) PTD/KIP/LD 8 A8 IRQ_G US_ID A IRQ_E TMR7 (pg,) PTD/KIP/LKOUT/LD 7 9 A9 IRQ_F US_VUS A7 IRQ_D TMR (pg,) PTD/KIP/LD 8 A8 A IRQ_E TMR7 IRQ_ TMR 9 A9 A IRQ_D TMR IRQ_ TMR A IRQ_ TMR IRQ_A RSTIN_ A PTE/LD (pg,) A (pg,) PTE/LD IRQ_ TMR F_ALE/F_S_ RSTOUT_ A PTE/LD (pg,) (pg,) PTA/FTMLK/TXD/EXTRIG/IRQ (pg,) PTE/LD A IRQ_A RSTIN_ A F_S_ LKOUT PTE/LD (pg,) A F_ALE/F_S_ RSTOUT_ A GND_7 GND_ A (pg,) PTE/LD9 A F_S_ LKOUT F_AD F_AD PTE/LD8 (pg,) A (pg,) PTD7/KIP7/LD7 7 A7 GND_7 GND_ F_AD F_AD PTD/KIP/LD (pg,) A 8 A8 F_AD F_AD F_AD7 F_AD PTD/KIP/LKOUT/LD (pg,) 7 A7 9 A9 F_AD F_AD F_AD8 F_AD PTD/KIP/LD (pg,) 8 A8 7 A7 F_AD7 F_AD F_AD9 F_AD PTD/KIP/SS/LD (pg) 9 A9 7 A7 F_AD8 F_AD F_R/W_ F_AD9 PTD/KIP/SLK/LD (pg) 7 A7 7 A7 F_AD9 F_AD F_OE_ F_AD8 PTD/KIP/MISO/LD (pg) 7 A7 7 A7 F_R/W_ F_AD9 F_D7 F_AD7 PTD/KIP/MOSI/LD (pg) 7 A7 7 A7 F_OE_ F_AD8 F_D F_AD PT7/PNTH/TXD/LD9 (pg,) 7 A7 7 A7 F_D7 F_AD7 F_D F_AD PT/PNTH/RXD/LD8 (pg,) 7 A7 7 A7 F_D F_AD F_D F_AD PT/FTMH/TXD/LD7 (pg,) 7 A7 77 A77 F_D F_AD F_D F_AD PT/FTMH/RXD/LD (pg,) 7 A7 (pg,) PT/SS/LD 78 A78 F_D F_AD F_D F_AD PT/SLK/LD (pg,) 77 A77 (pg,) PT/MISO/LD 79 A79 F_D F_AD F_D F_AD PT/MOSI/LD (pg,) 78 A78 8 A8 F_D F_AD VV F_D F_AD 79 A79 8 A8 VV F_D F_AD GND_8 GND_9 8 A8 8 A8 VV F_D F_AD VV.V_.V_ 8 A8 GND_8 GND_9 8 A8.V_.V_ EDGE PI EXPRESS EDGE PI EXPRESS Secondary Elevator Primary Elevator A A X IAP lassification: FP: FIUO: PUI: Drawing Title: TWR-S8GW Page Title: ELEVATOR ONNETIONS Document Number Size Rev SH- PDF: SPF- Thursday, September, Date: Sheet of
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