SupIRBuck TM PD9752 IR3838MPbF HIGHLY INTEGRATED 0A SINGLE-INPUT OLTAGE, SYNCHRONOUS BUCK REGULATOR Features Greater than 96% Maximum Efficiency Single 6 Applicatin Single 5 Applicatin Wide Output ltage Range: 0.6 t 0.9*in Cntinuus 0A Lad Capability Prgrammable Switching Frequency up t.5mhz Internal Digital Sft-Start Enable Input with ltage Mnitring Capability Hiccup Mde Over Current Prtectin Internal LDO External Synchrnizatin Enhanced PreBias Start up External Reference fr Margining Purpses Input fr Tracking Applicatins Integrated MOSFET Drivers and Btstrap Dide Operating Junctin Temp: -40 C <Tj<25 C Thermal Shut Dwn Pwer Gd Output with tracking capability Over ltage Detectin Feature Pin Cmpatible with 6A and 4A ersins Small Size 5mmx6mm PQFN, 0.9 mm Height Lead-free, Halgen-free and RHS Cmpliant Applicatins Netcm and Telecm Applicatins Data Center Applicatins Distributed Pint f Lad Pwer Architectures Descriptin The IR3838 SupIRBuck TM is an easy-t-use, fully integrated and highly efficient DC/DC regulatr. The nbard PWM cntrller and MOSFETs make IR3838 a space-efficient slutin, prviding accurate pwer delivery fr lw utput vltage applicatins. IR3838 is a versatile regulatr which ffers prgrammability f switching frequency and current limit while perates in wide input and utput vltage range. The switching frequency is prgrammable frm 250kHz t.5mhz fr an ptimum slutin. It als features imprtant prtectin functins, such as Pre-Bias startup, hiccup current limit and thermal shutdwn t give required system level security in the event f fault cnditins. IR3838 ffers margining capability thrugh ref pin. During the margining peratin, PGd tracks ref via feedback t ensure crrect status f the utput vltage. The internal LDO enables the device t perate frm a single supply. This internal LDO can be bypassed when an external bias vltage is available. Fig.. Typical applicatin diagram
ABSOLUTE MAXIMUM RATINGS (ltages referenced t GND unless therwise specified) IR3838MPbF Pin, in -0.3 t 25 cc/ldo_ut...... -0.3 t 8 (Nte2) Bt..... -0.3 t 33 SW.. -0.3 t 25 (DC), -4 t 25 (AC, 00ns) Bt t SW..... -0.3 t cc+0.3 (Nte) OCset.. -0.3 t 30 Input / utput Pins...... -0.3 t cc+0.3 (Nte) PGnd t Gnd...... -0.3 t +0.3 Strage Temperature Range... -55 C T 50 C Junctin Temperature Range... -40 C T 50 C (Nte2) ESD Classificatin JEDEC(2K) Misture sensitivity level.... JEDEC Level 2 @260 C (Nte 5) Nte: Must nt exceed 8 Nte2: cc must nt exceed 7.5 fr Junctin Temperature between -0 C and -40 C Stresses beynd thse listed under Abslute Maximum Ratings may cause permanent damage t the device. These are stress ratings nly and functinal peratin f the device at these r any ther cnditins beynd thse indicated in the peratinal sectins f the specificatins are nt implied. Package Infrmatin 5mm x 6mm Pwer QFN (Tp iew) 3 Pin 2 SW PGnd θ θ JA = 35 C / W J-PCB = 2 C / W Bt 4 0 cc/ldo_ut Enable p 5 6 7 Gnd 9 8 in Sync 2 3 4 5 6 7 ORDERING INFORMATION Fb ref Cmp Gnd Rt OCset PGd PACKAGE DESIGNATOR PACKAGE DESCRIPTION PIN COUNT PARTS PER REEL M IR3838MTRPbF 7 4000 M IR3838MTRPbF 7 750 2
Blck Diagram Fig. 2. Simplified blck diagram f the IR3838 3
Pin Descriptin IR3838MPbF Pin Name Fb 2 ref 3 Cmp Descriptin Inverting input t the errr amplifier. This pin is cnnected directly t the utput f the regulatr via resistr divider t set the utput vltage and prvide feedback t the errr amplifier External reference vltage, can be used fr margining peratin. A 00nF capacitr shuld be cnnected between this pin and Gnd. Output f errr amplifier. An external resistr and capacitr netwrk is typically cnnected frm this pin t Fb t prvide lp cmpensatin 4 Gnd Signal grund fr internal reference and cntrl circuitry 5 Rt 6 OCset 7 8 9 0 PGd Sync in CC /LDO_ut PGnd Use an external resistr frm this pin t Gnd t set the switching frequency Current limit set pint. A resistr frm this pin t SW pin will set the current limit threshld Pwer Gd status pin. Output is pen drain. Cnnect a pull up resistr frm this pin t cc External Synchrnizatin, this pin is used t synchrnize the device s switching with an external clck. It is recmmended that the external Sync clck be set t 20% abve the free-running frequency. If nt used, this pin can be left flating. Input vltage fr Internal LDO. A.0µF capacitr shuld be cnnected between this pin and PGnd. If external supply is cnnected t cc/ldo_ut pin, this pin shuld be left flating. Input Bias ltage, utput f internal LDO. Place a minimum 2.2µF cap frm this pin t PGnd Pwer Grund. This pin serves as a separated grund fr the MOSFET drivers and shuld be cnnected t the system s pwer grund plane. 2 SW Switch nde. This pin is cnnected t the utput inductr 3 Pin Input vltage fr pwer stage 4 Bt 5 Enable Supply vltage fr high side driver, a 00nF capacitr shuld be cnnected between this pin and SW pin. Enable pin t turn n and ff the device, if this pin is cnnected t Pin pin thrugh a resistr divider, input vltage ULO can be implemented. 6 p Input t errr amplifier fr tracking purpses 7 Gnd Signal grund fr internal reference and cntrl circuitry 4
Recmmended Operating Cnditins IR3838MPbF Symbl Definitin Min Max Units Pin Input ltage fr pwer stage.5 6 in Input ltage fr internal LDO * 7.0 6 cc/ldo_ut Supply ltage * 4.5 6.5 Bt t SW Supply ltage 4.5 7.5 Output ltage 0.6 0.9*in I Output Current 0 0 A Fs Switching Frequency 225 650 khz T j Junctin Temperature -40 25 C * cc/ldo_ut can be cnnected t an external regulated supply ( 5). If s, the in input shuld be left uncnnected. Electrical Specificatins Unless therwise specified, these specificatin apply ver, 7.0< in =Pin<6, ref=0.6 in 0 C<T j < 25 C. Typical values are specified at T a = 25 C. PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT POWER STAGE Pwer Lsses P lss in =2, =.8, I =0A, Fs=600kHz, L=0.6uH, Nte4 Tp Switch R ds(n)_tp Bt - sw =5.0, I D =0A,Tj=25C 2 W 7. 26 Bttm Switch R ds(n)_bt cc =5.0, I D =0A 8.5 Btstrap Dide Frward ltage SW leakage Current Isw mω I(Bt)= 30mA 80 260 470 m SW=0, Enable=0 6 SW=0, Enable=high, p=0 4 SUPPLY CURRENT in Supply Current (Standby) I in(standby) Enable lw, N Switching, 400 µa in Supply Current (Dyn) I in(dyn) Enable high, Fs=500kHz, in=2 INTERNAL REGULATOR (LDO) µa 2 ma Output ltage Intcc in(min)=7.0, I=0-50mA, 4.7 5.2 5.7 Clad=2.2uF Intcc Drput Intcc_drp I=50mA, Clad=2.2uF 50 50 m Shrt Circuit Current Ishrt 70 ma INTERNAL DIGITAL SOFT START Sft Start Clck Frequency Clk(SS) Nte4 68 200 254 khz Sft Start Ramp Rate Ramp(SS) 0.2 m/us 5
Electrical Specificatins (cntinued) Unless therwise specified, these specificatin apply ver, 7.0< in =Pin<6, ref=0.6 in 0 C<T j < 25 C. Typical values are specified at T a = 25 C. IR3838MPbF PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT ERROR AMPLIFIER s_p fb-p, p=0.6, ref >2.0 - + Input Offset ltage s_ref fb-ref, ref=0.6, p>2.0 - % Input Bias Current IFb(E/A) - + A Input Bias Current Ip(E/A) - + A Sink Current Isink(E/A) 0.40 0.85.2 ma Surce Current Isurce(E/A) 8 0 3 ma Slew Rate SR Nte4 7 2 20 /s Gain-Bandwidth Prduct GBWP Nte4 20 30 40 MHz DC Gain Gain Nte4 00 0 20 db Maximum ltage max(e/a) 3.4 3.5 3.75 Minimum ltage min(e/a) 50 220 m Cmmn Mde ltage 0.2 OSCILLATOR Rt ltage 0.665 0.7 0.735 Frequency Range Rt=59K 225 250 275 F S Rt=28.7K 450 500 550 Rt=9.53K, Nte4 350 500 650 khz Ramp Amplitude ramp Nte4.8 p-p Ramp Offset Ramp(s) Nte4 0.6 Min Pulse Width Dmin(ctrl) Nte4 70 ns Max Duty Cycle Dmax Fs=250kHz 9 % Fixed Off Time Nte4 300 ns Sync Frequency Range 20% abve free running frequency 225 650 khz Sync Pulse Duratin 00 200 ns Sync Level Threshld Sync High 2 Sync Lw 0.6 REFERENCE OLTAGE Feedback ltage FB ref pin flating, p=cc 0.6 Accuracy 0 C<Tj<25 C -.0 +.0-40 C<Tj<25 C, Nte3-2.0 +2.0 ref margining vltage ref_marg 0.54.2 Sink Current Isink_ref ref=0.7 9 25 µa Surce Current Isurce_ref ref=0.5 9 25 µa Tracker Cmparatr Threshld Tracker Cmparatr Hysteresis Tracker(upper) ref pulled up externally.35.5.6 Tracker(lwer) ref pulled up externally.05.2.3 Tracker_Hys ref pulled up externally 220 300 420 m % 6
Electrical Specificatins (cntinued) IR3838MPbF PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT FAULT PROTECTION Fs=250kHz 0.4.8 3.2 OCSET Current I OCSET Fs=500kHz 2.5 24.4 27.3 µa Fs=500kHz 68 77 86 OC cmp Offset ltage OFFSET Nte4-6 0 +6 m SS ff time SS_Hiccup 4096 Cycles Thermal Shutdwn Nte4 40 Thermal Hysteresis Nte4 20 UNDER OLTAGE LOCKOUT CC -Start-Threshld CC _ULO_Start cc Rising Trip Level 4.06 4.26 4.46 CC -Stp-Threshld CC _ULO_Stp cc Falling Trip Level 3.76 3.96 4.6 Enable-Start-Threshld Enable_ULO_Start Supply ramping up.4.2.36 Enable-Stp-Threshld Enable_ULO_Stp Supply ramping dwn 0.75 0.85 0.95 Enable leakage current Ien Enable=3.3 PGOOD Pwer Gd upper Threshld PG(upper) Fb Rising, ref <.2 5 %ref Fb Rising, ref >.5 5 %p Upper Threshld Delay PG(upper)_Dly Fb Falling 256/Fs s Pwer Gd lwer Threshld PG(lwer) Fb Rising, ref <.2 85 %ref Fb Rising, ref >.5 85 %p Lwer Threshld Delay PG(lwer)_Dly Fb Rising 256/Fs s Sft Start Delay Time Tdelay(Delay) Nte4 0 ms PGd ltage Lw PG(vltage) I Pgd =-5mA 0.5 Tracker Cmparatr Upper PG(tracker_upper) p Rising, ref >.5 0.5 Threshld Tracker Cmparatr Lwer PG(tracker_lwer) p Falling, ref >.5 0.3 Threshld Tracker Cmparatr Delay Tdelay(tracker) p Rising, ref >.5 256/Fs s 0 C µa Nte3: Cld temperature perfrmance is guaranteed via crrelatin using statistical quality cntrl. Nt tested in prductin. Nte4: Guaranteed by design but nt tested in prductin Nte5: Upgrade t industrial/msl2 level applies frm date cdes 4 (marking explained n applicatin nte AN32 page 2). Prducts with prir date cde f 4 are qualified with MSL3 fr Cnsumer market. 7
Typical Efficiency and Pwer Lss Curves in=2, cc=5 (external), I=A-0A, F s =600kHz, Rm Temperature, N Air Flw The table belw shws the inductrs used fr each f the utput vltages in the efficiency measurement. [] L [µh] MFR P/N DCR [mω].2 0.5 itec 59PR9876N 0.29.8 0.72 Wurth Elek. 744 325 072.3 3.3.2 Wurth Elek. 744 325 20.8 5.0.2 Delta MPL055-R2 2.9 98 96 94 Efficiency (%) 92 90 88 86 84 82 80 2 3 4 5 6 7 8 9 0 Lad Current (A).2.8 3.3 5.0 Pwer Lss (W) 2.8 2.6 2.4 2.2 2.0.8.6.4.2.0 0.8 0.6 0.4 0.2 2 3 4 5 6 7 8 9 0 Lad Current (A).2.8 3.3 5.0 8
Typical Efficiency and Pwer Lss Curves in=2, cc/ldo_ut=5.2, I=A-0A, Fs=600kHz, Rm Temperature, N Air Flw The same inductrs as listed n the previus page have been used. Efficiency (%) 98 96 94 92 90 88 86 84 82 80 78 76 2 3 4 5 6 7 8 9 0 Lad Current (A).2.8 3.3 5.0 3.0 2.7 2.4 Pwer Lss (W) 2..8.5.2 0.9 0.6 0.3 2 3 4 5 6 7 8 9 0 Lad Current (A).2.8 3.3 5.0 9
Iin(Standby) Iin(Dyn) IR3838MPbF TYPICAL OPERATING CHARACTERISTICS (-40 C - 25 C), F s =500 khz 400 2.5 380 [µa] 360 340 320 300 280 260 240 220 200 [ma] 2.3 2..9.7 80 60-40 -20 0 20 40 60 80 00 20 40 Temp [ºC].5-40 -20 0 20 40 60 80 00 20 40 Temp [ºC] [khz] FREQUENCY 550 540 530 520 50 500 490 480 470 460 450-40 -20 0 20 40 60 80 00 20 40 Temp [ºC] [µa] IOCSET(500kHz) 27.5 26.5 25.5 24.5 23.5 22.5 2.5-40 -20 0 20 40 60 80 00 20 40 Temp [ºC] cc(ulo) Start 4.46 4.4 4.36 4.3 cc(ulo) Stp 4.6 4. 4.06 4.0 [] 4.26 [] 3.96 4.2 3.9 4.6 3.86 4. 3.8 4.06-40 -20 0 20 40 60 80 00 20 40 Temp [ºC] 3.76-40 -20 0 20 40 60 80 00 20 40 Temp [ºC] Enable(ULO) Start Enable(ULO) Stp.36 0.95.34 0.93 [].32.30.28.26.24.22.20.8 [] 0.9 0.89 0.87 0.85 0.83 0.8 0.79.6 0.77.4-40 -20 0 20 40 60 80 00 20 40 Temp [ºC] 0.75-40 -20 0 20 40 60 80 00 20 40 Temp [ºC] cc_ldo fb 5.7 0.62 5.6 5.5 0.608 5.4 5.3 0.604 [] 5.2 [] 0.600 5. 5.0 0.596 4.9 4.8 0.592 4.7-40 -20 0 20 40 60 80 00 20 40 0.588-40 -20 0 20 40 60 80 00 20 40 Temp [ºC] Temp [ºC] 0
Rdsn f MOSFETs Over Temperature at cc=5 24 22 20 Resistance [m-hm] 8 6 4 2 0 8 6-40 -20 0 20 40 60 80 00 20 40 Temperature [C] Sync-FET Ctrl-FET Rdsn f Sync-FET versus cc at different Temperatures 4 3 RDS_ON_Sync [mω] 2 0 9 8 7 6 5 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 cc [] -40C 0C 25C 65C 00C 25C
Circuit Descriptin THEORY OF OPERATION Intrductin The IR3838 uses a PWM vltage mde cntrl scheme with external cmpensatin t prvide gd nise immunity and maximum flexibility in selecting inductr values and capacitr types. The switching frequency is prgrammable frm 250kHz t.5mhz and prvides the capability f ptimizing the design in terms f size and perfrmance. IR3838 prvides precisely regulated utput vltage prgrammed via tw external resistrs frm 0.6 t 0.9*in. The IR3838 perates with an internal bias supply vltage f 5.2 (LDO) which is cnnected t the cc/ldo_ut pin. This allws peratin with single supply. The IC can als be perated with an external supply frm 4.5 t 6.5, allwing an extended perating input vltage (Pin) range frm.5 t 6. Fr using the internal supply, the in pin shuld be cnnected t Pin pin. If an external supply is used, it shuld be cnnected t cc/ldo_ut pin and the in pin shuld be left flating. IR3838MPbF Enable The Enable features anther level f flexibility fr start up. The Enable has precise threshld which is internally mnitred by Under-ltage Lckut (ULO) circuit. Therefre, the IR3838 will turn n nly when the vltage at the Enable pin exceeds this threshld, typically,.2. If the input t the Enable pin is derived frm the bus vltage by a suitably prgrammed resistive divider, it can be ensured that the IR3838 des nt turn n until the bus vltage reaches the desired level (Fig. 3). Only after the bus vltage reaches r exceeds this level will the vltage at Enable pin exceed its threshld, thus enabling the IR3838. Therefre, in additin t being a lgic input pin t enable the IR3838, the Enable feature, with its precise threshld, als allws the user t implement an Under-ltage Lckut fr the bus vltage (Pin). This is desirable particularly fr high utput vltage applicatins, where we might want the IR3838 t be disabled at least until Pin exceeds the desired utput vltage level. 0. 2 Pvin (2) cc (5.2) The device utilizes the n-resistance f the lw side MOSFET (sync FET) as current sense element. This methd enhances the cnverter s efficiency and reduces cst by eliminating the need fr external current sense resistr. Enable Threshld =.2 Enable SS IR3838 includes tw lw R ds(n) MOSFETs using IR s HEXFET technlgy. These are specifically designed fr high efficiency applicatins. Under-ltage Lckut and POR The under-vltage lckut circuit mnitrs the vltage f cc/ld pin and the Enable input. It assures that the MOSFET driver utputs remain in the ff state whenever either f these tw signals drp belw the set threshlds. Nrmal peratin resumes nce cc/ldo and Enable rise abve their threshlds. The POR (Pwer On Ready) signal is generated when all these signals reach the valid lgic level (see system blck diagram). When the POR is asserted the sft start sequence starts (see sft start sectin). Fig. 3. Nrmal Start up, device turns n when the bus vltage reaches 0.2 Figure 4a. shws the recmmended start-up sequence fr the nrmal (nn-tracking, nnsequencing) peratin f IR3838, when Enable is used as a lgic input. In this perating mde ref is left flating. Figure 4b. shws the recmmended startup sequence fr sequenced peratin f IR3838 with Enable used as lgic input. Fr this mde f peratin, ref is left flating. Figure 4c shws the recmmended startup sequence fr tracking peratin f IR3838 with Enable used as lgic input. Fr this mde f peratin, ref is cnnected t a vltage greater than.5. 2
ref This pin reflects the internal reference vltage which is used by the errr amplifier t set the utput vltage. In mst perating cnditins this pin is nly cnnected t an external bypass capacitr and it is left flating. In tracking mde this pin shuld be cnnected t an external vltage greater than.5 and less than 7. Fr margining applicatins, an external vltage surce is cnnected t ref pin and verrides the internal reference vltage. The external vltage surce shuld have a lw internal resistance (<00Ω) and be able t surce and sink mre than 25µA. Fig. 4a. Recmmended startup fr Nrmal peratin Pvin (2) cc (5.2) Enable >. 2 SS p Pre-Bias Startup IR3838 is able t start up int pre-charged utput, which prevents scillatin and disturbances f the utput vltage. The utput starts in asynchrnus fashin and keeps the synchrnus MOSFET (sync FET) ff until the first gate signal fr cntrl MOSFET (cntrl FET) is generated. Figure 5a shws a typical Pre-Bias cnditin at start up. The sync FET always starts with a narrw pulse width and gradually increases its duty cycle with a step f 25%, 50%, 75% and 00% until it reaches the steady state value. The number f these startup pulses fr the sync FET is internally prgrammed. Figure 5b shws a series f 32, 6, 8 startup pulses. Fig. 4b. Recmmended startup fr sequencing peratin (ratimetric r simultaneus) Fig. 5a. Pre-Bias startup Fig. 4c. Recmmended startup fr memry tracking peratin (tt-ddr) Fig. 5b. Pre-Bias startup pulses 3
Sft-Start The IR3838 has a digital internal sft-start t cntrl the utput vltage rise and t limit the current surge at the start-up. T ensure crrect start-up, the sft-start sequence initiates when the Enable and cc rise abve their ULO threshlds and generate the Pwer On Ready (POR) signal. The internal SS signal linearly rises with the rate f 0.2m / µs frm 0 t 2. Figure 6 shws the wavefrms during sft start (als refer t figure ). The nrmal start up time is fixed, and is equal t: T start.3-0.7 0.2m/ s 3ms - - - - - - - - - - - - - - () During the sft start the OCP is enabled t prtect the device fr any shrt circuit and ver current cnditin. Table. Switching Frequency and I OCSet vs. External Resistr (R t ) R t (kω) 47.5 35.7 28.7 23.7 20.5 7.8 5.8 4.3 2.7.5 0.7 9.76 9.3 F s (khz) 300 400 500 600 700 800 900 000 00 200 300 400 500 I cset (μa) 4.7 9.6 24.35 29.54 34. 39.3 44.3 48.95 55. 60.85 65.4 7.7 75.5 Over-Current Prtectin The ver current prtectin is perfrmed by sensing current thrugh the R DS(n) f the sync FET. This methd enhances the cnverter s efficiency and reduces cst by eliminating a current sense resistr. As shwn in figure 7, an external resistr (R OCSet ) is cnnected between OCSet pin and the switch nde (SW) which sets the current limit set pint. An internal current surce surces current (IOCSet ) ut f the OCSet pin. This current is a functin f Rt and hence, f the free-running switching frequency. Fig. 6. Theretical peratin wavefrms during sft-start (nn tracking / nn sequencing) Operating Frequency The switching frequency can be prgrammed between 250kHz 500kHz by cnnecting an external resistr frm R t pin t Gnd. Table tabulates the scillatr frequency versus R t. Shutdwn The IR3838 can be shutdwn by pulling the Enable pin belw its 0.85 threshld. This will tri-state bth, the high side driver as well as the lw side driver. I OCSet 700 ( μa)...(2) R (k) t Table. shws IOCSet at different switching frequencies. The internal current surce develps a vltage acrss R OCSet. When the sync FET is turned n, the inductr current flws thrugh Q2 and results in a vltage at OCSet which is given by: OCSet ( IOCSet ROCSet ) ( R ) I DS(n L )...(3) An ver current is detected if the OCSet pin ges belw grund. Hwever, t avid false tripping, due t the nise generated when the sync FET is turned n, the OCP cmparatr is enabled abut 200ns after sync-fet is turned n. 4
External Synchrnizatin The IR3838 incrprates an internal circuit which enables synchrnizatin f the internal scillatr (using rising edge) t an external clck. An external resistr frm Rt pin t Gnd is still required t set the free-running frequency clse t the Sync input frequency. This functin is imprtant t avid sub-harmnic scillatins due t beat frequency fr embedded systems when multiple POL (pint f lad) regulatrs are used. Applying the external signal t the Sync input changes the effective value f the ramp signal (ramp/sc). sc. 8 f Free _ Run f Sync......(5) Fig. 7. Cnnectin f ver current sensing resistr As mentined earlier, an ver current is detected if the OCSet pin ges belw grund. Hence, at the current limit threshld, OCset =0. Then, fr a current limit setting I Limit,R OCSet is calculated as fllws: R OCSet R DS( n) * I OCSet I Limit......(4) An ver-current detectin trips the OCP cmparatr, latches OCP signal and cycles the sft start functin in hiccup mde. The hiccup is perfrmed by making the internal SS signal equal t zer and cunting the number f switching cycles. The Sft Start pin is held lw until 4096 cycles have been cmpleted. The OCP signal resets and the cnverter recvers. After every sft start cycle, the cnverter stays in this mde until the verlad r shrt circuit is remved. An ptinal 0pF-22pF filter capacitr can be cnnected frm OCSet pin t PGnd. It is recmmended t use this capacitr fr very narrw duty cycle applicatins (pulse-width <50ns). Thermal Shutdwn Temperature sensing is prvided inside IR3838. The trip threshld is typically set t 40 C. When trip threshld is exceeded, thermal shutdwn turns ff bth MOSFETs and resets the internal sft start. Autmatic restart is initiated when the sensed temperature drps within the perating range. There is a 20 C hysteresis in the thermal shutdwn threshld. Equatin (5) shws that the effective amplitude f the ramp is reduced after the external Sync signal is applied. Mre difference between the frequency f the Sync and the free-running frequency results in mre change in the effective amplitude f the ramp signal. Therefre, since the ramp amplitude takes part in calculating the lp-gain and bandwidth f the regulatr, it is recmmended t nt use a Sync frequency which is much higher than the free-running frequency (r vice versa). In additin, the effective value f the ramp signal, given by equatin (5), shuld be used when the cmpensatr is designed fr the regulatr. The pulse width f the external clck, which is applied t the sync, shuld be greater than 00ns and its high level shuld be greater than 2, while its lwer level is less than 0.6. Fr mre infrmatin refer t the Oscillatr sectin in page- 6. If this pin is left flating, the IC will run with the free running frequency set by the resistr Rt. Output ltage Tracking and Sequencing The IR3838 can accmmdate user prgrammable tracking and/r sequencing ptins using p, ref, Enable, and Pwer Gd pins. In the blck diagram presented n page 3, the errr-amplifier (E/A) has been depicted with three psitive inputs. Ideally, the input with the lwer vltage is used fr regulating the utput vltage and the ther tw inputs are ignred. In practice the vltage f the ther tw inputs shuld be abut 200m greater than the lwvltage input s that their effects can cmpletely be ignred. Fr nrmal peratin, p is tied t cc (.5 < p < cc) and ref is left flating (with a bypass capacitr). 5
Therefre, in nrmal perating cnditin, after Enable ges high the SS ramps up the utput vltage until fb (vltage f feedback/fb pin) reaches abut 0.6. Then ref takes ver and the utput vltage is regulated (refer t Fig. ). Tracking-mde peratin is achieved by cnnecting ref t cc (.5<ref<cc). Then, while p=0, Enable is taken abve its threshld s that the sft start circuit generates internal SS signal. After the internal SS signal reaches the final value (refer t Fig. 4c) ramping up the p input will ramp up the utput vltage. In tracking mde, fb always fllws p which means ut is always prprtinal t p vltage (typical fr DDR/tt rail applicatins) In sequencing mde f peratin (simultaneus r ratimetric), ref is left flating and p is kept t grund level until after SS signal reaches the final value. Then p is ramped up and fb fllws p. When p>0.6 the errr-amplifier switches t ref and the utput vltage is regulated with ref. Tracking and sequencing peratins can be implemented t be simultaneus r ratimetric (refer t figures 9 and 0). Figure 8 shws typical circuit cnfiguratin fr sequencing peratin. With this pwer-up cnfiguratin, the vltage at the p pin f the slave reaches 0.6 befre the Fb pin f the master. If R E /R F =R C /R D, simultaneus startup is achieved. That is, the utput vltage f the slave fllws that f the master until the vltage at the p pin f the slave reaches 0.6. After the vltage at the p pin f the slave exceeds 0.6, the internal 0.6 reference f the slave dictates its utput vltage. In reality the regulatin gradually shifts frm p t internal ref. The circuit shwn in Fig. 8 can als be used fr simultaneus r ratimetric tracking peratin if ref f the slave is cnnected t cc. Table 2 n page 7 summarizes the required cnditins t achieve simultaneus / ratimetric tracking r sequencing peratins. Fig. 9 Typical wavefrms fr sequencing mde f peratin: (a) simultaneus, (b) ratimetric Fig. 8. Applicatin Circuit fr Simultaneus and ratimetric Sequencing Fig. 0 Typical wavefrms in tracking mde f peratin: (a) simultaneus, (b) ratimetric 6
Pwer Gd Output The IC cntinually mnitrs the utput vltage via Feedback (Fb pin). The feedback vltage is cmpared t a threshld. The threshld is set differently at different perating mdes and the results f the cmparisn sets the PGd signal. Figures, 2, and 3 shw the timing diagram f the PGd signal at different perating mdes. The PGd pin is pen drain and it needs t be externally pulled high. High state indicates that utput is in regulatin. Table 2. The required cnditins t achieve simultaneus / ratimetric tracking and sequencing peratins with the circuit cnfiguratin f Fig. 8 Operating Mde ref (slave) p Required Cnditin Nrmal (Nn-Sequencing, Nn-Tracking) 0.6 (Flat) >.5 - Simultaneus Sequencing 0.6 Ramp up frm 0 R A /R B > R E /R F =R C /R D Ratimetric Sequencing 0.6 Ramp up frm 0 R A /R B >R E /R F > R C /R D Simultaneus Tracking >.5 Ramp up frm 0 R E /R F =R C /R D Ratimetric Tracking >.5 Ramp up frm 0 R E /R F >R C /R D TIMING DIAGRAM OF PGOOD FUNCTIONS ref 0 0.6 2.0.3 Internal SS 0.7 SSOK 0.5*ref Fb 0 0.85*ref PGd 0 256/Fs 256/Fs Fig. Nn-sequence Startup and ref Margin (p =cc) 7
TIMING DIAGRAM OF PGOOD FUNCTIONS Fig.2 p Tracking (ref >.5, SS=H) Fig.3 p Sequence and ref Margin 8
Minimum n time Cnsideratins The minimum ON time is the shrtest amunt f time fr which the Cntrl FET may be reliably turned n, and this depends n the internal timing delays. Fr the IR3838, the typical minimum n-time is specified as 70 ns. Any design r applicatin using the IR3838 must ensure peratin with a pulse width that is higher than this minimum n-time and preferably higher than 50 ns. This is necessary fr the circuit t perate withut jitter and pulse-skipping, which can cause high inductr current ripple and high utput vltage ripple. Maximum Duty Rati Cnsideratins A fixed ff-time f 300 ns maximum is specified fr the IR3838. This prvides an upper limit n the perating duty rati at any given switching frequency. Thus, the higher the switching frequency, the lwer is the maximum duty rati at which the IR3838 can perate. T allw sme margin, the maximum perating duty rati in any applicatin using the IR3838 shuld still accmmdate abut 500 ns ff-time. Fig 4. shws a plt f the maximum duty rati v/s the switching frequency, with 300 ns ff-time. t n s s In any applicatin that uses the IR3838, the fllwing cnditin must be satisfied: t t D ut F in F n(min) n(min) t n ut F in in Fs t ut n(min) The minimum utput vltage is limited by the reference vltage and hence ut(min) = 0.6. Therefre, fr ut(min) = 0.6, s Max Duty Cycle (%) 95 90 85 80 75 70 65 60 55 50 250 450 650 850 050 250 450 650 Switching Frequency (khz) Fig. 4. Maximum duty cycle v/s switching frequency. in F in s F t s ut(min) n(min) 0.6 50 ns 40 /s Therefre, at the maximum recmmended input vltage 6 and minimum utput vltage, the cnverter shuld be designed at a switching frequency that des nt exceed 250 khz. Cnversely, fr peratin at the maximum recmmended perating frequency (.65 MHz) and minimum utput vltage (0.6), The input vltage (Pin) shuld nt exceed 2.42, therwise pulse skipping will happen. At lw utput vltages (belw ) specially at =0.6, it is recmmended t design the cmpensatr s that the bandwidth f the lp des nt exceed /0 f the switching frequency. 6 9
Applicatin Infrmatin Design Example: The fllwing example is a typical applicatin fr IR3838. The applicatin circuit is shwn n page 26. I in F s = 2 (32. max) = 8. =0 A Δ 2% fr ( = 600 khz 30% lad transient) Enabling the IR3838 As explained earlier, the precise threshld f the Enable lends itself well t implementatin f a ULO fr the Bus ltage as shwn in figure 5. R 8 ref.........(8) R 9 When an external resistr divider is cnnected t the utput as shwn in figure 6. Equatin (8) can be rewritten as: R 9 8 ref R ref.........(9) Fr the calculated values f R8 and R9 see feedback cmpensatin sectin. IR3624 IR3838 Fb OUT R8 R9 IR3838 Enable in R R 2 Fig. 6. Typical applicatin f the IR3838 fr prgramming the utput vltage Btstrap Capacitr Selectin Fig. 5. Using Enable pin fr ULO implementatin Fr a typical Enable threshld f EN =.2 in (min) R 2 Fr a in (min) =0.2, R =49.9K and R 2 =6.8k hm is a gd chice. Prgramming the frequency Fr F s = 600 khz, select R t = 23.7 kω, using Table. Output ltage Prgramming Output vltage is prgrammed by reference vltage and external vltage divider. The Fb pin is the inverting input f the errr amplifier, which is internally referenced t 0.6. The divider rati is set t prvide 0.6 at the Fb pin when the utput is at its desired value. The utput vltage is defined by using the fllwing equatin: R2 * R R R 2 in( EN min ) EN EN.2... (6)... (7) T drive the Cntrl FET, it is necessary t supply a gate vltage at least 4 greater than the vltage at the SW pin, which is cnnected t the surce f the Cntrl FET. This is achieved by using a btstrap cnfiguratin, which cmprises the internal btstrap dide and an external btstrap capacitr (C6). The peratin f the circuit is as fllws: When the sync FET is turned n, the capacitr nde cnnected t SW is pulled dwn t grund. The capacitr charges twards cc thrugh the internal btstrap dide (figure 7), which has a frward vltage drp D. The vltage c acrss the btstrap capacitr C6 is apprximately given as c cc D... (0) When the cntrl FET turns n in the next cycle, the capacitr nde cnnected t SW rises t the bus vltage in. Hwever, if the value f C6 is apprpriately chsen, the vltage c acrss C6 remains apprximately unchanged and the vltage at the Bt pin becmes: Bt in cc...() D 20
Inductr Selectin The inductr is selected based n utput pwer, perating frequency and efficiency requirements. A lw inductr value causes large ripple current, resulting in the smaller size, faster respnse t a lad transient but pr efficiency and high utput nise. Generally, the selectin f the inductr value can be reduced t the desired maximum ripple current in the inductr ( i). The ptimum pint is usually fund between 20% and 50% ripple f the utput current. Fr the buck cnverter, the inductr value fr the desired perating ripple current can be determined using the fllwing relatin: Fig. 7. Btstrap circuit t generate c vltage A btstrap capacitr f value 0.uF is suitable fr mst applicatins. Input Capacitr Selectin The ripple current generated during the n time f the cntrl FET shuld be prvided by the input capacitr. The RMS value f this ripple is expressed by: I RMS D I D( D ).........(2) in.........(3) Where: D is the Duty Cycle I RMS is the RMS value f the input capacitr current. I is the utput current. Fr I =0A and D = 0.5, the I RMS = 3.6A. Ceramic capacitrs are recmmended due t their peak current capabilities. They als feature lw ESR and ESL at higher frequency which enables better efficiency. Fr this applicatin, it is advisable t have 3x0uF, 6 ceramic capacitrs, ECJ-3YXC06K frm Panasnic. In additin t these, althugh nt mandatry, a x330uf, 25 SMD capacitr EE-FKE33P may als be used as a bulk capacitr and is recmmended if the input pwer supply is nt lcated clse t the cnverter. Where: i in L ; t D t Fs... (4) L in i* F in Maximum input vltage Output ltage Δi Inductr ripple current F Switching frequency s Δt Turn n time in D Duty cycle If Δi 42.5%(I ), then the utput inductr is calculated t be 0.6μH. Select MPL04-0R6 frm Delta (L=0.6μH) which prvides a cmpact, lw prfile inductr suitable fr this applicatin. Output Capacitr Selectin The vltage ripple and transient requirements determine the utput capacitrs type and values. The criteria is nrmally based n the value f the Effective Series Resistance (ESR). Hwever the actual capacitance value and the Equivalent Series Inductance (ESL) are ther cntributing cmpnents. These cmpnents can be described as ( ESR ) ( ESR ) ( ESL ) ( C ) I ( ESL ) L in * ESL L I * ESR L 8* C * Fs s ( C )... (5) 2
Where: = utput vltage ripple I L = Inductr ripple current Since the utput capacitr has a majr rle in the verall perfrmance f the cnverter and determines the result f transient respnse, selectin f the capacitr is critical. The IR3838 can perfrm well with all types f capacitrs. As a rule, the capacitr must have lw enugh ESR t meet utput ripple and lad transient requirements. The gal fr this design is t meet the vltage ripple requirement in the smallest pssible capacitr size. Therefre it is advisable t select ceramic capacitrs due t their lw ESR and ESL and small size. Five f Taiy Yuden s JMK22BJ476MG-T (47uF, 6.3, 3mΩ) capacitrs is a gd chice. It is als recmmended t use a 0.µF ceramic capacitr at the utput fr high frequency filtering. Feedback Cmpensatin The IR3838 is a vltage mde cntrller. The cntrl lp is a single vltage feedback path including errr amplifier and errr cmparatr. T achieve fast transient respnse and accurate utput regulatin, a cmpensatin circuit is necessary. The gal f the cmpensatin netwrk is t prvide a clsed-lp transfer functin with the highest 0 db crssing frequency and adequate phase margin (greater than 45 ). The utput LC filter intrduces a duble ple, 40dB/decade gain slpe abve its crner resnant frequency, and a ttal phase lag f 80 (see figure 8). The resnant frequency f the LC filter is expressed as fllws: Fig. 8. Gain and Phase f LC filter The IR3838 uses a vltage-type errr amplifier with high-gain (0dB) and high-bandwidth (30MHz). The utput f the amplifier is available fr DC gain cntrl and AC phase cmpensatin. The errr amplifier can be cmpensated either in type II r type III cmpensatin. Lcal feedback with Type II cmpensatin is shwn in Fig. 9. This methd requires that the utput capacitr shuld have enugh ESR t satisfy stability requirements. If the utput capacitr s ESR generates a zer at 5kHz t 50kHz, the zer generates acceptable phase margin and the Type II cmpensatr can be used. The ESR zer f the utput capacitr is expressed as fllws: F ESR 2 π*esr*c...(7) F LC 2 π L C.........(6) Figure 8 shws gain and phase f the LC filter. Since we already have 80 phase shift frm the utput filter alne, the system runs the risk f being unstable. Fig. 9. Type II cmpensatin netwrk and its asympttic gain plt 22
The transfer functin ( e / ut ) is given by: The additinal ple is given by: e ut Z H(s) Z f IN src 3 src 8 4 4...(8) FP C4 *C 2π* R3 * C C 4 POLE POLE............(24) The (s) indicates that the transfer functin varies as a functin f frequency. This cnfiguratin intrduces a gain and zer, expressed by: F H s z R R 3 8 2π* R *C 3.........(9) 4.........(20) First select the desired zer-crssver frequency (F ): F F ESR and F /5~/0 * F...(2) s The ple sets t ne half f the switching frequency which results in the capacitr C POLE : C POLE π*r 3*Fs C 4 π*r *F Fr a general slutin fr uncnditinal stability fr any type f utput capacitrs, and a wide range f ESR values, we shuld implement lcal feedback with a type III cmpensatin netwrk. The typically used cmpensatin netwrk fr vltage-mde cntrller is shwn in figure 20. 3 s......(25) Use the fllwing equatin t calculate R3: R 3 sc * F * F *F in ESR 2 LC * R 8.........(22) Where: in = Maximum Input ltage sc = Amplitude f the scillatr Ramp ltage F = Crssver Frequency F ESR = Zer Frequency f the Output Capacitr F LC = Resnant Frequency f the Output Filter R 8 = Feedback Resistr Z IN C7 R 0 Gain (db) OUT R 8 R 9 Fb REF R 3 C 3 E/A C 4 Z f e Cmp T cancel ne f the LC filter ples, place the zer befre the LC filter resnant frequency ple: H(s) db F 75%F z LC Fz 0. 75* 2π L *C............(23) Use equatins (20), (2) and (22) t calculate C4. One mre capacitr is smetimes added in parallel with C4 and R3. This intrduces ne mre ple which is mainly used t suppress the switching nise. F Z F Z 2 F P2 F P3 Frequency Fig.20. Type III Cmpensatin netwrk and its asympttic gain plt 23
Again, the transfer functin is given by: By replacing Z in and Z f accrding t figure 20, the transfer functin can be expressed as: The cmpensatin netwrk has three ples and tw zers and they are expressed as fllws: F F F F F P P2 P3 Z Z2 e ut 0 2π* R0*C7 C 2 4 *C π* R 3 3 *C3 2π* R3 C4 C 3 2π* R3 *C4 2π*C *( R R ) 2π*C * R..................(27) 7............(28)............(30) 8 Crss ver frequency is expressed as: F R3 *C7 * Z H( s ) Z ( sr3c 4 ) sc7 R8 R0 C *C 4 3 H( s ) sr 8(C4 C3 ) sr3 ( sr0c7 ) C4 C 3...(26) in sc 0 * 2π* L *C...(29)...(3) Based n the frequency f the zer generated by the utput capacitr and its ESR, relative t crssver frequency, the cmpensatin type can be different. Table 3 shws the cmpensatin types fr relative lcatins f the crssver frequency. f IN 7 8...........(32) Table 3. Different types f cmpensatrs Cmpensatr Typical Output F Type ESR vs F 0 Capacitr Type II F LC < F ESR < F 0 < F S /2 Electrlytic Type III F LC < F 0 < F ESR SP-Cap, Ceramic The higher the crssver frequency is, the ptentially faster the lad transient respnse will be. Hwever, the crssver frequency shuld be lw enugh t allw attenuatin f switching nise. Typically, the cntrl lp bandwidth r crssver frequency (F ) is selected such that The DC gain shuld be large enugh t prvide high DC-regulatin accuracy. The phase margin shuld be greater than 45 fr verall stability. Fr this design we have: in =2 =.8 sc =.8 ref =0.6 L =0.6µH C =5x47µF, ESR 3mΩ each It must be nted here that the value f the capacitance used in the cmpensatr design must be the small signal value. Fr instance, the small signal capacitance f the 47uF capacitr used in this design is 26uF at.8 DC bias and 600 khz frequency. It is this value that must be used fr all cmputatins related t the cmpensatin. The small signal value may be btained frm the manufacturer s datasheets, design tls r SPICE mdels. Alternatively, they may als be inferred frm measuring the pwer stage transfer functin f the cnverter and measuring the duble ple frequency F LC and using equatin (6) t cmpute the small signal C. These result t: F LC =8 khz F ESR =2.04 MHz F s /2=300 khz /5~/0 Fs F * 24
Select crssver frequency F 0 =00 khz Since F LC <F 0 <Fs/2<F ESR, Type III is selected t place the ple and zers. Detailed calculatin f cmpensatin Type III : Desired F Z2 F P2 Select: F F P3 0.5* F 300 khz Select:C 2.2nF Calculate R, C 2π* F * L *C * R3 C * Select: R 3.32k Calculate R R 0 F F 7 Phase 0. 5* F 2π*C * F R8 2π*C * F sin 7.63kHz sin sin 567.kHz sin Z -R Select: R 4.02 kω 8 3 C4 2π * F Z P3 7 7 3 7 0 3 3 3 8 P2 Z2 Margin 70 and C : in ; Z2 ; C4 * R C3 ;C3 2π* F * R s 0 8.82 khz and ;R 3. 34 kω 5. 44 nf, Select: 59 pf, Select: C R 0 sc 4, R and R : 9 28Ω, Select: R ; R 3.98kΩ, 8 3 C 5. 6 nf 3 4 50 pf 0 27 Ω Prgramming the Current-Limit The Current-Limit threshld can be set by cnnecting a resistr (R OCSet ) frm the SW pin t the OCSet pin. The resistr can be calculated by using equatin (4). This resistr (R OCSet )must be placed clse t the IC. The R DS(n) has a psitive temperature cefficient and it shuld be cnsidered fr the wrst case peratin (40% increase due t temperature has been cnsidered in belw). I SET RDS( n ) 8. 5 mω*.4. 9 mω I SET I ( LIM ) 0 A*.5 5 A (50% ver nminal utput current ) IOCSet 29.54 μa (at Fs 600 khz) R 6. 04 kω Select R 6.04 kω OCSet I L(critical) R R OCSet I DS(n) OCSet.........(33) OCSet The ptinal filter capacitr frm OCSet pin t PGnd has nt been used fr this design. Setting the Pwer Gd Threshld In this design IR3838 is used in nrmal (nntracking, nn-sequencing) mde, therefre the PGd threshlds are internally set at 85% and 5% f ref. At startup as sn as the internal sft start signal reaches 2 (Figure ), and assuming Fb vltage fllws ref, the PGd is asserted. As lng as the vltage at the Fb pin is between the threshlds (mentined abve), Enable is high, and n fault happens, the PGd remains high. The PGd is an pen drain utput. Hence, it is necessary t use a pull up resistr, R PG, frm PGd pin t cc. The value f the pull-up resistr must be chsen such as t limit the current flwing int the PGd pin t less than 5mA when the utput vltage is nt in regulatin. A typical value used is 0kΩ. ref Bypass Capacitr A bypass capacitr f abut 0.uF is required t be placed between ref and Gnd pins. This capacitr shuld be placed as clse as pssible t ref pin. ref R9 - ref * R ;R 2.0kΩ 8 9 Select: R 9 2 kω 25
Applicatin Diagram: Fig. 2. Applicatin circuit diagram fr a 2 t.8, 0 A Pint Of Lad Cnverter Suggested Bill f Materials fr the applicatin circuit: Part Reference Quantity alue Descriptin Manufacturer Part Number Cin 330uF SMD Elecrlytic, Fsize, 25, 20% Panasnic EE-FKE33P 3 0uF 206, 6, X7R, 20% Panasnic - ECG ECJ-3YXC06K L 0.6uH.5x0x4mm, 20%,.5mΩ Delta MPL04-0R6 C 5 47uF Ceramic, 6.3, 0805, X5R,20% Taiy Yuden JMK22BJ476MG-T R 49.9K Thick Film, 0603,/0 W,% Rhm MCR03EZPFX4992 R2 6.8K Thick Film, 0603,/0W,% Rhm MCR03EZPFX680 R t 23.7k Thick Film, 0603,/0W,% Rhm MCR03EZPFX2372 R OCSet 6.04k Thick Film, 0603,/0 W,% Rhm MCR03EZPFX604 R PG 0K Thick Film, 0603,/0W,% Rhm MCR03EZPFX002 Cref 0.uF 0603, 25, X7R, 0% Panasnic - ECG ECJ-BE04K R3 3.32k Thick Film, 0603,/0W,% Rhm MCR03EZPFX332 C3 50pF 50, 0603, NPO, 5% Panasnic- ECG ECJ-CH5J C4 5.6nF 0603, 50, X7R, 0% Panasnic - ECG ECJ-BH562K C6 0.uF 0603, 25, X7R, 0% Panasnic - ECG ECJ-BE04K R8 4.02K Thick Film, 0603,/0W,% Rhm MCR03EZPFX402 R9 2.0K Thick Film, 0603,/0W,% Rhm MCR03EZPFX200 R0 27 Thick Film, 0603,/0W,% Panasnic - ECG ERJ-3EKF270 C7 2200pF 0603, 50, X7R, 0% Panasnic - ECG ECJ-BH222K Ccc 2.2uF 0603, 0, X5R, 0% Panasnic - ECG ECJ-BA225K U IR3838 SupIRBuck, 0A, PQFN 5x6mm Internatinal Rectifier IR3838MPbF 26
TYPICAL OPERATING WAEFORMS in=2, cc/ldo=5.2, =.8, I=0-0A, Rm Temperature, N Air Flw Fig. 22: Start up at 0A Lad (Nte 6) Ch : ut Ch 2 :PGd Ch 3 :EN Ch 4 : in Fig. 23: Start up at 0A Lad (Nte 6) Ch : ut Ch 2 :PGd Ch 3 :cc Ch 4 : in Fig. 24: Start up with.62 Prebias, 0A Lad, Ch : ut Ch 2 : PGd Ch 3 : EN Fig. 25: Output ltage Ripple, 0A lad Ch : ut Fig. 26: Inductr nde at 0A lad Ch 3 :SW Fig. 27: Shrt (Hiccup) Recvery Ch : ut, Ch 2 :PGd, Ch 4 :Iut 27
TYPICAL OPERATING WAEFORMS in=2, cc/ldo=5.2, =.8, Rm Temperature, N Air Flw Fig. 28: Transient Respnse A-4A lad (0.5A/us) Ch : ut, Ch 4 :I Nte6: Enable (EN) is tied t in via a resistr divider and triggered when in is exceeding abve 0.2. 28
TYPICAL OPERATING WAEFORMS in=2, cc/ldo=5.2, =.8, I=0-0A, Rm Temperature, N Air Flw Fig.29: Bde Plt at 0A lad shws a bandwidth f 94kHz and phase margin f 5 degrees 29
Layut Cnsideratins The layut is very imprtant when designing high frequency switching cnverters. Layut will affect nise pickup and can cause a gd design t perfrm with less than expected results. Make all the cnnectins fr the pwer cmpnents in the tp layer with wide, cpper filled areas r plygns. In general, it is desirable t make prper use f pwer planes and plygns fr pwer distributin and heat dissipatin. The inductr, utput capacitrs and the IR3838 shuld be as clse t each ther as pssible. This helps t reduce the EMI radiated by the pwer traces due t the high switching currents thrugh them. Place the input capacitr directly at the Pin pin f IR3838. The feedback part f the system shuld be kept away frm the inductr and ther nise surces. The critical bypass cmpnents such as capacitrs fr in, cc, ref and p shuld be clse t their respective pins. It is imprtant t place the feedback cmpnents including feedback resistrs and cmpensatin cmpnents clse t Fb and Cmp pins. The cnnectin between the OCSet resistr and the SW pin shuld nt share any trace with the cnnectin between the btstrap capacitr and the SW pin. Instead, it is recmmended t use a Kelvin in cnnectin f the trace PGnd frm the OCSet resistr and the trace frm the btstrap in PGnd capacitr at the SW pin. Als, place the OCset resistr clse t the device. In a multilayer PCB use ne layer as AGnd ut a pwer grund plane and have a cntrl circuit grund (analg grund), t which all signals are referenced. The gal is t lcalize the high current AGnd path t a separate ut lp that des nt interfere with the mre sensitive analg cntrl functin. These tw grunds must be cnnected tgether n the PC bard layut at a single pint. It is recmmended t place all the cmpensatin parts ver the analg grund plane in tp layer. The Pwer QFN is a thermally enhanced package. Based n thermal perfrmance it is recmmended t use at least a 4-layers PCB. T effectively remve heat frm the device the expsed pad shuld be cnnected t the grund plane using vias. Figure 30 illustrates the implementatin f the layut guidelines utlined abve, n the IRDC3838 4 layer dembard. Enugh cpper & minimum length grund path between Input and Output AGnd Cmpensatin parts shuld be placed as clse as pssible t the Cmp pin. in PGnd All bypass caps shuld be placed as clse as pssible t their cnnecting pins. Resistrs Rt and R OCSet shuld be placed as clse as pssible t their pins. ut PGnd Fig. 30a. IRDC3838 Dembard layut cnsideratins Tp Layer 30
Bt cap uses separate trace frm R OCSet t be cnnected t SW nde PGnd Fig. 30b. IRDC3838 dembard layut cnsideratins Bttm Layer Analg Grund plane Pwer Grund plane Single pint cnnectin between AGND & PGND, shuld be clse t the SupIRBuck, kept away frm nise surces. Feedback trace shuld be kept away frm nise surces Fig. 30c. IRDC3838 dembard layut cnsideratins Mid Layer The trace which cnnects R OCSet t SW nde is separated frm the trace which cnnect Bt Cap t SW nde Fig. 30d. IRDC3838 dembard layut cnsideratins Mid Layer 2 3
PCB Metal and Cmpnents Placement Evaluatins have shwn that the best verall perfrmance is achieved using the substrate/pcb layut as shwn in fllwing figures. PQFN devices shuld be placed t an accuracy f 0.050mm n bth X and Y axes. Self-centering behavir is highly dependent n slders and prcesses, and experiments shuld be run t cnfirm the limits f self-centering n specific prcesses. Fr further infrmatin, please refer t SupIRBuck Multi-Chip Mdule (MCM) Pwer Quad Flat N-Lead (PQFN) Bard Munting Applicatin Nte. (AN-32) PCB metal pad sizing (all dimensins in mm) PCB metal pad spacing (all dimensins in mm) 32
Slder Resist It is recmmended that the lead lands are Nn Slder Mask Defined (NSMD). The slder resist shuld be pulled away frm the metal lead lands by a minimum f 0.025mm t ensure NSMD pads. The land pad shuld be Slder Mask Defined (SMD), with a minimum verlap f the slder resist nt the cpper f 0.05mm t accmmdate slder resist mis-alignment. Ensure that the slder resist in between the lead lands and the pad land is 0.5mm due t the high aspect rati f the slder resist strip separating the lead lands frm the pad land. 33
Stencil Design Stencils fr PQFN can be used with thicknesses f 0.00-0.250mm (0.004-0.00"). Stencils thinner than 0.00mm are unsuitable because they depsit insufficient slder paste t make gd slder jints with the grund pad; high reductins smetimes create similar prblems. Stencils in the range f 0.25mm-0.200mm (0.005-0.008"), with suitable reductins, give the best results. Evaluatins have shwn that the best verall perfrmance is achieved using the stencil design shwn in fllwing figure. This design is fr a stencil thickness f 0.27mm (0.005"). The reductin shuld be adjusted fr stencils f ther thicknesses. Stencil pad sizing (all dimensins in mm) Stencil pad spacing (all dimensins in mm) 34
DIM MILIMITERS INCHES MILIMITERS INCHES DIM MIN MAX MIN MAX MIN MAX MIN MAX A 0.800.000 0.035 0.0394 L 0.350 0.450 0.038 0.077 A 0.000 0.050 0.0000 0.0020 M 2.44 2.54 0.096 0.000 b 0.375 0.475 0.477 0.87 N 0.703 0.803 0.0277 0.036 b 0.250 0.350 0.0098 0.379 O 2.079 2.79 0.089 0.0858 c 0.203 REF. 0.008 REF. P 3.242 3.342 0.276 0.36 D 5.000 BASIC.969 BASIC Q.265.365 0.0498 0.0537 E 6.000 BASIC 2.362 BASIC R 2.644 2.744 0.04 0.080 e.033 BASIC 0.0407 BASIC S.500.600 0.059 0.0630 e 0.650 BASIC 0.0256 BASIC t, t2, t3 0.40 BASIC 0.06 BACIS e2 0.852 BASIC 0.0335 BASIC t4.53 BASIC 0.045 BASIC t5 0.727 BASIC 0.0286 BASIC IR WORLD HEADQUARTERS: 233 Kansas St., El Segund, Califrnia 90245, USA Tel: (30) 252-705 TAC Fax: (30) 252-7903 This prduct has been designed and qualified fr the Industrial market (Nte5) isit us at www.irf.cm fr sales cntact infrmatin Data and specificatins subject t change withut ntice. / 35