1.0 μm Process Family: XI10 The XI10 series is X-Fab's 1.0-micron Modular Silicon-On-Insulator Technology DESCRIPTION The XI10 series is X-FAB s 1.0 micron Modular Non-fully Depleted SOI CMOS Technology. Based on SOI wafers and the industrial standard single poly with fully dielectric isolated twin well three metal layers process, integrated with high voltage DMOS and hall plate, the platform is best suited for SOC applications in the automotive market, as well as high-voltage/ high-temperature applications in the communications, consumer and industrial market. Comprehensive design rules, precise SPICE models, analog and digital libraries, IPs and development kits support the process for major EDA vendors. KEY FEATURES OVERVIEW 6-inch wafer process Operating conditions: - Tj = -40 C to 125 C (without HTMET), - Tj = -40 C to 225 C (with HTMET) Non-fully depleted technology with: - 1000nm Box Oxide - 250nm Active Silicon - 25nm Gate Oxide Thickness Fully dielectric isolated twin well 3 metal layers with high temperature option upto 225 C operating temperature High-voltage MOS up to 90V APPLICATIONS Dielectric isolated mixed signal (multi-voltage systems) Intrinsic radiation hardness 42V Automotive Board Net Hall sensor High voltage & High Temperature QUALITY ASSURANCE X-FAB spends a lot of effort to improve the product quality and reliability and to provide comprehensive support to the customers. This is maintained by the direct and flexible customer interface, the reliable manufacturing process and complex test and evaluation conceptions, all of them guided by strict quality improvement procedures developed by X-FAB. This comprehensive, proprietary quality improvement system has been certified to fulfill the requirements of the ISO 9001, ISO TS 16949 and other standards. DELIVERABLES PCM tested wafers Optional engineering services: Multi Project Wafer (MPW) and Multi Layer Mask Service (MLM) Optional design services: feasibility studies, Place & Route, synthesis, custom block development DIGITAL LIBRARIES Low power high temperature digital core library I/O Library PRIMITIVE DEVICES BSIM3SOI v3.2 transistor models Fully isolated diodes Different types of passive devices Hall plate for magnetic field detection 1
XI10 PROCESS FLOW XI10 PROCESS MODULE Module Descriptions Masks No. CORE1 SOI core 13 SOI core for increased backside gate voltage 13 CIMP CIMP capacitor 1 HRES1 High resistive poly 0 HWCONT Handle wafer contact 1 HTMET High temperature metal 1 2
Active s XI10 MOS TRANSISTORS VT IDS [µa/µm] RDSon [kω.µm] BVDS VDS Max VGS N-ch H-type (6x1) nbth4, nbth5* 1.65 950 0.95 > 10 5.5 5.5 P-ch H-type (12x1) pbth4, pbth5* 1.20 750 2.4 > 10 5.5 5.5 N-ch A-type (6x1) nbta4, nbta5* 1.65 600 1.6 > 10 5.5 5.5 P-ch A-type (6x1) pbta4, pbta5* 1.2 430 4.2 > 10 5.5 5.5 * These devices are variants of the corresponding basic device with the handle wafer as the fifth terminal. Parameters of these devices are identical to the corresponding basic device (4 terminals). All devices are body tied, 1µm drift XI10 HIGH VOLTAGE TRANSISTORS Available with VT IDS [µa/µm] RON [kω.µm] BVDS VDS VGS N-ch HVMOS 3µm drift nhvt4d3, nhvt5d3* 1.70 520 3.6 > 55 40 5.5 N-ch HVMOS 6µm drift nhvt4d6, nhvt5d6* - - - - 60 5.5 N-ch HVMOS 10µm drift nhvt4d10, nhvt5d10* 1.70 500 8 > 110 90 5.5 P-ch HVMOS 3µm drift phvt4d3, phvt5d3* 1.10 750 5.5 > 55 30 5.5 P-ch HVMOS 6µm drift ** phvt4d6, phvt5d6* - - - - 40 5.5 P-ch HV MOS 10µm drift ** phvt4d10, phvt5d10* 1.10 750 16 > 55 40 5.5 * These devices are variants of the corresponding basic device with the handle wafer as the fifth terminal. Parameters of these devices are identical to the corresponding basic device (4 terminals).** These devices are not recommended for new designs. All devices are body tied. Passive s XI10 DIFFUSION RESISTORS RS[Ω/ ] Temp. Coeff. [10-3 /K] P-implanted silicon rpplus CORE1 70 1.51 65 1.51 N-implanted silicon rnplus 30 0.85 XI10 HIGH RESISTIVITY RESISTORS RS[Ω/ ] Max J/W [ma/µm] Temp. Coeff. [10-3 /K] Effective Width @1µm [µm] High resistive Poly rhires HRES1 1300 0.18-0.86 0.7 Mid. resistive Poly rmidres HRES1 160 0.4 0.48 0.9 XI10 LOW TC RESISTOR RS [Ω/ ] Max J/W [ma/µm] Temp. Coeff. [10-3 /K] Polysilicon rnpoly 40 0.45 1.35 3
Passive s XI10 POD CAPACITORS Area Cap [ff/µm²] BV Vt1-t2 Linear P-implanted cimp CIMP 1.05 > 20 5.5 XI10 PIP CAPACITORS Area Cap [ff/µm²] BV Vt1-t2 NWELL gate oxide cgoxnw 1.35 > 15 5.5 PWELL gate oxide cgoxpw 1.35 > 15 5.5 XI10 CAPACITOR SANDWICH Capacitance [ff] Perimeter Cap. [ff/µm] Vt1-t2 Poly1/M1/M2/M3 csand 0.15 0.08 90 HTMET 0.13 0.07 XI10 DIFFUSION DIODES BV Junc. cap. [ff/µm] Max VCC N diff. /P-well dn 12.5 0.25 5.5 P diff. /N-well dp 12.5 0.13 5.5 N diff. /P-drift dnpd 18 0.22 10 P diff. /N-drift dpnd 18 0.21 10 Standard Cells Libraries XI10 STD CELLS LIB Library feature Voltage range Application benefits D_CELLS Standard 5.0V Reduced parasitic effects, high voltage D_CELLS High Temperature 5.0V high voltage, high temperature (up to 225 C) XI10 I/O CELLS Library Feature Voltage Range Application benefits IO_CELLS_F Standard 5V cell height (core-limited):275µm IO_CELLS_F High Temperature 5V Standard and High temperature XI10 HALL PLATE Resistance [kω] Temp. Coeff. [10ˉ³/K] Normalized Sensitivity [V/AT] Hall Plate hall_nd 6.9 4 205 4
XI10 SUPPORTED EDA TOOLS Synthesis Frontend Design Environment Digital Simulation Timing, Power, Signal-Integrity Analysis Mixed-Signal- Simulators Analog Simulators Mixed Signal Environment Floorplanning, Place & Route Layout / Chip assembly drawing Verification & SignOff Tape Out / GDSII Note: Diagram shows overview of reference flow at X-FAB. Detailed information of suported EDA tools for major vendors like Cadence, Mentor and Synopsys can be found on X-FAB s online technical information center X-TIC. X-FAB'S IC DEVELOPMENT KIT "THEKIT" The X-FAB IC Development Kit is a complete solution for easy access to X-FAB technologies. TheKit is the best interface between standard CAE tools and X-FAB s processes and libraries. TheKit contain documentation, a set of software programs and utilities, digital and I/O libraries which contain full front-end and back-end information for the development of digital, analog and mixed signal circuits. Tutorials and application notes are included as well. CONTACT Marketing & Sales Headquarters X-FAB Semiconductor Foundries AG Haarbergstr. 67, 99097 Erfurt, Germany Tel.: 49-361-427 6160 Fax: 49-361-427 6161 Email: info@xfab.com Web: http://www.xfab.com Technology & Design Support hotline@xfab.com Silicon Foundry Services sifo@xfab.com DISCLAIMER Products sold by X-FAB are covered by the warranty provisions appearing in its Term of Sale. X-FAB makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. X-FAB reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with X-FAB for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as medical life-support or life-sustaining equipment are specifically not recommended without additional processing by X-FAB for each application. The information furnished by X-FAB is believed to be correct and accurate. However, X-FAB shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of X-FAB s rendering of technical or other services. 2017 by X-FAB Semiconductor Foundries AG. All rights reserved. 5