Applications Zero Voltage Switching SMPS Telecom and Server Power Supplies Uninterruptible Power Supplies Motor Control applications SMPS MOSFET Features and Benefits SuperFast body diode eliminates the need for external diodes in ZVS applications. Lower Gate charge results in simpler drive requirements. Enhanced dv/dt capabilities offer improved ruggedness. Higher Gate voltage threshold offers improved noise immunity. IRFPS35N50L HEXFET Power MOSFET V DSS R DS(on) typ. Trr typ. I D 500V 0.25Ω 70ns 34A Super-247 Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, @ V 34 I D @ T C = 0 C Continuous Drain Current, @ V 22 A I DM Pulsed Drain Current c 40 P D @T C = 25 C Power Dissipation 450 W Linear Derating Factor 3.6 W/ C Gate-to-Source Voltage ±30 V dv/dt Peak Diode Recovery dv/dt e 5 V/ns T J Operating Junction and -55 to 50 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torque, 6-32 or M3 screw.() N m (lbf in) Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 34 MOSFET symbol (Body Diode) A showing the I SM Pulsed Source Current 40 integral reverse (Body Diode)c p-n junction diode. PD- 94227A V SD Diode Forward Voltage.5 V T J = 25 C, I S = 34A, = 0V f t rr Reverse Recovery Time 70 250 ns T J = 25 C, I F = 34A 220 330 T J = 25 C, di/dt = 0A/µs f Q rr Reverse Recovery Charge 670 nc T J = 25 C, I S = 34A, = 0V f 500 2200 T J = 25 C, di/dt = 0A/µs f I RRM Reverse Recovery Current 8.5 A T J = 25 C t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) 8/26/04
Static @ T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 500 V = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.2 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 0.25 0.45 Ω (th) Gate Threshold Voltage 3.0 5.0 V I DSS Drain-to-Source Leakage Current 50 µa 2.0 ma I GSS Gate-to-Source Forward Leakage 0 na Gate-to-Source Reverse Leakage -0 R G Internal Gate Resistance. Ω Dynamic @ T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 8 S Q g Total Gate Charge 230 Q gs Gate-to-Source Charge 65 nc Q gd Gate-to-Drain ("Miller") Charge t d(on) Turn-On Delay Time 24 t r Rise Time 0 ns t d(off) Turn-Off Delay Time 42 t f Fall Time 42 C iss Input Capacitance 5580 C oss Output Capacitance 590 C rss Reverse Transfer Capacitance 58 pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 7290 = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 60 = 0V, V DS = 400V, ƒ =.0MHz C oss eff. Effective Output Capacitance 320 C oss eff. (ER) Effective Output Capacitance 220 (Energy Related) Avalanche Characteristics Symbol Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 560 mj I AR Avalanche Currentc 34 A E AR Repetitive Avalanche Energy c 45 mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc Junction-to-Caseh 0.28 R θcs Case-to-Sink, Flat, Greased Surface 0.24 C/W R θja Junction-to-Ambienth 40 Notes: Pulse width 400µs; duty cycle 2%. Repetitive rating; pulse width limited by max. junction temperature. (See Fig. ) Starting T J = 25 C, L = 0.97mH, R G =25Ω, I AS = 34A (See Figure 3) = V, I D = 20A f V DS =, I D = 250µA V DS = 500V, = 0V V DS = 400V, = 0V, T J = 25 C = 30V = -30V f = MHz, open drain Conditions V DS = 50V, I D = 20A I D = 34A V DS = 400V = V, See Fig. 7 & 5 f V DD = 250V I D = 34A R G =.2Ω = V, See Fig. a & b f = 0V V DS = 25V = 0V,V DS = 0V to 400V g C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. C oss eff.(er) is a fixed capacitance that stores the same energy as C oss while V DS is rising from 0 to 80% V DSS. ƒ I SD 34A, di/dt 765A/µs, V DD V (BR)DSS, T J 50 C. R θ is measured at T J approximately 90 C 2 www.irf.com
I D, Drain-to-Source Current (A) IRFPS35N50L 00 0 0. 0.0 0.00 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH Tj = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 50 C 0. 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 00 0 0. T J = 50 C T J = 25 C V DS= 50V 20µs PULSE WIDTH 0.0 4.0 5.0 6.0 7.0 8.0 9.0.0, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 I D = 34A 2.5 2.0.5.0 0.5 = V 0.0-60 -40-20 0 20 40 60 80 0 20 40 60 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance(pF) Energy (µj) IRFPS35N50L 0000 000 = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss 30 25 20 00 5 Coss 0 Crss 5 0 00 V DS, Drain-to-Source Voltage (V) 0 0 0 200 300 400 500 600 V DS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typ. Output Capacitance Stored Energy vs. V DS, Gate-to-Source Voltage (V) 20 6 2 8 4 I = D 34A V DS = 400V V DS = 250V V DS = 0V FOR TEST CIRCUIT SEE FIGURE 3 0 0 40 80 20 60 200 240 Q G, Total Gate Charge (nc) I SD, Reverse Drain Current (A) 00 0 T J = 50 C T J = 25 C = 0 V 0. 0.2 0.4 0.6 0.8.0.2.4.6 V SD,Source-to-Drain Voltage (V) Fig 7. Typical Gate Charge Vs. Fig 8. Typical Source-Drain Diode Gate-to-Source Voltage Forward Voltage 4 www.irf.com
35 V DS R D I D, Drain Current (A) 30 25 20 5 5 Fig a. Switching Time Test Circuit V DS 90% R G Pulse Width µs Duty Factor 0. % D.U.T. - V DD 0 25 50 75 0 25 50 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. 0.0 D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 0.00 2. Peak T J = P DM x Z thjc TC 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us 0us ms TC = 25 C TJ = 50 C ms Single Pulse 0 00 000 V DS, Drain-to-Source Voltage (V) Fig 2. Maximum Safe Operating Area E AS, Single Pulse Avalanche Energy (mj) 200 00 800 600 400 200 TOP BOTTOM 0 25 50 75 0 25 50 Starting T, Junction Temperature ( J C) Fig 3. Maximum Avalanche Energy Vs. Drain Current I D 5A 22A 34A 5V V (BR)DSS V DS L DRIVER tp R G D.U.T I AS - V DD A 20V tp 0.0Ω Fig 4a. Unclamped Inductive Test Circuit I AS Fig 4b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF D.U.T. V - DS Q GS Q GD V G 3mA I G I D Current Sampling Resistors Charge Fig 5a. Gate Charge Test Circuit Fig 5b. Basic Gate Charge Waveform 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * = 5V for Logic Level Devices Fig 4. For N-Channel HEXFET Power MOSFETs www.irf.com 7
Super-247 (TO-274AA) Package Outline 2X R 3.00 [.8] 2.00 [.079] 6. [.632] 5. [.595] A 5.50 [.26] 4.50 [.78] 0.3 [.005] 2.5 [.084].45 [.058] 0.25 [.0] B A 3.90 [.547] 3.30 [.524].30 [.05] 0.70 [.028] 20.80 [.88] 9.80 [.780] 4 6. [.633] 5.50 [.6] 4 C 2 3 B 4.80 [.582] 3.80 [.544] 4.25 [.67] 3.85 [.52] Ø.60 [.063] MAX. E E 5.45 [.25] 2X.60 [.062] 3X.45 [.058] 0.25 [.0] B A.30 [.05] 3X. [.044] 2.35 [.092].65 [.065] SECTION E-E NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M-994. 2. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES] 3. CONTROLLING DIMENSION: MILLIMETER 4. OUTLINE CONFORMS TO JEDEC OUTLINE TO-274AA Super-247 (TO-274AA)Part Marking Information EXAMPLE: THIS IS AN IRFPS37N50A WITH ASSEMBLY LOT CODE A8B9 INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFPS37N50A A8B9 0020 LEAD AS S IGNMENT S MOS F ET IGBT - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN - GATE 2 - COL L ECT OR 3 - EMITTER 4 - COL L ECT OR PART NUMBER DATE CODE (YYWW) YY = YEAR WW = WEEK Super TO-247 package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. TOP IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information.08/04 8 www.irf.com