DSHEE ISL12029, ISL12029 Real ime lock/alendar with I2 Bus and EEPROM NO REOMMENDED FOR NEW DESIGNS NO REOMMENDED REPLEMEN contact our echnical Support enter at 1-888-INERSIL or www.intersil.com/tsc FN6206 Rev 1.00 he ISL12029 device is a low power real time clock with clock/calendar, power-fail indicator, clock output and crystal compensation, two periodic or polled alarms (open drain output), intelligent battery backup switching, PU Supervisor, integrated 512x8-bit EEPROM configured in 16 bytes per page. he oscillator uses an external, low-cost 32.768kHz crystal. he real-time clock tracks time with separate registers for hours, minutes and seconds. he device has calendar registers for date, month, year and day of the week. he calendar is accurate through 2099, with automatic leap year correction. he ISL12029 and ISL12029 Power ontrol Settings are different. he ISL12029 uses the Legacy Mode Setting, and the ISL12029 uses the Standard Mode Setting. pplications that have V B > V DD will require only the ISL12029. Please refer to Power ontrol Operation on page 14 for more details. lso, please refer to I 2 ommunications During Battery Backup on page 24 for important details. Pinout X1 X2 N N N RESE GND ISL12029, ISL12029 (14 LD SSOP, SOI) OP VIEW 1 2 3 4 5 6 7 14 13 12 11 10 9 8 V DD V B N = No internal connection IRQ/F OU N N SL SD Features Real ime lock/alendar - racks ime in Hours, Minutes and Seconds - Day of the Week, Day, Month and Year - 3 Selectable Frequency Outputs wo Non-Volatile larms - Settable on the Second, Minute, Hour, Day of the Week, Day or Month - Repeat Mode (periodic interrupts) utomatic Backup to Battery or Superap - Power Failure Detection - 800n Battery Supply urrent On-hip Oscillator ompensation: - Internal Feedback Resistor and ompensation apacitors - 64 Position Digitally ontrolled rim apacitor - 6 Digital Frequency djustment Settings to ±30ppm 512x8 Bits of EEPROM - 16-Byte Page Write Mode (32 total pages) - 8 Modes of BlockLock Protection - Single Byte Write apability - Data Retention: 50 years - Endurance: >2,000,000 ycles Per Byte PU Supervisor Functions - Power-On Reset, Low Voltage Sense - Watchdog imer (0.25s, 0.75s, 1.5s) I 2 Interface - 400kHz Data ransfer Rate 14 Ld SOI and 14 Ld SSOP Packages Pb-Free (RoHS ompliant) pplications Utility Meters HV Equipment udio/video omponents Modems Network Routers, Hubs, Switches, Bridges ellular Infrastructure Equipment Fixed Broadband Wireless Equipment Pagers/PD POS Equipment est Meters/Fixtures Office utomation (opiers, Fax) Home ppliances omputer Products Other Industrial/Medical/utomotivePR FN6206 Rev 1.00 Page 1 of 29
Block Diagram OS OMPENSION X1 32.768kHZ X2 IRQ/F OU SELE OSILLOR FREQUENY DIVIDER 1Hz IMER LENDR LOGI IME EEPING REGISERS (SRM) BERY SWIH IRUIRY V DD V B SL SD SERIL INERFE DEODER ONROL DEODE LOGI ONROL/ REGISERS (EEPROM) SUS REGISERS (SRM) LRM MS OMPRE LRM REGS (EEPROM) RESE 8 WHDOG IMER LOW VOLGE RESE 4k EEPROM RRY Pin Descriptions PIN NUMBER SYMBOL DESRIPION 1 X1 he X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. 2 X2 he X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. 6 RESE RESE. his is a reset signal output. his signal notifies a host processor that the Watchdog time period has expired or that the voltage has dropped below a fixed V RIP threshold. It is an open drain active LOW output. Recommended value for the pull-up resistor is 5k. If unused, connect to ground. 7 GND Ground. 8 SD Serial Data (SD) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR ed with other open drain or open collector outputs. 9 SL he Serial lock (SL) input is used to clock all serial data into and out of the device. he input buffer on this pin is always active (not gated). 12 IRQ/F OU Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. It is an open drain output. he function is set via the configuration register. 13 V B his input provides a backup supply voltage to the device. V B supplies power to the device in the event that the V DD supply fails. his pin should be tied to ground if not used. 14 V DD Power Supply. 3, 4, 5, 10, 11 N No Internal onnection. FN6206 Rev 1.00 Page 2 of 29
Ordering Information PR NUMBER (Notes 1, 2, 3) PR MRING V B RIP POIN (V) BSW BI DEFUL SEING V RESE VOLGE (V) EMP. RNGE ( ) PGE (Pb-free) PG. DWG. # ISL12029IB27Z 12029IB27Z V DD < V B BSW = 1 2.63-40 to +85 14 Ld SOI M14.15 ISL12029IB27Z 12029IB27 Z V DD < V B BSW = 1 2.92-40 to +85 14 Ld SOI M14.15 ISL12029IB30Z 12029IB30 Z V DD < V B BSW = 1 3.09-40 to +85 14 Ld SOI M14.15 ISL12029IBZ 12029IBZ V DD < V B BSW = 1 4.38-40 to +85 14 Ld SOI M14.15 ISL12029IBZ 12029IBZ V DD < V B BSW = 1 4.64-40 to +85 14 Ld SOI M14.15 ISL12029IV27Z 12029 IV27Z V DD < V B BSW = 1 2.63-40 to +85 14 Ld SSOP M14.173 ISL12029IV27Z 12029 27Z V DD < V B BSW = 1 2.92-40 to +85 14 Ld SSOP M14.173 ISL12029IV30Z 12029 30Z V DD < V B BSW = 1 3.09-40 to +85 14 Ld SSOP M14.173 ISL12029IVZ 12029 IVZ V DD < V B BSW = 1 4.38-40 to +85 14 Ld SSOP M14.173 ISL12029IVZ 12029 IVZ V DD < V B BSW = 1 4.64-40 to +85 14 Ld SSOP M14.173 ISL12029IB27Z 12029IB 27Z 2.2 BSW = 0 2.63-40 to +85 14 Ld SOI M14.15 ISL12029IV27Z 2029 IV27Z 2.2 BSW = 0 2.63-40 to +85 14 Ld SSOP M14.173 NOES: 1. dd -* suffix for tape and reel. Please refer to B347 for details on reel specifications. 2. hese Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J SD- 020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12029, ISL12029. For more information on MSL please see techbrief B363. FN6206 Rev 1.00 Page 3 of 29
bsolute Maximum Ratings Voltage on V DD, V B, SL, SD, and IRQ/F OU Pins (respect to ground).......................... -0.3V to 6.0V Voltage on X1 and X2 Pins (respect to ground).......................... -0.3V to 2.5V Latchup (Note 4)................... lass II, Level B @ +85 ESD Rating Human Body Model (MIL-SD-883, Method 3014).......>±2kV Machine Model...................................>175V hermal Information hermal Resistance (ypical) J ( /W) J ( /W) 14 Ld SOI Package (Notes 5, 6).... 90 40 14 Ld SSOP Package (Note 5, 6)... 110 35 Maximum Junction emperature (Plastic Package)....... +150 Storage emperature........................-65 to +150 Pb-Free Reflow Profile.........................see link below http://www.intersil.com/pbfree/pb-freereflow.asp UION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOES: 4. Jedec lass II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins. 5. J is measured with the component mounted on a high effective thermal conductivity test board in free air. See ech Brief B379 for details. 6. For J, the case temp location is taken at the package top center. D Electrical Specifications Unless otherwise noted, V DD = +2.7V to +5.5V, = -40 to +85, ypical values are at = +25 and V DD = 3.3V. Boldface limits apply over the operating temperature range, -40 to +85. SYMBOL PRMEER ONDIIONS MIN (Note 16) YP MX (Note 16) UNI NOES V DD Main Power Supply 2.7 5.5 V V B Backup Power Supply 1.8 5.5 V Electrical Specifications Boldface limits apply over the operating temperature range, -40 to +85. SYMBOL PRMEER ONDIIONS MIN (Note 16) YP MX (Note 16) UNI NOES I DD1 Supply urrent with I 2 ctive V DD = 2.7V 500 µ 7, 8, 9 V DD = 5.5V 800 µ I DD2 I DD3 Supply urrent for Non-Volatile Programming Supply urrent for Main imekeeping (Low Power Mode) V DD = 2.7V 2.5 m 7, 8, 9, V DD = 5.5V 3.5 m V DD = V SD = V SL = 2.7V 10 µ 9 V DD = V SD = V SL = 5.5V 20 µ I B Battery Supply urrent V B = 1.8V, V DD = V SD = V SL = V RESE = 0V V B = 3.0V, V DD = V SD = V SL = V RESE = 0V 800 1000 n 7, 10, 11 850 1200 n I BLG Battery Input Leakage V DD = 5.5V, V B = 1.8V -100 100 n V RIP V B Mode hreshold 1.8 2.2 2.6 V 11 V RIPHYS V RIP Hysteresis 30 mv 11, 13 V BHYS V B Hysteresis 50 mv 11, 13 V DD SR- V DD Negative Slew Rate 10 V/ms 12 IRQ/F OU, RESE OUPUS V OL Output Low Voltage V DD = 5.5V I OL = 3m V DD = 2.7V I OL = 1m I LO Output Leakage urrent V DD = 5.5V V OU =5.5V 0.4 V 0.4 V 100 400 n FN6206 Rev 1.00 Page 4 of 29
Watchdog imer/low Voltage Reset Parameters SYMBOL PRMEER ONDIIONS MIN (Note 16) YP (Note 11) MX (Note 16) UNIS NOES t RPD V DD Detect to RESE LOW 500 ns 13 t PURS Power-Up Reset ime-out Delay 100 250 400 ms V RVLID Minimum VDD for Valid RESE Output 1.0 V V RESE ISL12029-4.5 Reset Voltage Level 4.59 4.64 4.69 V ISL12029 Reset Voltage Level 4.33 4.38 4.43 V ISL12029-3 Reset Voltage Level 3.04 3.09 3.14 V ISL12029-2.7 Reset Voltage Level 2.87 2.92 2.97 V ISL12029-2.7 Reset Voltage Level 2.58 2.63 2.68 V t WDO Watchdog imer Period 32.768kHz crystal between X1 and X2 1.70 1.75 1.801 s 725 750 775 ms 225 250 275 ms t RS Watchdog imer Reset ime-out Delay 32.768kHz crystal between X1 and X2 225 250 275 ms t RSP I 2 Interface Minimum Restart ime 1.2 µs EEPROM SPEIFIIONS EEPROM Endurance >2,000,000 ycles EEPROM Retention emperature 75 50 Years Serial Interface (I 2 ) Specifications - D/ haracteristics SYMBOL PRMEER ONDIIONS MIN (Note 16) YP MX (Note 16) UNIS NOES V IL SD, and SL Input Buffer LOW SBIB = 1 (Under V DD mode) -0.3 0.3 x V DD V Voltage V IH SD, and SL Input Buffer HIGH SBIB = 1 (Under V DD mode) 0.7 x V DD V DD + 0.3 V Voltage Hysteresis SD and SL Input Buffer SBIB = 1 (Under V DD mode) 0.05 x V DD V Hysteresis V OL SD Output Buffer LOW Voltage I OL =4m 0 0.4 V I LI Input Leakage urrent on SL V IN = 5.5V 0.1 10 µ I LO I/O Leakage urrent on SD V IN = 5.5V 0.1 10 µ IMING HRERISIS f SL SL Frequency 400 khz t IN Pulse Width Suppression ime at SD and SL Inputs ny pulse narrower than the max spec is suppressed. 50 ns t t BUF SL Falling Edge to SD Output Data Valid ime the Bus Must be Free Before the Start of a New ransmission SL falling edge crossing 30% of V DD, until SD exits the 30% to 70% of V DD window. SD crossing 70% of V DD during a SOP condition, to SD crossing 70% of V DD during the following SR condition. t LOW lock LOW ime Measured at the 30% of V DD crossing. 900 ns 1300 ns 1300 ns FN6206 Rev 1.00 Page 5 of 29
Serial Interface (I 2 ) Specifications - D/ haracteristics (ontinued) SYMBOL PRMEER ONDIIONS t HIGH lock HIGH ime Measured at the 70% of V DD crossing. t SU:S SR ondition Setup ime SL rising edge to SD falling edge. Both crossing 70% of V DD. t HD:S SR ondition Hold ime From SD falling edge crossing 30% of V DD to SL falling edge crossing 70% of V DD. t SU:D Input Data Setup ime From SD exiting the 30% to 70% of V DD window, to SL rising edge crossing 30% of V DD t HD:D Input Data Hold ime From SL falling edge crossing 70% of V DD to SD entering the 30% to 70% of V DD window. t SU:SO SOP ondition Setup ime From SL rising edge crossing 70% of V DD, to SD rising edge crossing 30% of V DD. t HD:SO SOP ondition Hold ime for Read, or Volatile Only Write From SD rising edge to SL falling edge. Both crossing 70% of V DD. MIN (Note 16) 600 ns 600 ns 600 ns 100 ns 0 ns 600 ns 600 ns t DH Output Data Hold ime From SL falling edge crossing 30% of V DD, until SD enters the 30% to 70% of V DD window. 0 ns pin SD, and SL Pin apacitance 10 pf t W Non-Volatile Write ycle ime 12 20 ms 14 t R SD and SL Rise ime From 30% to 70% of V DD 20 + 250 ns 15 0.1xb t F SD and SL Fall ime From 70% to 30% of V DD 20 + 250 ns 15 0.1 x b b apacitive Loading of SD or SL otal on-chip and off-chip 10 400 pf 15 Rpu SD and SL Bus Pull-up Resistor Off-chip Maximum is determined by t R and t F. For b = 400pF, max is about 2k ~2.5k. For b = 40pF, max is about 15k ~20k 1 k 15 NOES: 7. IRQ/F OU Inactive (no frequency output and no alarms). 8. V IL = V DD x 0.1, V IH = V DD x 0.9, f SL = 400kHz. 9. V RESE = 2.63V (VDD must be greater than V RESE ), VB = 0V. 10. Bit BSW = 0 (Standard Mode), R = 00h, V B 1.8V. 11. Specified at +25. 12. In order to ensure proper timekeeping, the V DD SR- specification must be followed. 13. Parameter is not 100% tested. 14. t W is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid SOP condition at the end of Write sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 15. hese are I 2 specific parameters and are not directly tested, however they are used during device testing to validate device specification. 16. ompliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. YP MX (Note 16) UNIS NOES FN6206 Rev 1.00 Page 6 of 29
iming Diagrams t F t HIGH t LOW t R t HD:SO SL t SU:D t SU:S t HD:S t HD:D t SU:SO SD (INPU IMING) t t DH t BUF SD (OUPU IMING) FIGURE 1. BUS IMING SL SD 8H BI OF LS BYE t W SOP ONDIION SR ONDIION FIGURE 2. WRIE YLE IMING t RSP t RSP >t WDO t RSP <t WDO t RSP >t WDO t RS t RS SL SD RESE SR SOP SR Note: ll inputs are ignored during the active reset period (t RS ). FIGURE 3. WHDOG IMING V RESE V DD t PURS t PURS t RPD t R t F RESE V RVLID FIGURE 4. RESE IMING FN6206 Rev 1.00 Page 7 of 29
ypical Performance urves emperature is +25 unless otherwise specified I B (µ) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 BSW = 0 OR 1 SL, SD PULL-UPS = 0V SL, SD PULL-UPS = V B BSW = 0 OR 1 0.0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 V B (V) 0.0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 V B (V) FIGURE 5. I B vs V B, SBIB = 0 FIGURE 6. I B vs V B, SBIB = 1 I B (µ) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 SL, SD PULL-UPS = 0V BSW = 0 OR 1 I DD (µ) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 V DD = 5.5V V DD = 3.3V 0.0-45 -35-25 -15-5 5 15 25 35 45 55 65 75 85 EMPERURE ( ) FIGURE 7. I DD3 vs EMPERURE I B (µ) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 V B = 3.0V 0.0-45 -35-25 -15-5 5 15 25 35 45 55 65 75 85 EMPERURE ( ) FIGURE 8. I B vs EMPERURE 4.5 80 I DD (µ) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 PPM HNGE FROM R = 0 60 40 20 0-20 0.0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 V DD (V) -40-32 -28-24 -20-16 -12-8 -4 0 4 8 12 16 20 24 28 R SEING FIGURE 9. I DD3 vs V DD FIGURE 10. F OU vs R SEING FN6206 Rev 1.00 Page 8 of 29
Description he ISL12029 device is a Real ime lock with clock/calendar, two polled alarms with integrated 512x8 EEPROM, oscillator compensation, PU Supervisor (Power-on Reset, Low Voltage Sensing and Watchdog imer) and battery backup switch. he oscillator uses an external, low-cost 32.768kHz crystal. ll compensation and trim components are integrated on the chip. his eliminates several external discrete components and a trim capacitor, saving board area and component cost. he Real-ime lock keeps track of time with separate registers for Hours, Minutes, Seconds. he alendar has separate registers for Date, Month, Year and Day-of-week. he calendar is correct through 2099, with automatic leap year correction. he Dual larms can be set to any lock/alendar value for a match. For instance, every minute, every uesday, or 5:23 M on March 21. he alarms can be polled in the Status Register or can provide a hardware interrupt (IRQ/F OU Pin). here is a repeat mode for the alarms allowing a periodic interrupt. he IRQ/F OU pin may be software selected to provide a frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive. he ISL12029 device integrates PU Supervisory functions (POR, WD) and Battery Switch. here is Power-On-Reset (RESE) output with 250ms delay from power-on when the V DD supply crosses the V RESE threshold for the device. It will also assert RESE when V DD goes below the specified V RESE threshold for the device. he V RESE threshold is selectable via VS2/VS1/VS0 registers to five (5) preselected levels. here is Watchdog imer (WD) with 3 selectable time-out periods (0.25s, 0.75s and 1.75s) and disabled setting. he WatchDog imer activates the RESE pin when it expires. Normally, the I 2 Interface is disabled when the RESE output is active, but this can be changed by using a register bit to enable I 2 operation in battery backup mode. he device offers a backup power input pin. his V B pin allows the device to be backed up by battery or Superap. he entire ISL12029 device is fully operational from 2.7 to 5.5V and the clock/calendar portion of the ISL12029 device remains fully operational down to 1.8V (Standby Mode). he ISL12029 device provides 4k bits of EEPROM with 8 modes of BlockLock control. he BlockLock allows a safe, secure memory for critical user and configuration data, while allowing a large user storage area. Pin Descriptions Serial lock (SL) he SL input is used to clock all data into and out of the device. he input buffer on this pin is always active (not gated). he pull-up resistor on this pin must use the same voltage source as V DD. Serial Data (SD) SD is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. he input buffer is always active (not gated). his open drain output requires the use of a pull-up resistor. he pull-up resistor on this pin must use the same voltage source as V DD. he output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. he circuit is designed for 400kHz I 2 interface speed. V B his input provides a backup supply voltage to the device. V B supplies power to the device in the event the V DD supply fails. his pin can be connected to a battery, a Superap or tied to ground if not used. Note that the device is not guaranteed to operate with V B < 1.8V. If the battery voltage is expected to drop lower than this minimum, correct operation of the device, (especially after a V DD power-down cycle) is not guaranteed. IRQ/F OU (Interrupt Output/Frequency Output) his dual function pin can be used as an interrupt or frequency output pin. he IRQ/F OU mode is selected via the frequency out control bits of the control/status register. Interrupt Mode. he pin provides an interrupt signal output. his signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output. Frequency Output Mode. he pin outputs a clock signal which is related to the crystal frequency. he frequency output is user selectable and enabled via the I 2 bus. It is an open drain output. he IRQ/F OU pin is an open drain output requiring a pull-up resistor which was intended to be used for clocking applications for micro controllers. hoose the pull-up resistor with care, since low values will cause high currents to flow in the V DD and ground traces around the device which can contribute to faulty oscillator function. For a 32kHz output, values up to 10k can be used with some degradation of the square waveform. RESE he RESE signal output can be used to notify a host processor that the Watchdog timer has expired or the VDD voltage supply has dipped below the V RESE threshold. It is an open drain, active LOW output. Recommended value for the pull-up resistor is 5k. If unused, it can be tied to ground. In battery mode, the Watchdog timer function is disabled. he RESE signal output is asserted LOW when the V DD voltage supply has dipped below the V RESE threshold but the RESE signal output will not return HIGH until the device is back to V DD mode (out of Battery Backup mode) even if the V DD voltage is above V RESE threshold. FN6206 Rev 1.00 Page 9 of 29
X1, X2 he X1 and X2 pins are the input and output, respectively, of an inverting amplifier. n external 32.768kHz quartz crystal is used with the ISL12029 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40 to +85. his oscillator compensation network can be used to calibrate the crystal timing accuracy over-temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. X2 is intended to drive a crystal only, and should not drive any external circuit. No external compensation resistors or capacitors are needed or are recommended to be connected to the X1 and X2 pins. Real ime lock Operation he Real ime lock (R) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of the second, minute, hour, day, date, month, and year. he R has leap-year correction. he clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or M/PM format. When the ISL12029 powers up after the loss of both V DD and V B, the clock will not operate until at least one byte is written to the clock register. Reading the Real ime lock he R is read by initiating a Read command and specifying the address corresponding to the register of the Real ime lock. he R Registers can then be read in a Sequential Read Mode. Since the clock runs continuously and read takes a finite amount of time, there is a possibility that the clock could change during the course of a read operation. In this device, the time is latched by the read command (falling edge of the clock on the bit prior to R data output) into a separate latch to avoid time changes during the read operation. he clock continues to run. larms occurring during a read are unaffected by the read operation. Writing to the Real ime lock he time and date may be set by writing to the R registers. R Register should be written ONLY with Page Write. o avoid changing the current time by an uncompleted write operation, write to the all 8 bytes in one write operation. When writing the R registers, the new time value is loaded into a separate buffer at the falling edge of the clock during the cknowledge. his new R value is loaded into the R Register by a stop bit at the end of a valid write sequence. n invalid write operation aborts the time update procedure and the contents of the buffer are discarded. fter a valid write operation the R will reflect the newly loaded data beginning X1 X2 FIGURE 11. REOMMENDED RYSL ONNEION with the next one second clock cycle after the stop bit is written. he R continues to update the time while an R register write is in progress and the R continues to run during any non-volatile write sequences. ccuracy of the Real ime lock he accuracy of the Real ime lock depends on the accuracy of the quartz crystal that is used as the time base for the R. Since the resonant frequency of a crystal is temperature dependent, the R performance will also be dependent upon temperature. he frequency deviation of the crystal is a function of the turnover-temperature of the crystal from the crystal s nominal frequency. For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. hese parameters are available from the crystal manufacturer. Intersil s R family provides on-chip crystal compensation networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information, see pplication Section on page 22. lock/ontrol Registers (R) he ontrol/lock Registers are located in an area separate from the EEPROM array and are only accessible following a slave byte of 1101111x and reads or writes to addresses [0000h:003Fh]. he clock/control memory map has memory addresses from 0000h to 003Fh. he defined addresses are described in able 2. Writing to and reading from the undefined addresses are not recommended. R ccess he contents of the R can be modified by performing a byte or a page write operation directly to any address in the R. Prior to writing to the R (except the status register), however, the WEL and RWEL bits must be set using a three step process (See Writing to the lock/ontrol Registers on page 15.) he R is divided into 5 sections. hese are: 1. larm 0 (8 bytes; non-volatile) 2. larm 1 (8 bytes; non-volatile) 3. ontrol (5 bytes; non-volatile) 4. Real ime lock (8 bytes; volatile) 5. Status (1 byte; volatile) Each register is read and written through buffers. he non-volatile portion (or the counter portion of the R) is updated only if RWEL is set and only after a valid write operation and stop bit. sequential read or page write operation provides access to the contents of only one section of the R per operation. ccess to another section requires a new operation. read or write can begin at any address in the R. It is not necessary to set the RWEL bit prior to writing the status register. Section 5 (status register) supports a single FN6206 Rev 1.00 Page 10 of 29
byte read or write only. ontinued reads or writes from this section terminates the operation. he state of the R can be read by performing a random read at any address in the R at any time. his returns the contents of that register location. dditional registers are read by performing a sequential read. he read instruction latches all lock registers into a buffer, so an update of the clock does not change the time being read. sequential read of the R will not result in the output of data from the memory array. t the end of a read, the master supplies a stop condition to end the operation and free the bus. fter a read of the R, the address remains at the previous address +1 so the user can execute a current address read of the R and continue reading the next Register. Real ime lock Registers (Volatile) S, MN, HR, D, MO, YR: lock/alendar Registers hese registers depict BD representations of the time. s such, S (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an M or PM indicator (H21-bit) or 0 to 23 (with MIL = 1), D (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99. DW: Day of the Week Register his register provides a Day of the Week status and uses three bits DY2 to DY0 to represent the seven days of the week. he counter advances in the cycle 0-1-2-3-4-5-6-0-1-2- he assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. he default value is defined as 0. Y2: Year 2000 Register an have value 19 or 20. s of the date of the introduction of this device, there would be no real use for the value 19 in a true real time clock, however. 24-Hour ime If the MIL bit of the HR register is 1, the R uses a 24-hour format. If the MIL bit is 0, the R uses a 12-hour format and H21-bit functions as an M/PM indicator with a 1, representing PM. he clock defaults to standard time with H21 = 0. Leap Years Leap years add the day February 29 and are defined as those years that are divisible by 4. Status Register (SR) (Volatile) he Status Register is located in the R memory map at address 003Fh. his is a volatile register only and is used to control the WEL and RWEL write enable latches, read power status and two alarm bits. his register is separate from both the array and the lock/ontrol Registers (R). BLE 1. SUS REGISER (SR) DDR 7 6 5 4 3 2 1 0 003Fh B L1 L0 OSF 0 RWEL WEL RF Default 0 0 0 0 0 0 0 1 B: Battery Supply his bit set to 1 indicates that the device is operating from V B, not V DD. It is a read-only bit and is set/reset by hardware (ISL12029 internally). Once the device begins operating from V DD, the device sets this bit to 0. L1, L0: larm Bits hese bits announce if either alarm 0 or alarm 1 match the real time clock. If there is a match, the respective bit is set to 1. he falling edge of the last data bit in a SR Read operation resets the flags. Note: Only the L bits that are set when an SR read starts will be reset. n alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. OSF: Oscillator Fail Indicator his bit is set to "1" if the oscillator is not operating or is operating but has clock jitter, which does not affect the accuracy of R counting. he bit is set to "0" if the oscillator is functioning and does not have clock jitter. his bit is read only, and is set/reset by hardware. RWEL: Register Write Enable Latch his bit is a volatile latch that powers up in the LOW (disabled) state. he RWEL bit must be set to 1 prior to any writes to the lock/ontrol Registers. Writes to RWEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. write to the R requires both the RWEL and WEL bits to be set in a specific sequence. WEL: Write Enable Latch he WEL bit controls the access to the R during a write operation. his bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the R address will be ignored, although acknowledgment is still issued. he WEL bit is set by writing a 1 to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a 0 to the WEL bit and zeroes to the other bits of the Status Register) or until the part powers up again. Writes to WEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. RF: Real ime lock Fail Bit his bit is set to a 1 after a total power failure. his is a read only bit that is set by hardware (ISL12029 internally) when the device powers up after having lost all power to the device (both V DD and V B go to 0V). he bit is set regardless of FN6206 Rev 1.00 Page 11 of 29
whether V DD or V B is applied first. he loss of only one of the supplies does not set the RF bit to 1. On power-up after a total power failure, all registers are set to their default states and the clock will not increment until at least one byte BLE 2. LO/ONROL MEMORY MP is written to the clock register. he first valid write to the R section after a complete power failure resets the RF bit to 0 (writing one byte is sufficient). DDR. YPE REG NME BI 7 6 5 4 3 2 1 0 RNGE ISL12029 DEFUL ISL12029 DEFUL 003F Status SR B L1 L0 OSF 0 RWEL WEL RF 01h 01h 0037 R Y2 0 0 Y221 Y220 Y213 0 0 Y210 19/20 20h 20h 0036 (SRM) DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h 00h 0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h 00h 0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h 00h 0033 D 0 0 D21 D20 D13 D12 D11 D10 1-31 01h 01h 0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h 00h 0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h 00h 0030 S 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h 00h 0014 ontrol PWR SBIB BSW 0 0 0 VS2 VS1 VS0 4Xh 0Xh 0013 (EEPROM) DR 0 0 0 0 0 DR2 DR1 DR0 00h 00h 0012 R 0 0 R5 R4 R3 R2 R1 R0 00h 00h 0011 IN IM L1E L0E FO1 FO0 0 0 0 00h 00h 0010 BL BP2 BP1 BP0 WD1 WD0 0 0 0 18h 18h 000F larm1 Y21 0 0 1Y221 1Y220 1Y213 0 0 1Y210 19/20 20h 20h 000E (EEPROM) DW1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h 00h 000D YR1 Unused - Default = R Year value (No EEPROM) - Future expansion 000 MO1 EMO1 0 0 1G20 1G13 1G12 1G11 1G10 1-12 00h 00h 000B D1 ED1 0 1D21 1D20 1D13 1D12 1D11 1D10 1-31 00h 00h 000 HR1 EHR1 0 1H21 1H20 1H13 1H12 1H11 1H10 0-23 00h 00h 0009 MN1 EMN1 1M22 1M21 1M20 1M13 1M12 1M11 1M10 0-59 00h 00h 0008 S1 ES1 1S22 1S21 1S20 1S13 1S12 1S11 1S10 0-59 00h 00h 0007 larm0 Y20 0 0 0Y221 0Y220 0Y213 0 0 0Y210 19/20 20h 20h 0006 (EEPROM) DW0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h 00h 0005 YR0 Unused - Default = R Year value (No EEPROM) - Future expansion 0004 MO0 EMO0 0 0 0G20 0G13 0G12 0G11 0G10 1-12 00h 00h 0003 D0 ED0 0 0D21 0D20 0D13 0D12 0D11 0D10 1-31 00h 00h 0002 HR0 EHR0 0 0H21 0H20 0H13 0H12 0H11 0H10 0-23 00h 00h 0001 MN0 EMN0 0M22 0M21 0M20 0M13 0M12 0M11 0M10 0-59 00h 00h 0000 S0 ES0 0S22 0S21 0S20 0S13 0S12 0S11 0S10 0-59 00h 00h NOE: Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation, see device Ordering Information on on page 3. FN6206 Rev 1.00 Page 12 of 29
Unused Bits: Bit 3 in the SR is not used, but must be zero. he Data Byte output during a SR read will contain a zero in this bit location. larm Registers (Non-Volatile) larm0 and larm1 he alarm register bytes are set up identical to the R register bytes, except that the MSB of each byte functions as an enable bit (enable = 1 ). hese enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year. he alarm function works as a comparison between the alarm registers and the R registers. s the R advances, the alarm will be triggered once a match occurs between the alarm registers and the R registers. ny one alarm register, multiple registers, or all registers can be enabled for a match. See Device Operation on page 15 and pplication Section on page 22 for more information. ontrol Registers (Non-Volatile) he ontrol Bits and Registers described in the following are non-volatile. BL Register BP2, BP1, BP0 - Block Protect Bits he Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. write to a protected block of memory is ignored. he block protect bits will prevent write operations to one of eight segments of the array. he partitions are described in able 3. BP2 BLE 3. BLO PROE BIS PRIIONS PROEED DDRESSES ISL12029 RRY LO BP1 BP0 0 0 0 None (Default) None 0 0 1 180 h 1FF h Upper 1/4 0 1 0 100 h 1FF h Upper 1/2 0 1 1 000 h 1FF h Full rray 1 0 0 000 h 03F h First 4 Pages 1 0 1 000 h 07F h First 8 Pages 1 1 0 000 h 0FF h First 16 Pages 1 1 1 000 h 1FF h Full rray IN Register: Interrupt ontrol and Frequency Output Register IM, L1E, L0E - Interrupt ontrol and Status Bits here are two Interrupt ontrol bits, larm 1 Interrupt Enable (L1E) and larm 0 Interrupt Enable (L0E) to specifically enable or disable the alarm interrupt signal output (IRQ/F OU ). he interrupts are enabled when either the L1E or L0E or both bits are set to 1 and both the FO1 and FO0 bits are set to 0 (F OU disabled). he IM bit enables the pulsed interrupt mode. o enter this mode, the L0E or L1E bits are set to 1, and the IM bit to 1. he IRQ/F OU output will now be pulsed each time an alarm occurs. his means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. his mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. In the case that both larm 0 and larm 1 are enabled, the IRQ/F OU pin will be pulsed each time either alarm matches the R (both alarms can provide hardware interrupt). If the IM bit is also set to "1", the IRQ/F OU will be pulsed for each of the alarms as well. FO1, FO0 - Programmable Frequency Output Bits hese are two output control bits. hey select one of three divisions of the internal oscillator, that is applied to the IRQ/FOU output pin. able 4 shows the selection bits for this output. When using this function, the larm output function is disabled. BLE 4. PROGRMMBLE FREQUENY OUPU BIS FO1 FO0 OUPU FREQUENY 0 0 larm output (F OU disabled) 0 1 32.768kHz 1 0 4096Hz 1 1 1Hz Oscillator ompensation Registers here are two trimming options. - R - nalog rimming Register - DR - Digital rimming Register hese registers are non-volatile. he combination of analog and digital trimming can give up to -64ppm to +110 ppm of total adjustment. R Register - R5, R4, R3, R2, R1, R0: nalog rimming Register Six analog trimming bits, R0 to R5, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the R. Each bit has a different weight for capacitance adjustment. For example, using a itizen FS- 206 crystal with different R bit combinations provides an estimated ppm adjustment range from -34ppm to +80ppm to the nominal frequency compensation. FN6206 Rev 1.00 Page 13 of 29
BLE 5. DIGIL RIMMING REGISERS (ontinued) X1 X2 X1 RYSL OSILLOR DR REGISER DR2 DR1 DR0 ESIMED FREQUENY PPM 0 1 0 +10 0 0 1 +20 X2 0 1 1 +30 1 0 0 0 1 1 0-10 FIGURE 12. DIGRM OF R he effective on-chip series load capacitance, LOD, ranges from 4.5pF to 20.25pF with a mid-scale value of 12.5pF (default). LOD is changed via two digitally controlled capacitors, X1 and X2, connected from the X1 and X2 pins to ground (see Figure 11). he value of X1 and X2 is given by Equation 1: = 16 b5 X + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9 pf he effective series load capacitance is the combination of X1 and X2 given in Equation 2: 1 = LOD ---------------------------------- 1 1 ---------- + ---------- X1 X2 For example, LOD(R = 00000) = 12.5pF, LOD (R = 100000) = 4.5pF, and LOD (R = 011111) = 20.25pF. he entire range for the series combination of load capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values. DR Register - DR2, DR1, DR0: Digital rimming Register he digital trimming Bits DR2, DR1 and DR0 adjust the number of counts per second and average the ppm error to achieve better accuracy. DR2 is a sign bit. DR2 = 0 means frequency compensation is > 0. DR2 = 1 means frequency compensation is < 0. DR1 and DR0 are scale bits. DR1 gives 10ppm adjustment and DR0 gives 20ppm adjustment. range from -30ppm to +30ppm can be represented by using the three DR bits. BLE 5. DIGIL RIMMING REGISERS DR REGISER DR2 DR1 DR0 (EQ. 1) 16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9 = ---------------------------------------------------------------------------------------------------------------------------- LOD pf 2 (EQ. 2) ESIMED FREQUENY PPM 1 0 1-20 1 1 1-30 PWR Register: SBIB, BSW, VS2, VS1, VS0 SBIB: Serial Bus Interface (Enable) he serial bus can be disabled in battery backup mode by setting this bit to 1. his will minimize power drain on the battery. he Serial Interface can be enabled in battery backup mode by setting this bit to 0. (default is 0 ). See RESE on page 9 and Power ontrol Operation on page 16. BSW: Power ontrol Bit he Power ontrol bit, BSW, determines the conditions for switching between V DD and Back Up Battery. here are two options. Option 1 Standard Mode: Set BSW = 0 (default for ISL12029) Option 2 Legacy/Default Mode: Set BSW = 1 (default for ISL12029) See Power ontrol Operation on page 16 for more details. lso see I 2 ommunications During Battery Backup and LVR Operation on page 24 for important details. VS2, VS1, VS0: V RESE Select Bits he ISL12029 is shipped with a default V DD threshold (V RESE ) per the ordering information table. his register is a non-volatile with no protection, therefore any writes to this location can change the default value from that marked on the package. If not changed with a non-volatile write, this value will not change over normal operating and storage conditions. However, ISL12029 has four (4) additional selectable levels to fit the customers application. Levels are: 4.64V(default), 4.38V, 3.09V, 2.92V and 2.63V. he V RESE selection is via 3 bits (VS2, VS1 and VS0) (see able 6). are should be taken when changing the V RESE select bits. If the V RESE voltage selected is higher than V DD, then the device will go into RESE and unless V DD is increased, the device will no longer be able to communicate using the I 2 bus. 0 0 0 0 FN6206 Rev 1.00 Page 14 of 29
In battery mode, the RESE signal output is asserted LOW when the V DD voltage supply has dipped below the V RESE threshold, but the RESE signal output will not return HIGH until the device is back to V DD mode even the V DD voltage is above V RESE threshold. Device Operation Writing to the lock/ontrol Registers hanging any of the bits of the clock/control registers requires the following steps: 1. Write a 02h to the Status Register to set the Write Enable Latch (WEL). his is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). 2. Write a 06h to the Status Register to set both the Register Write Enable Latch (RWEL) and the WEL bit. his is also a volatile cycle. he zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). Write all eight bytes to the R registers, or one byte to the SR, or one to five bytes to the control registers. his sequence starts with a start bit, requires a slave byte of 11011110 and an address within the R and is terminated by a stop bit. write to the EEPROM registers in the R will initiate a nonvolatile write cycle and will take up to 20ms to complete. write to the R registers (SRM) will require much shorter cycle time (t = t BUF ). Writes to undefined areas have no effect. he RWEL bit is reset by the completion of a write to the R, so the sequence must be repeated to again initiate another change to the R contents. If the sequence is not completed for any reason (by sending an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not reset and the device remains in an active mode. Writing all zeros to the status register resets both the WEL and RWEL bits. read operation occurring between any of the previous operations will not interrupt the register write operation. larm Operation BLE 6. V RESE SELE BIS VS2 VS1 VS0 V RESE (V) 0 0 0 4.64 0 0 1 4.38 0 1 0 3.09 0 1 1 2.92 1 0 0 2.63 Since the alarm works as a comparison between the alarm registers and the R registers, it is ideal for notifying a host processor of a particular time event and trigger some action as a result. he host can be notified by either a hardware interrupt (the IRQ/F OU pin) or by polling the Status Register (SR) larm bits. hese two volatile bits (L1 for larm 1 and L0 for larm 0), indicate if an alarm has happened. he bits are set on an alarm condition regardless of whether the IRQ/F OU interrupt is enabled. he L1 and L0 bits in the status register are reset by the falling edge of the eighth clock of status register read. here are two alarm operation modes: Single Event and periodic Interrupt Mode: 1. Single Event Mode is enabled by setting the L0E or L1E bit to 1, the IM bit to 0, and disabling the frequency output. his mode permits a one-time match between the alarm registers and the R registers. Once this match occurs, the L0 or L1 bit is set to 1 and the IRQ/F OU output will be pulled low and will remain low until the L0 or L1 bit is read, which will automatically resets it. Both larm registers can be set at the same time to trigger alarms. he IRQ/F OU output will be set by either alarm, and will need to be cleared to enable triggering by a subsequent alarm. Polling the SR will reveal which alarm has been set. 2. Interrupt Mode (or Pulsed Interrupt Mode or PIM) is enabled by setting the L0E or L1E bit to 1 the IM bit to 1, and disabling the frequency output. If both L0E and L1E bits are set to "1", then both L0E and L1E PIM alarms will function. he IRQ/F OU output will now be pulsed each time each of the alarms occurs. his means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. his mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. Interrupt Mode NNO be used for general periodic alarms, however, since a specific time period cannot be programmed for interrupt, only matches to a specific time of day. he interrupt mode is only stopped by disabling the IM bit or the larm Enable bits. Writing to the larm Registers he larm Registers are non-volatile but require special attention to insure a proper non-volatile write takes place. Specifically, byte writes to individual registers are good for all but registers 0006h and 0000Eh, which are the DW0 and DW1 registers, respectively. hose registers will require a special page write for non-volatile storage. he recommended page write sequences are as follows: 1. 16-byte page writes: he best way to write or update the larm Registers is to perform a 16-byte write beginning at address 0001h (MN0) and wrapping around and ending at address 0000h (S0). his will insure that non-volatile storage takes place. his means that the code must be designed so that the larm0 data is written starting with Minutes register, and then all the larm1 data, with the last byte being the larm0 Seconds (the page ends at the larm1 Y2k register and then wraps around to address 0000h). lternatively, the 16-byte page write could start with address 0009h, wrap around and finish with address 0008h. Note that any page write ending at address 0007h or 000Fh (the highest byte in each larm) will not trigger a non-volatile write, so wrapping around or overlapping to the following larm's Seconds register is advised. FN6206 Rev 1.00 Page 15 of 29
2. Other non-volatile writes: It is possible to do writes of less than an entire page, but the final byte must always be addresses 0000h through 0004h or 0008h though 000h to trigger a non-volatile write. Writing to those blocks of 5 bytes sequentially, or individually, will trigger a non-volatile write. If the DW0 or DW1 registers need to be set, then enough bytes will need to be written to overlap with the other larm register and trigger the non-volatile write. For Example, if the DW0 register is being set, then the code can start with a multiple byte write beginning at address 0006h, and then write 3 bytes ending with the S1 register as follows: ddr Name 0006h DW0 0007h Y20 0008h S1 If the larm1 is used, S1 would need to have the correct data written. Power ontrol Operation he power control circuit accepts a V DD and a V B input. Many types of batteries can be used with Intersil R products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power an Intersil R device for up to 10 years. nother option is to use a Superap for applications where V DD is interrupted for up to a month. See pplication Section on page 22 for more information. Standard Mode Power Switchover Normal Operating Mode (V DD ) to Battery Backup Mode (V B ) o transition from the V DD to V B mode, both of the following conditions must be met: - ondition 1: V DD < V B - V BHYS where V BHYS 50mV - ondition 2: V DD < V RIP where V RIP 2.2V Battery Backup Mode (V B ) to Normal Mode (V DD ) he ISL12029 device will switch from the V B to V DD mode when one of the following conditions occurs: - ondition 1: V DD > V B + V BHYS where V BHYS 50mV - ondition 2: V DD > V RIP + V RIPHYS where V RIPHYS 30mV here are two discrete situations that are possible when using Standard Mode: V B < V RIP and V B > V RIP. hese two power control situations are illustrated in Figures 13 and 14. here are two options for setting the change-over conditions from V DD to Battery back-up mode. he BSW bit in the PWR register controls this operation. V DD BERY BUP MODE Option 1 - Standard Mode (Default for ISL12029) Option 2 - Legacy Mode (Default for ISL12029) V RIP V B 2.2V 1.8V BLE 7. V B RIP POIN WIH DIFFEREN BSW SEING BSW BI V B RIP POIN (V) POWER ONROL SEING 0 2.2 Standard Mode (ISL12029) 1 V DD < V B Legacy Mode (ISL12029) VB - V BHYS V B + V BHYS FIGURE 13. BERY SWIHOVER WHEN V B < V RIP Note that applications that have V B > V DD will require the ISL12029 (standard mode) for proper startup. Note that the I 2 bus may or may not be operational during battery backup, that function is controlled by the SBIB bit. hat operation is covered after the power control section. OPION 1 - SNDRD POWER ONROL MODE (DEFUL FOR ISL12029) In the Standard mode, the supply will switch over to the battery when V DD drops below VRIP or VB, whichever is lower. In this mode, accidental operation from the battery is prevented since the battery backup input will only be used when the V DD supply is shut off. o select Option 1, BSW bit in the Power Register must be set to BSW = 0. description of power switchover follows. V DD V B V RIP BERY BUP MODE 3.0V V RIP 2.2V V RIP + V RIPHYS FIGURE 14. BERY SWIHOVER WHEN V B > V RIP OPION 2 - LEGY POWER ONROL MODE (DEFUL FOR ISL12029) he Legacy Mode follows conditions set in X1226 products. In this mode, switching from V DD to V B is simply done by comparing the voltages and the device operates from whichever FN6206 Rev 1.00 Page 16 of 29
is the higher voltage. are should be taken when changing from Normal to Legacy Mode. If the V B voltage is higher than V DD, then the device will enter battery backup and unless the battery is disconnected or the voltage decreases, the device will no longer operate from V DD. If that is the situation on initial powerup, then I 2 communication may not be possible. For these applications, the ISL12029 should be used. o select the Option 2, BSW bit in the Power Register must be set to BSW = 1. Normal Mode (V DD ) to Battery Backup Mode (V B ) o transition from the V DD to V B mode, the following conditions must be met: V DD < V B - V BHYS Battery Backup Mode (V B ) to Normal Mode (V DD ) he device will switch from the V B to V DD mode when the following condition occurs: V DD > V B +V BHYS he Legacy Mode power control conditions are illustrated in Figure 15. V B OFF V DD VOLGE FIGURE 15. BERY SWIHOVER IN LEGY MODE Power-on Reset pplication of power to the ISL12029 activates a Power-on Reset ircuit that pulls the RESE pin active. his signal provides several benefits. - It prevents the system microprocessor from starting to operate with insufficient voltage. - It prevents the processor from operating prior to stabilization of the oscillator. - It allows time for an FPG to download its configuration prior to initialization of the circuit. - It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power-up. When V DD exceeds the device V RESE threshold value for typically 250ms the circuit releases RESE, allowing the system to begin operation. Recommended slew rate is between 0.2V/ms and 50V/ms. NOE: If the V B voltage drops below the data sheet minimum of 1.8V and the V DD power cycles to 0V then back to V DD voltage, then the RESE output may stay low and the I 2 communications will not operate. he V B and V DD power will ON IN need to be cycled to 0V together to allow normal operation again. Watchdog imer Operation he Watchdog timer time-out period is selectable. By writing a value to WD1 and WD0, the Watchdog timer can be set to 3 different time-out periods or off. When the Watchdog timer is set to off, the Watchdog circuit is configured for low power operation (see able 8). BLE 8. WHDOG IMER OPERION WD1 WD0 DURION 1 1 disabled 1 0 250ms 0 1 750ms 0 0 1.75s Watchdog imer Restart he Watchdog imer is started by a falling edge of SD when the SL line is high (SR condition). he start signal restarts the Watchdog timer counter, resetting the period of the counter back to the maximum. If another SR fails to be detected prior to the Watchdog timer expiration, then the RESE pin becomes active for one reset time out period. In the event that the start signal occurs during a reset time out period, the start will have no effect. When using a single SR to refresh Watchdog timer, a SOP condition should be followed to reset the device back to stand-by mode (see Figure 3). In battery mode, the Watchdog timer function is disabled. Low Voltage Reset (LVR) Operation When a power failure occurs, a voltage comparator compares the level of the V DD line versus a preset threshold voltage (V RESE ), then generates a RESE pulse if it is below V RESE. he reset pulse will time-out 250ms after the V DD line rises above V RESE. If the V DD remains below V RESE, then the RESE output will remain asserted low. Power-up and powerdown waveforms are shown in Figure 4. he LVR circuit is to be designed so the RESE signal is valid down to V DD =1.0V. When the LVR signal is active, unless the part has been switched into the battery mode, the completion of an in-progress non-volatile write cycle is unaffected, allowing a non-volatile write to continue as long as possible (down to the Reset Valid Voltage). he LVR signal, when active, will terminate any in-progress communications to the device and prevents new commands from disrupting any current write operations. See I 2 ommunications During Battery Backup and LVR Operation on page 24. In battery mode, the RESE signal output is asserted LOW when the V DD voltage supply has dipped below the V RESE threshold. he RESE signal output will not return HIGH until the device is back to V DD mode even the V DD voltage is above V RESE threshold. FN6206 Rev 1.00 Page 17 of 29