CD5/7HC13, CD5/7HCT13, CD7HC3, CD7HCT3 Data sheet acquired from Harris Semiconductor SCHS1A September 1997 - Revised May 000 High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets Features Description [ /Title (CD7 HC13, CD7 HCT1 3, CD7 HC3, CD7 HCT 3) /Subject High peed Overriding Reset Terminates Output Pulse Triggering From the Leading or Trailing Edge Q and Q Buffered Outputs Separate Resets Wide Range of Output-Pulse Widths Schmitt Trigger on Both A and B Inputs Fanout (Over Temperature Range) - Standard Outputs............... 10 LSTTL Loads - Bus Driver Outputs............. 15 LSTTL Loads Wide Operating Temperature Range... -55 o C to 15 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - V to V Operation - High Noise Immunity: N IL = 30%, N IH = 30%of at = 5V HCT Types -.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Pinout CD5HC13, CD5HCT13 (CERDIP) CD7HC13, CD7HCT13, CD7HC3, CD7HCT3 (PDIP, SOIC) TOP VIEW The HC13, HCT13, CD7HC3 and CD7HCT3 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 13 types can be triggered by a negative to positive reset pulse; whereas the 3 types do not have this feature. An external resistor (R X ) and an external capacitor (C X ) control the timing and the accuracy for the circuit. Adjustment of Rx and C X provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses. Once triggered, the output pulse width may be extended by retriggering inputs A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A) and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A, B, and R) must be terminated high or low. The minimum value of external resistance, Rx is typically 5kΩ. The minimum value external capacitance, C X, is 0pF. The calculation for the pulse width is = 0.5 R X C X at = 5V. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD5HC13F -55 to 15 1 Ld CERDIP CD5HC13F3A -55 to 15 1 Ld CERDIP CD7HC13E -55 to 15 1 Ld PDIP CD7HC13M -55 to 15 1 Ld SOIC CD5HCT13F3A -55 to 15 1 Ld CERDIP CD7HCT13E -55 to 15 1 Ld PDIP CD7HCT13M -55 to 15 1 Ld SOIC 1A 1 1 CD7HC3E -55 to 15 1 Ld PDIP 1B 1R 1Q 3 15 1 13 1R X C X 1C X 1Q CD7HC3M -55 to 15 1 Ld SOIC CD7HCT3E -55 to 15 1 Ld PDIP Q 5 1 Q CD7HCT3M -55 to 15 1 Ld SOIC C X R X C X 7 8 11 10 9 R B A NOTES: 1. When ordering, use the entire part number. Add the suffix 9 to obtain the variant in the tape and reel.. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 000, Texas Instruments Incorporated 1
Functional Diagram CD5/7HC13, CD5/7HCT13, CD7HC3, CD7HCT3 1Cx 1Rx 1 15 1A 1B 1 1Cx 1RxCx MONO 1 13 1Q 1Q 1R 3 R 11 A 9 5 Q B 10 MONO 1 Q Cx RxCx 7 Cx Rx TRUTH TABLE INPUTS OUTPUTS A B R Q Q CD7HC/HCT13 H X H L H X L H L H L H H H X X L L H L H CD7HC/HCT3 H X H L H X L H L H L H H H X X L L H NOTE: H = High Level, L = Low Level, X = Don t Care.
CD5/7HC13, CD5/7HCT13, CD7HC3, CD7HCT3 Absolute Maximum Ratings DC Supply,........................ -0.5V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > + 0.5V......................±0mA DC Output Diode Current, I OK For V O < -0.5V or V O > + 0.5V....................±0mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < + 0.5V....................±5mA DC or Ground Current, I CC or I..................±50mA Thermal Information Thermal Resistance (Typical, Note 3) θ JA ( o C/W) PDIP Package............................. 90 SOIC Package............................. 115 Maximum Junction Temperature....................... 150 o C Maximum Storage Temperature Range..........-5 o C to 150 o C Maximum Lead Temperature (Soldering 10s)............. 300 o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range (T A )..................... -55 o C to 15 o C Supply Range, HC Types.....................................V to V HCT Types..................................5V to 5.5V DC Input or Output, V I, V O................. 0V to Input Rise and Fall Time V...................................... 1000ns (Max).5V...................................... 500ns (Max) V....................................... 00ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Quiescent Device Current SYMBOL TEST CONDITIONS 5 o C -0 o C TO 85 o C -55 o C TO 15 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH - - 1.5 - - 1.5-1.5 - V.5 3.15 - - 3.15-3.15 - V. - -. -. - V V IL - - - - 0.5-0.5-0.5 V.5 - - 1.35-1.35-1.35 V - - 1.8-1.8-1.8 V V OH V IH or V IL -0.0 1.9 - - 1.9-1.9 - V -0.0.5. - -. -. - V -0.0 5.9 - - 5.9-5.9 - V - - - - - - - - - V -.5 3.98 - - 3.8-3.7 - V -5. 5.8 - - 5.3-5. - V V OL V IH or V IL 0.0 - - 0.1-0.1-0.1 V 0.0.5 - - 0.1-0.1-0.1 V 0.0 - - 0.1-0.1-0.1 V I I I CC or or - - - - - - - - - V.5 - - 0. - 0.33-0. V 5. - - 0. - 0.33-0. V - - - ±0.1 - ±1 - ±1 µa 0 - - 8-80 - 10 µa 3
CD5/7HC13, CD5/7HCT13, CD7HC3, CD7HCT3 DC Electrical Specifications (Continued) PARAMETER HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load SYMBOL V IH - -.5 to 5.5 V IL - -.5 to 5.5 - - - - V - - 0.8-0.8-0.8 V V OH V IH or V IL -0.0.5. - -. -. - V -.5 3.98 - - 3.8-3.7 - V V OL V IH or V IL 0.0.5 - - 0.1-0.1-0.1 V I I I CC I CC TEST CONDITIONS 5 o C -0 o C TO 85 o C -55 o C TO 15 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX and or -.1.5 - - 0. - 0.33-0. V 0 5.5 - ±0.1 - ±1 - ±1 µa 0 5.5 - - 8-80 - 10 µa -.5 to 5.5 NOTE: For dual-supply systems theoretical worst case (V I =.V, = 5.5V) specification is 1.8mA. HCT Input Loading Table - 100 30-50 - 90 µa INPUT UNIT LOADS All 0.35 NOTE: Unit Load is I CC limit specified in DC Electrical Table, e.g. 30µA max at 5 o C. Prerequisite for Switching Specifications 5 o C -0 o C TO 85 o C -55 o C TO 15 o C PARAMETER SYMBOL (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX HC TYPES Minimum Input, Pulse Width L A 100 - - 15 - - 150 - - ns.5 0 - - 5 - - 30 - - ns 17 - - 1 - - - - ns B H 100 - - 15 - - 150 - - ns.5 0 - - 5 - - 30 - - ns 17 - - 1 - - - - ns
CD5/7HC13, CD5/7HCT13, CD7HC3, CD7HCT3 Prerequisite for Switching Specifications (Continued) 5 o C -0 o C TO 85 o C -55 o C TO 15 o C PARAMETER SYMBOL (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX R L 100 - - 15 - - 150-150 ns.5 0 - - 5 - - 30-30 ns 17 - - 1 - - - ns A and B Hold Time t H 50 - - 5 - - 75-75 ns.5 10 - - 13 - - 15-15 ns 9 - - 11 - - 13-13 ns Reset Removal Time t REM 50 - - 5 - - 75-75 ns.5 10 - - 13 - - 15-15 ns 9 - - 11 - - 13-13 ns Retrigger Time Number t rt 5 - - - - - - - - - ns R X = 10KΩ, C X = 0-50 - - 3 - - 7 - ns Output Pulse Width 5 Q or Q R X = 10KΩ, C X = 10nF 0-50 38.7-51.3 38. - 51.8 µs HCT TYPES Minimum Input, Pulse Width L 5 A 0 - - 5 - - 30 - - ns B H 0 - - 5 - - 30 - - ns R L 0 - - 5 - - 30 - - ns A and B Hold Time t H 5 10 - - 13 - - 15 - - ns Reset Removal Time t REM 5 10 - - 13 - - 15 - ns Retrigger Time Number (Note ) R X = 10KΩ, C X = 0 t rt 5-50 - - 3 - - 7 - ns Output Pulse Width Q or Q 5 0-50 38.7-51.3 38. - 51.8 µs R X = 10KΩ, C X = 10nF NOTE:. Time to trigger depends on the values of R X and C X. The output pulse width can only be extended when the time between the activegoing edges of the trigger input pulses meet the minimum retrigger time requirement. - 5
CD5/7HC13, CD5/7HCT13, CD7HC3, CD7HCT3 Switching Specifications C L = 50pF, Input t r, t f = ns, R X = 10KΩ, C X = 0 PARAMETER SYMBOL TEST CONDITIONS (V) 5 o C -0 o C TO 85 o C -55 o C TO 15 o C MIN TYP MAX MIN MAX MIN MAX HC TYPES Trigger Propagation Delay t PHL C L = 50pF A, B, R to Q - - 300-375 - 50 ns.5 - - 0-75 - 90 ns C L = 15pF 5-5 - - - - - ns C L = 50pF - - 51 - - 7 ns A, B, R to Q t PHL C L = 50pF - - 30-00 - 80 ns.5 - - - 80-9 ns C L = 15pF 5 - - - - - - ns C L = 50pF - - 5-8 - 8 ns Reset Propagation Delay t PHL, t PLH C L = 50pF - - 15-70 - 35 ns R to Q or Q.5 - - 3-5 - 5 ns - - 37 - - 55 ns Output Transition Time t THL, t TLH C L = 50pF - - 75-95 - 110 ns.5 - - 15-19 - ns - - 13-1 - 19 ns Output Pulse Width - - 5 R X = 10KΩ, C X = 10pF - 5 - - - - - µs Pulse Width Match Between Circuits In the Same Package - - 5 R X = 10KΩ, C X = 10pF - ± - - - - - % Power Dissipation Capacitance (Notes 5, ) C PD C L = 15pF 5 - - - - - - - pf Input Capacitance C IN C L = 50pF - 10-10 - 10-10 pf NOTES: 5. C PD is used to determine the dynamic power consumption, per multivibrator.. P D =(C PD +C X )V CC fi (C L V CC fo ) where f i = input frequency, f O = Output Frequency, C L = Output Load Capacitance, C X = External Capacitance = Supply assuming f i «I ------
CD5/7HC13, CD5/7HCT13, CD7HC3, CD7HCT3 Test Circuits and Waveforms A A B R tw B = LOW A = HIGH B R B = LOW A = HIGH Q Q FIGURE 1. OUTPUT PULSE CONTROL USING RESET INPUT (R) PULSE FOR 13 FIGURE. OUTPUT PULSE CONTROL USING RESET INPUT (R) FOR 3 A B B A t rt (R = HIGH) Q NOTE: Output pulse control using retrigger pulse for 13 and 3. FIGURE 3. TRIGGERING OF ONE SHOT BY INPUT A OR INPUT B FOR A PERIOD OUTPUT PULSE WIDTH (µs) 8 10 3 8 10 8 10 1 8 R X = 100kΩ R X = 10kΩ DC SUPPLY VOLTAGE ( ) = 5V AMBIENT TEMPERATURE (T A ) = 5 o C 8 10 3 10 8 8 8 10 5 10 10 7 EXTERNAL CAPACITANCE (C X ) - pf K FACTOR 0.9 0.8 0.7 0. 0.5 0. 0.3 0. EXTERNAL CAPACITANCE (C X ) = 10nF EXTERNAL RESISTANCE (R X ) = 10kΩ TO 100kΩ AMBIENT TEMPERATURE (T A ) = 5 o C HCT 0.1 1 3 5 7 8 9 10 11 DC SUPPLY VOLTAGE ( ) - VOLTS FIGURE. TYPICAL OUTPUT PULSE WIDTH AS A FUNCTION OF C X FOR R X = 10kΩ AND 100kΩ FIGURE 5. TYPICAL K FACTOR AS A FUNCTION OF 7
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