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Dual N-Channel.V Specified PowerTrench MOSFET July 3 General Description These N-Channel.V specified MOSFETs use Fairchild Semiconductor s advanced PowerTrench process. It has been optimized for power management applications with a wide range of gate drive voltage (.V V). Applications Features 6. A, V. R DS(ON) = 3 mω @ V GS =. V R DS(ON) = 3 mω @ V GS =. V. Optimized for use in battery protection circuits Low gate charge Battery protection Load switch Power management 6 7 8 Q Q 3 Absolute Maximum Ratings TA= o C unless otherwise noted Symbol Parameter Ratings Units V DSS Drain-Source Voltage V V GSS Gate-Source Voltage ± I D Drain Current Continuous (Note a) 6. A P D Pulsed Power Dissipation for Dual Operation Power Dissipation for Single Operation (Note a).6 (Note b) (Note c).9 T J, T STG Operating and Storage Junction Temperature Range to + C Thermal Characteristics R θja Thermal Resistance, Junction-to-Ambient (Note a) 78 C/W R θjc Thermal Resistance, Junction-to-Case (Note ) Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity 3 mm units W 3 Fairchild Semiconductor Corp. Rev E (W)

Electrical Characteristics T A = C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV DSS Drain Source Breakdown Voltage V GS = V, I D = µa V BVDSS Breakdown Voltage Temperature I T J Coefficient D = µa, Referenced to C mv/ C I DSS Zero Gate Voltage Drain Current V DS = 6 V, V GS = V µa I GSS Gate Body Leakage V GS = ±8 V, V DS = V ± na On Characteristics (Note ) V GS(th) Gate Threshold Voltage V DS = V GS, I D = µa.6. V VGS(th) T J R DS(on) Gate Threshold Voltage Temperature Coefficient Static Drain Source On Resistance I D = µa, Referenced to C V GS =. V, I D = 6. A V GS =. V, I D =. A V GS =. V, I D =6.A, T J= C 3 mv/ C I D(on) On State Drain Current V GS =. V, V DS = V A g FS Forward Transconductance V DS = V, I D = 6. A S Dynamic Characteristics C iss Input Capacitance V DS = V, V GS = V, 6 pf C oss Output Capacitance f =. MHz pf C rss Reverse Transfer Capacitance 3 3 3 3 mω 8 pf R G Gate Resistance V GS = mv, f =. MHz. Ω Switching Characteristics (Note ) t d(on) Turn On Delay Time V DD = V, I D = A, 8 6 ns t r Turn On Rise Time V GS =. V, R GEN = 6 Ω 9 7 ns t d(off) Turn Off Delay Time 6 ns t f Turn Off Fall Time 9 ns Q g Total Gate Charge V DS = V, I D = 3 A, 6. 9 nc Q gs Gate Source Charge V GS =. V. nc Q gd Gate Drain Charge.7 nc Drain Source Diode Characteristics and Maximum Ratings V SD Drain Source Diode Forward Voltage V GS = V, I S =.3 A (Note ).73.3 V t rr Diode Reverse Recovery Time I F = 6. A, d if/d t = A/µs ns Q rr Diode Reverse Recovery Charge nc Notes:. R θja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θjc is guaranteed by design while R θca is determined by the user's board design. a) 78 /W when mounted on a.in pad of oz copper b) /W when mounted on a. in pad of oz copper c) 3 /W when mounted on a minimum pad. Scale : on letter size paper. Pulse Test: Pulse Width < 3µs, Duty Cycle <.% Rev E (W)

Typical Characteristics V GS =.V.V 6 3. 3.V 8.V R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE...8.6.. V GS =.V.V 3.V 3.V.V.V.. V DS, DRAIN TO SOURCE VOLTAGE (V) Figure. On-Region Characteristics..8 I D, DIRAIN CURRENT (A) Figure. On-Resistance Variation with Drain Current and Gate Voltage. R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE.6...8 I D = 6.A V GS =.V R DS(ON), ON-RESISTANCE (OHM)..9.7..3 T A = o C T A = o C I D = 3.A.6 - - 7 T J, JUNCTION TEMPERATURE ( o C) Figure 3. On-Resistance Variation with Temperature.. 3 V GS, GATE TO SOURCE VOLTAGE (V) Figure. On-Resistance Variation with Gate-to-Source Voltage. V DS = V T A = - o C o C o C I S, REVERSE DRAIN CURRENT (A)... V GS = V T A = o C o C - o C.. 3 V GS, GATE TO SOURCE VOLTAGE (V)....6.8. V SD, BODY DIODE FORWARD VOLTAGE (V) Figure. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. Rev E (W)

Typical Characteristics V GS, GATE-SOURCE VOLTAGE (V) I D = 3 A V DS = V V V 3 3 6 7 8 Q g, GATE CHARGE (nc) Figure 7. Gate Charge Characteristics. CAPACITANCE (pf) 8 6 C rss C oss C iss V DS, DRAIN TO SOURCE VOLTAGE (V) f = MHz V GS = V Figure 8. Capacitance Characteristics.. R DS(ON) LIMIT V GS =.V R θja = 3 o C/W T A = o C ms ms ms s s DC... V DS, DRAIN-SOURCE VOLTAGE (V) µs P(pk), PEAK TRANSIENT POWER (W) 3 R θja = 3 C/W T A = C... t, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE.. D =........... t, TIME (sec) R θja (t) = r(t) * R θja R θja = 3 o C/W P(pk) t t T J - T A = P * R θja (t) Duty Cycle, D = t / t Figure. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note c. Transient thermal response will change depending on the circuit board design. Rev E (W)

TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx ActiveArray Bottomless CoolFET CROSSVOLT DOME EcoSPARK E CMOS TM EnSigna TM FACT DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms FACT Quiet Series FAST FASTr FRFET GlobalOptoisolator GTO HiSeC I C ImpliedDisconnect ISOPLANAR Across the board. Around the world. The Power Franchise Programmable Active Droop LittleFET MICROCOUPLER MicroFET MicroPak MICROWIRE MSX MSXPro OCX OCXPro OPTOLOGIC OPTOPLANAR PACMAN POP Power7 PowerTrench QFET QS QT Optoelectronics Quiet Series RapidConfigure RapidConnect SILENT SWITCHER SMART START SPM Stealth SuperSOT -3. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Datasheet Identification Product Status Definition SuperSOT -6 SuperSOT -8 SyncFET TinyLogic TINYOPTO TruTranslation UHC UltraFET VCX Advance Information Preliminary No Identification Needed Formative or In Design First Production Full Production This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I