A 24-Channel 300 Gb/s 8.2 pj/bit Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single Holey CMOS IC A. Rylyakov, C. Schow, F. Doany, B. Lee, C. Jahnes, Y. Kwark, C.Baks, D. Kuchta, J. Kash IBM T.J. Watson Research Center, Yorktown Heights, NY 1
Goal: Motivation Develop technologies enabling Terabit/s-class, highdensity, low-power, board/backplane-level optical interconnect. Key features of this work: single holey CMOS IC with 24 TX and 24 RX channels 850 nm PD and VCSEL arrays flip-chip attached to the IC wafer-level process for optical via fabrication dual-lens system for relaxed tolerances, efficient coupling 2
Transceiver Optical Module Fully functional 24+24 channel 850-nm optical transceiver based on holey CMOS IC have been packaged into pluggable module and characterized to 12.5Gb/s/ch. 4 x 12 array of 50/80 µm MMF Holey Optochip Lens arrays 4x12 MT LDD TIA V PD Organic carrier PGA Connector Optical vias in CMOS IC Test Mother Board 3
Optical Module Components GaP lens arrays CMOS IC CoreEZ 4x12 MT Organic carrier LDD V PD TIA Pin Grid Array 50/80um Fiber Arrays PGA Connector Test Mother Board 4
Transmitter Circuit Architecture V DD_PA V DD_OS V DD_LD x1 x2 x3 x4 x5 R L2 M 1 M 2 R L1 L1 VCSEL I 0 I LD common-anode VCSEL connection for low power series inductor peaking at the output 0.027 mm 2 (90 nm CMOS) single channel performance*: 12 mw,15 Gb/s, BER < 10-12 maximum speed: 20 Gb/s (67 mw, BER < 10-12 ) *B. G. Lee et al., Low-power CMOS-driven transmitters and receivers, Conf. Lasers and Electro-Optics, San Jose, CA, May 2010 5
Receiver Circuit Architecture V DD_TIA V DD_LA V DD_IO PD TIA Predriver _ LA Output Buffer Chip Boundary Transimpedance Amplifier V DD_TIA 5 stages Cherry-Hooper LA V DD_LA Output Buffer V DD_IO L L L L R 1 R 3 R 2 R 2 R 3 R 1 R L R L V PD R L R L V out + V out + V out + I IN R PD C AC L IN V - out R L F F L F R F M 1 M 2 V in + M 3 M 4 M 1 M 2 V out - V in + V in - V out - M 1 M 2 R PD C AC L IN I 1 V in - I 1 I 2 I 1 0.056 mm 2 (90 nm CMOS) single channel performance: 36 mw,15 Gb/s, BER < 10-12 6
Optochip Assembly Bottom view: RIE vias (wafer-scale processing) Optochips assembled with high yield Wafer-scale processing: RIE for optical vias Ni-Au plating for bond pads New high-speed VCSEL and PD arrays* PDs VCSELs *N. Li et al., High-Performance 850 nm VCSEL and Photodetector Arrays for 25 Gb/s Parallel Optical Interconnects, Optical Fiber Communication Conference OFC 2010, paper OTuP2, San Diego, CA, Mar. 21-25, 2010. 7
Optochip-Organic carrier-pga Connector Injection Molded Solder (IMS) for Optochip attachment to CoreEZ BGA solder reflow for CoreEZ to PGA Connector Attach 8
Electrical/Optical Characterization Fully assembled Optomodules plugged into test motherboard Optical Fiber Probe Optomodule under test Electrical high-speed input/output 9
DC Characterization Fully functional Holey Optomodule 6.5 µm diameter VCSEL 30 µm diameter photodiodes Uniform performance across all channels Average TX output power Photodiode Responsivity 10
High-Speed Characterization: Transmitters 240 to 300 Gb/s aggregate data rate 24 Channels at 10 Gb/s and 12.5 Gb/s Power dissipation: 35 mw per channel ( 2.8 pj/bit at 12.5 Gb/s) Uniform modulated output power for all channels (same vertical scale) 11
High-Speed Characterization: Receivers 25 µm diameter photodiodes 24 Channels at 10 Gb/s and 12.5 Gb/s Power dissipation: 68 mw per channel ( 5.4 pj/bit at 12.5 Gb/s) 12
Receiver Sensitivity Optomodule with 30 µm photodiodes Sensitivity curves for 6 receiver channels at data rates 7.5 Gb/s and 10 Gb/s. Less than 1dB spread in sensitivity 7.5 Gb/s 10 Gb/s 13
High-Speed Characterization Typical TX and RX channels at various data rates Good performance up to 12.5 Gb/s Some degradation at 15 Gb/s 14
Dual-Lens optical system lensed 4 x 12 channel fiber connector with GaP lens Holey Optomodule with GaP lens uniform coupling efficiency for ±35µm offsets T O C ouplin g Transmitter Optical Coupling 0 uniform coupling efficiency for greater than ±50µm offsets Receiver Optical Coupling Reciever Optical Coupling 0 Normalized Power (d -2-4 -6 Normalized Power (d -2-4 -6-8 -8-10 -10 0-75 -5 0-25 0 2 5 50 75 100 Offset (um) -10-100 -75-50 -25 0 2 5 50 75 100 Offset (um) 15
Summary Novel package leveraging Standard digital 90nm IBM bulk CMOS process Straightforward wafer-scale postprocessing Direct flip-chip attachment of commercial 850 nm O/Es Complete Optomodule demonstrated Pluggable PGA connector Fully connectorized test board Dual-lens 4 x 12 channel optical system for efficient coupling with relaxed tolerances High-speed 300 Gb/s bi-directional aggregate bandwidth Up to 20 Gb/s TX, 15 Gb/s RX single channel test sites Low power 2.47 W ( 8.2 pj/bit at 300 Gb/s) 12 mw ( 0.8 pj/bit at 15 Gb/s) single channel TX 36 mw ( 2.4 pj/bit at 15 Gb/s) single channel RX Compact fully-packaged module is about 2 x 2 cm 2 directly coupled to low-bend radius 50/80 µm MMF Aggregate 300-Gb/s bi-drectional data rate is highest reported for single-chip CMOS transceiver modules 16