Dependable Texas Instruments Quality and Reliability description These devices contain six independent inverters. SN404, SN4LS04, SN4S04, SN404... J PACKAGE SN4LS04, SN4S04... J OR W PACKAGE SN7404... D, N, OR NS PACKAGE SN74LS04... D, DB, N, OR NS PACKAGE SN74S04... D OR N PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y 1 2 3 4 6 7 14 13 12 11 10 9 8 V CC 6A 6Y A Y 4A 4Y SN404... W PACKAGE (TOP VIEW) 1A 2Y 2A V CC 3A 3Y 4A 1 2 3 4 6 7 14 13 12 11 10 9 8 1Y 6A 6Y Y A 4Y SN4LS04, SN4S04... FK PACKAGE (TOP VIEW) 2A 2Y 3A 1Y 1A 3 4 2 1 20 19 18 6 7 17 16 1 8 14 9 10 11 12 13 3Y 4Y 4A 6A 6Y A Y No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated On products compliant to MIL-PRF-383, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 6303 DALLAS, TEXAS 726 1
TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN7404N SN7404N PDIP N Tube SN74LS04N SN74LS04N Tube SN74S04N SN74S04N Tube SN7404D 7404 Tube SN74LS04D 0 C to 70 C SOIC D Tape and reel SN74LS04DR SOP NS Tube Tape and reel SN74S04D SN74S04DR LS04 S04 Tape and reel SN7404NSR SN7404 Tape and reel SN74LS04NSR 74LS04 SSOP DB Tape and reel SN74LS04DBR LS04 CDIP J Tube SN404J SN404J Tube SNJ404J SNJ404J Tube SN4LS04J SN4LS04J Tube SN4S04J SN4S04J Tube SNJ4LS04J SNJ4LS04J C to 12 C Tube SNJ4S04J SNJ4S04J Tube SNJ404W SNJ404W CFP W Tube SNJ4LS04W SNJ4LS04W Tube SNJ4S04W SNJ4S04W Tube SNJ4LS04FK SNJ4LS04FK LCCC FK Tube SNJ4S04FK SNJ4S04FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUTION TABLE (each inverter) INPUT A H L OUTPUT Y L H 2 POST OFFICE BOX 6303 DALLAS, TEXAS 726
logic diagram (positive logic) 1A 1Y 2A 2Y 3A 3Y 4A 4Y A Y 6A 6Y Y = A POST OFFICE BOX 6303 DALLAS, TEXAS 726 3
schematics (each gate) 04 4 kω 1.6 kω 130 Ω A Y 1 kω LS04 S04 20 kω 8 kω 120 Ω 2.8 kω 900 Ω 0 Ω A 4 kω Y A 3. kω Y 12 kω 3 kω 00 Ω 20 Ω 1. kω Resistor values shown are nominal. 4 POST OFFICE BOX 6303 DALLAS, TEXAS 726
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note 1)............................................................. 7 V voltage, V I : 04, S04................................................................. V LS04..................................................................... 7 V Package thermal impedance, θ JA (see Note 2): D package................................... 86 C/W DB package................................. 96 C/W N package................................... 80 C/W NS package................................. 76 C/W Storage temperature range, T stg................................................... 6 C to 10 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 1-7. recommended operating conditions SN404 SN7404 MIN NOM MAX MIN NOM MAX Supply voltage 4.. 4.7.2 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current 0.4 0.4 ma IOL Low-level output current 16 16 ma TA Operating free-air temperature 12 0 70 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN404 SN7404 MIN TYP MAX MIN TYP MAX VIK = MIN, II = 12 ma 1. 1. V = MIN, VIL = 0.8 V, IOH = 0.4 ma 2.4 3.4 2.4 3.4 V = MIN, VIH = 2 V, IOL = 16 ma 0.2 0.4 0.2 0.4 V II = MAX, VI =. V 1 1 ma IIH = MAX, VI = 2.4 V 40 40 µa IIL = MAX, VI = 0.4 V 1.6 1.6 ma IOS V CC = MAX 20 18 ma ICCH = MAX, VI = 6 12 6 12 ma IC = MAX, VI = 4. V 18 33 18 33 ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at = V, TA = 2 C. Not more than one output should be shorted at a time. switching characteristics, V CC = V, T A = 2 C (see Figure 1) FROM TO TEST CONDITIONS (INPUT) (OUTPUT) A Y = 400 Ω, =1pF SN404 SN7404 MIN TYP MAX 12 22 8 1 ns POST OFFICE BOX 6303 DALLAS, TEXAS 726
recommended operating conditions SN4LS04 SN74LS04 MIN NOM MAX MIN NOM MAX Supply voltage 4.. 4.7.2 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current 0.4 0.4 ma IOL Low-level output current 4 8 ma TA Operating free-air temperature 12 0 70 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN4LS04 SN74LS04 MIN TYP MAX MIN TYP MAX VIK = MIN, II = 18 ma 1. 1. V = MIN, VIL = MAX, IOH = 0.4 ma 2. 3.4 2.7 3.4 V = MIN, VIH =2V IOL = 4 ma 0.2 0.4 0.4 IOL = 8 ma 0.2 0. II = MAX, VI = 7 V 0.1 0.1 ma IIH = MAX, VI = 2.7 V 20 20 µa IIL = MAX, VI = 0.4 V 0.4 0.4 ma IOS V CC = MAX 20 100 20 100 ma ICCH = MAX, VI = 1.2 2.4 1.2 2.4 ma IC = MAX, VI = 4. V 3.6 6.6 3.6 6.6 ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at = V, TA = 2 C. Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second. switching characteristics, V CC = V, T A = 2 C (see Figure 2) V FROM TO TEST CONDITIONS (INPUT) (OUTPUT) A Y =2kΩ kω, =1pF SN4LS04 SN74LS04 MIN TYP MAX 9 1 10 1 ns 6 POST OFFICE BOX 6303 DALLAS, TEXAS 726
recommended operating conditions SN4S04 SN74S04 MIN NOM MAX MIN NOM MAX Supply voltage 4.. 4.7.2 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current 1 1 ma IOL Low-level output current 20 20 ma TA Operating free-air temperature 12 0 70 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN4S04 SN74S04 MIN TYP MAX MIN TYP MAX VIK = MIN, II = 18 ma 1.2 1.2 V = MIN, VIL = 0.8 V, IOH = 1 ma 2. 3.4 2.7 3.4 V = MIN, VIH = 2 V, IOL = 20 ma 0. 0. V II = MAX, VI =. V 1 1 ma IIH = MAX, VI = 2.7 V 0 0 µa IIL = MAX, VI = 0. V 2 2 ma IOS V CC = MAX 40 100 40 100 ma ICCH = MAX, VI = 1 24 1 24 ma IC = MAX, VI = 4. V 30 4 30 4 ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at = V, TA = 2 C. Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second. switching characteristics, V CC = V, T A = 2 C (see Figure 1) FROM TO TEST CONDITIONS (INPUT) (OUTPUT) A Y = 280 Ω, =1pF SN4S04 SN74S04 MIN TYP MAX 3 4. 3 ns A Y = 280 Ω, =0pF 4. ns POST OFFICE BOX 6303 DALLAS, TEXAS 726 7
MEASUREMENT INFORMATION SERIES 4/74 AND 4S/74S DEVICES From Under (see Note B) From Under From Under 1 kω S1 (see Note B) S2 FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS High-Level Pulse Low-Level Pulse tw PULSE DURATIONS Timing Data tsu 1. V th SETUP AND HOLD TIMES Control (low-level enabling) tpzl tplz In-Phase (see Note D) Out-of-Phase (see Note D) PROPAGATION DELAY TIMES Waveform 1 (see Notes C and D) Waveform 2 (see Notes C and D) tpzh 1. V 1. V + 0. V tphz 1. V 0. V 1. V ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for,, tphz, and tplz; S1 is open and S2 is closed for tpzh; S1 is closed and S2 is open for tpzl. E. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 0 Ω; tr and tf 7 ns for Series 4/74 devices and tr and tf 2. ns for Series 4S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 6303 DALLAS, TEXAS 726
MEASUREMENT INFORMATION SERIES 4LS/74LS DEVICES SN404, SN4LS04, SN4S04, From Under (see Note B) From Under From Under kω S1 (see Note B) S2 FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS High-Level Pulse Low-Level Pulse 1. 1. tw 1. 1. PULSE DURATIONS Timing Data tsu 1. th 1. 1. SETUP AND HOLD TIMES 1. 1. Control (low-level enabling) tpzl 1. 1. tplz In-Phase (see Note D) Out-of-Phase (see Note D) PROPAGATION DELAY TIMES 1. 1. 1. 1. Waveform 1 (see Notes C and D) Waveform 2 (see Notes C and D) NOTES: A. includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for,, tphz, and tplz; S1 is open and S2 is closed for tpzh; S1 is closed and S2 is open for tpzl. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 0 Ω, tr 1. ns, tf 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. tpzh 1. Figure 2. Load Circuits and Voltage Waveforms 1. + 0. V tphz 1. V 0. V 1. V ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS POST OFFICE BOX 6303 DALLAS, TEXAS 726 9