Exercises: Fundamentals of Computer Engineering PAGE: Exercise Minimise the following using the laws of Boolean algebra. f = a + ab + ab.2 f ( ) ( ) ( ) 2 = c bd + bd + ac b + d + cd a + b + ad( b + c) + ab In each case, show the circuit diagram of the minimised function. Exercise 2 Express the function y = abd + c + acd + b as the complete disjunctive normal form: 2. by applying Boole's theorerm, 2.2 producing a function table. I I I Exercise 3 The following truth table is given. A B C X I I I I I I I I I I I I I I I I 3. Express the function as the complete disjunctive normal form. 3.2 Express the function as the complete conjunctive normal form. 3.3 Suggest a circuit solution for the complete disjunctive normal form. 3.4 Suggest a circuit solution for the complete conjunctive normal form.
Exercises: Fundamentals of Computer Engineering PAGE: 2 Exercise 4 Given is the following digital circuit. 4. What is the circuits function y = f(a,b,c,d)? 4.2 Transform y into the CDNF. 4.3 Give the truth table for y CDNF. 4.4 Draw the circuit for the CDNF as derived from 4.2 and 4.3 4.5 Compare the two implementations Exercise 5 Given in the following digital circuit and its input sequence. Assume delay time for all gates is 2 ns. X,X2 5. Analyze the logical function of the circuit 5.2 Complete the given timing diagram 5.3 Does the circuit produce any Hazards for the given input sequence? X3 X4 Y,Y2 Y 3 Y4 Y
Exercises: Fundamentals of Computer Engineering PAGE: 3 Exercise 6 6. X = A + A + A + A 6.2 Y = A D + A D + A D + A D + A D + A D 6.3 f K = ( A + B + C) ( A + B + C) ( A + B + C) 6.4 Use a KV map to minimize the function given through the following truth table and by using don t cares. A B C D Y Exercise 7 Given is the circuit in fig. 7. and its timing diagram in fig. 7.2. fig. 7. 7. Analyse the circuits function and its timing behaviour 7.2 Fill in the KV-Map for the given circuit 7.3 Explain the timing diagram by means of the KV-Map 7.4 Construct a hazard-free implementation from the KV-Map fig. 7.2
Exercises: Fundamentals of Computer Engineering PAGE: 4 Exercise 8 Convert the following numbers: 8. N = 9,375 N 2 8.2 N = 27,375 N 4 8.3 N 2 = I I I I,I I N 8, N 6 Exercise 9 Voltage values in the range of -2 mv to +2 mv need to be represented precisely to an accuracy of mv. 9. State the minimum number of positions necessary for a representation in two s-complement. 9.2 Which number range is covered by usage of this format? Now a floating point representation is considered 9.3 State the minimum number of positions necessary for a floating-point representation without loss of accuracy. The mantissa and exponent are represented as a dual complement. 9.4 Which number range is covered by usage of this floating point format? Exercise Given is the following floating point format In this format is VZ:=Sign Bit, where positive numbers are represented by VZ= and negative numbers being represented by VZ=. Characteristic:= the exponent increased by 64. Therefore, E =Charakteristik - 64. In case that all bits of the mantissa are equal to, the number is represented. In case that at least one bit of the mantissa equals to, the following number is represented:. Which kind of normalisation is used?.2 Which range is covered by this format. What is - the biggest and the smallest possible positive numbers - the biggest and the smallest possible negative number Give these numbers as decimal numbers as well as the corresponding bit pattern of the given floating point format..3 State the changes in case that the mantissa will be reduced by one bit and that bit is added to the characteristic..4 State the changes in case that the characteristic is directly used as exponent E (without substraction of 64).5 Compare the format given by.3 with IEEE-754 format Exercise The following numbers shall be represented in IEEE-754-single precision format.. x = -6,5.2 x=,875.3 x=. 2?
Exercises: Fundamentals of Computer Engineering PAGE: 5 Exercise 2 2. Add the ternary numbers (B=3) N = 22,22 N 2 = 2,2 2.2 Multiply N 2 = I I I, I N 2 2 = I I, I 2.3 Complete a binary calculation as a dual complement, whereby z = 8 places. 7 + 2 and 7 + 8 2. 7-2 and 7-8 3. -8-2 and -8-8 Exercise 3 The following binary floating-point format is given: S Exp.(Char.) Mantissa 5 4 9 8 Mantissa accuracy is bits! The exponent is represented as a characteristic (C=32) 3. Why can the mantissa be represented with 9 bits (without positive/negative number sign)? 3.2 Complete the subtraction A-B in this format when A = 46528 B = 6696 Check your result against that of a decimal control calculation. Exercise 4 Convert 3-bit binary digits into Gray's code. 4. State the calculation rules for conducting such a conversion. 4.2 State a program sequence plan for completing this conversion with software. 4.3 Suggest a circuit solution. Exercise 5 Design a code converter for converting Aiken into DCD code (Dual Coded Decimal).
Exercises: Fundamentals of Computer Engineering PAGE: 6 Exercise 6 Design a combinational circuit with 4 input lines (x3, x2, x, x) and one output line y. Output shall be high when checksum of the input lines equals to 2 6. Give the truth table for this function 6.2 Realize the function with one MUX. (It can be assumed that also the inverted input signals are available) 6.3 Realise the same function, but now only with 2:-Multiplexers. helping Tables x4 x3 x2 x y x4 x3 x2 x y I I 2 I I 3 I I I I 4 I I 5 I I I I 6 I I I I 7 I I I I I I 8 I I 9 I I I I I I I I I I I I I I 2 I I I I 3 I I I I I I 4 I I I I I I 5 I I I I I I I I I I I2 I3 I4 I5 I6 I7 x3 x2 x Y
Exercises: Fundamentals of Computer Engineering PAGE: 7 Split table in x4= and x4=i 2 3 4 5 6 7 x3 x2 x Y x3 x2 x Y ---------------------------------------------------------------------------------------------------------------------- x2 x Y x2 x Y x2 x Y x2 x Y ------------------------------------------------------------------------------------------------------------------------ x Ya x Yb x Y x Yb x Ya x Yb x Ya x Yb
Exercises: Fundamentals of Computer Engineering PAGE: 8 Exercise 7 Given is the following Circuit Let A and B be the input lines and C and D the control lines. With the help of C and D, logical functions of A and B can be selected. Assume D=, C= selects the first MUX-Input line, D=, C=I the 2nd input line, and so on. 7. Give the truth table for the output y 7.2 Minimize the output function 7.3 Draw the minimized circuit Exercise 8 Given the following circuit: 8. State the DNF for x and y. 8.2 Give the circuits truth table. 8.3 Suggest a possible application for the circuit.
Exercises: Fundamentals of Computer Engineering PAGE: 9 Exercise 9 Given the following circuits, Examine their 9. logical behaviour (truth table). 9.2 ideal-typical electrical behaviour (impulse diagram). Exercise 2 Analyse the circuit given in figure 2.. In doing so, cut off the marked line and produce a new input q. figure 2. 2. Give the truth table of the combinational circuit after you cut off the line. 2.2 Mark stable and unstable states in the truth table. 2.3 Which device is implemented by the given circuit? Now the circuit in figure 2. is enhanced by two additional gates as shown in figure 2.2 figure 2.2 2.4 Produce the truth table for the circuit given in figure 2.2. 2.5 Which device is implemented by the circuit given in figure 2.2? 2.6 Describe the function of the input signal x3. Now analyse the circuit given in figure 2.3. Use the former results from this task?
Exercises: Fundamentals of Computer Engineering PAGE: figure 2.3 2.7 Which implementation strategy applies to the circuit given in figure 2.3? Exercise 2 Given are the timing diagrams of the input signals clk, d, s, r, j and k. 2. Name and describe the shown elements 2.2 Complete the timing diagrams
Exercises: Fundamentals of Computer Engineering PAGE: Exercise 22 22. Determine the characteristic equation of a D-Flip Flop and a JK-Flip Flop. 22.2 How must a JK flip-flop be switched to turn it into a D flip-flop? Exercise 23 Given the following sequential circuit (automaton): 23. what type of state machine is it? (Give reason) 23.2 determine the coded state table for this circuit. 23.3 determine the general (non-coded) state table for this circuit. 23.4 minimise the state table. 23.5 draw the state transition diagram of the minimised state machine. 23.6 construct the functionally identical minimised state machine as a sequential circuit. Exercise 24 Design a synchronous Aiken-code ring counter.